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CLICpix2 Design Status
Pierpaolo Valerio & Edinei Santin
CLICdp Vertex Meeting - September 24th 2015
Digital Design Part
Pierpaolo Valerio
Digital Signals Delay Maximum delay of data signal from the pixel matrix
measured from the edge of the input clock is: ~3.4 ns if VDD = 1.0V ~1.6 ns if VDD = 1.2V
3
Corner choice This is true for the Worst corner, which is very pessimistic:
Slow/Slow process, 125 °C, -10% VDD If the delay is bigger than a clock period, it becomes
impossible to implement a fully synchronous readout In CLICpix1 it worked because the columns were “self-
managing” the readout algorithm. It can’t work in CLICpix2
The solution is to characterize the design at 1.2V (with a < 20% increase in digital power consumption) and then reduce the voltage during the tests as the chips won’t have to work at the worst corner
4
Ongoing implementation
The end-of-column block is now implemented and it correctly meets the timing specifications
5
Path 1: MET Setup Check with Pin u/out_reg/CP Endpoint: u/out_reg/D (^) checked with leading edge of 'clkin_divided'Beginpoint: datain_column (^) triggered by leading edge of 'clkout'Analysis View: av_maxOther End Arrival Time 0.325- Setup 0.080+ Phase Shift 3.125+ CPPR Adjustment 0.001- Uncertainty 0.150= Required Time 3.221- Arrival Time 2.132= Slack Time 1.089
Output Serializer The Double Data Rate serializer was implemented,
allowing for 640 Mbit/s data output
6
Ethernet IDLE sequence
Status of the digital design
Other improvements: Large code cleanup All reset signals are now synchronous, to avoid possible
glitches Reorganization of control registers in more logical groups:
Readout control Global configuration
To do: Place and route the rest of the periphery Validate the timing analysis with extracted simulations
7
Analog Design Part
Edinei Santin
Outline (cf. DR checklist)
Periphery buffers stability, DC gain, and offset voltage Test pulse circuitry simulation with switching overlapping
and varying pixels load Cascode current mirrors at periphery DACs outputs Bandgap IP integration (preliminary) Resolution adjustment for Ikrum and one of the test pulse
DACs
9
Biasing/reference lines capacitive loading
10
Signal
Cgg,devices [pF]
Crouting* [pF] Total
[pF]per pixel matrix per 2-column matrix
Vbpcsa 0.0134 219.55 1.36 88.40 307.95
Vcpcsa 0.0011 18.02 1.36 88.40 106.42
Vbpikrum 0.0797 1305.80 1.85 120.25 1426.05
Vfbk 0.0239 391.58 2.33 151.45 543.03
Vt1 0.0112 183.50 1.31 85.15 268.65
Vt2 0.0112 183.50 1.12 72.80 256.30
Vbncomp 0.0316 517.73 1.23 79.95 597.68
Vbpcomp 0.0225 368.64 1.46 94.90 463.54
Vth 0.0244 399.77 0.91 59.15 458.92
Vbpcaldac 0.0737 1207.50 1.51 98.15 1305.65
Vcpcaldac 0.0228 373.56 1.61 104.65 478.21
Vcncaldac 0.0071 116.33 1.67 108.55 224.88* Periphery routing excluded.
Biasing/reference lines leakage current
11
SignalIleak*
per pixel (nom / max**) [pA] matrix [nA]
Vbpcsa 5.35 / 28.50 87.7 / 466.9
Vcpcsa 1.87 / 140.00 30.6 / 2293.8
Vbpikrum 4.35 / 247.50 71.3 / 4055.0
Vfbk 1.86 / 225.00 30.5 / 3686.4
Vt1 ~ 0 / 0 ~ 0 / 0
Vt2 ~ 0 / 0 ~ 0 / 0
Vbncomp 6.13 / 1312.50 100.4 / 21504.0
Vbpcomp 2.79 / 62.50 45.7 / 1024.0
Vth 2.93 / 1715.00 48.0 / 28098.6
Vbpcaldac 1.77 / 312.50 29.0 / 5120.0
Vcpcaldac 3.70 / 125.00 60.6 / 2048.0
Vcncaldac 3.03 / 1050.00 49.6 / 17203.2 * Strongly dependent on biasing.** ‘max’ means Ileak,den∙Agate for the worst (but unrealistic) bias condition (i.e. |Vg - Vd,s,b| = Vdd).
Biasing/reference lines model
12
Approximated model for the biasing/reference lines including parasitic RC elements and leakage current The capacitance and leakage current vary from line to line since they depend on the devices connected
to the respective lines. The resistance does not vary much because the lines are equally sized (R route,2col ~ 181.6 Ω).
The periphery routing (Rs & Rup) has an important impact on the buffers response
Accounts for bias dependence
Buffer stability vs CL & Rs/Rup
13
The resistance Rs has a strong influence on the stability of the buffers. It creates a left-half plane (LHP) zero at wz = 1/(RsCL) which improves the phase margin as the zero is pushed to lower frequencies.
Approximately the same holds for Rup, but to avoid different potential through the columns this resistance needs to be minimized (i.e. it cannot be unrestricted sized up). Hence, the main parameter to set wz becomes Rs.
Buffer stability vs CL & Rs at # Ileak
14
The leakage current has a very minor impact on the phase margin, even considering that the nominal I leak is increased by a factor of 10 to account for bias dependence
Buffer DC gain & fu
15
As expected, the DC gain is constant and ~ 64 dB. The unit-gain frequency, fu, has a minimum value of ~ 600 kHz and a maximum ~ 16 MHz for varying CL and Rs values.
Buffer offset voltage
16
For nominal conditions, the buffer has a systematic offset voltage of ~ 1.8 mV and a sigma of ~ 1.2 mV
Buffer summary
17
It was kept the same topology of the previous design, i.e., a two-stage Miller compensated amplifier
Same buffer sizing for all biasing/reference lines. Good phase margins (> 45°) achieved by controlling the Rs values via the periphery routing.
Considering a worst leakage current of 1 µA, the voltage drop due to Rs is ~ 1 mV. However, this can be seen as offset, since it affects all the columns equally.
Test pulses with tpsw/tpswn overlapping
18
States 2 and 4 may be problematic if RonN1,2 and/or RonP1,2 are too small and td is sufficiently large
Interestingly, if Vt1,2 < Vdd/2, the critical state is 2, since in this case RonN << RonP. Conversely, if Vt1,2 >
Vdd/2, the critical state is 4, since now RonP << RonN. Hence, if really needed, we can choose the least
critical “transition” to inject the test pulses, and swap the magnitudes of Vt1 and Vt2 to achieve the
desired test pulse polarity.
Test pulses with varying td and Vt1,2
19
Test pulses are simultaneously applied to 4096 pixels and also the RC model of the lines (Ru = 1.5Ω, Rup = 6Ω, Rs = 1kΩ, Cu = 1.3pF/128) is accounted for the loading of the two test pulse buffers
Slightly differences in the test pulses happen only for sufficiently large td and at the critical (worst) transitions (set by the Vt1,2 magnitudes)
For typical td values (one INV gate delay ~ 200 ps), the switching overlapping is not a problem at all
Vt1,2 < Vdd/2 transition 2 critical Vt1,2 ~ Vdd/2 no critical transition Vt1,2 > Vdd/2 transition 4 critical
Test pulses for varying pixels load
20
Ideally, applying a ΔVt of 80 mV in the test capacitor, Ct = 10 fF, would inject an input charge of 5ke- Increasing the load (i.e. the number of pixels being driven by the buffers) distort the applied test
pulses. Up to ~ 512 pixels, however, the distortion is minimal. For relatively small number of pixels, the input charge injected by the test pulse circuit correlates
very well with an equivalent charge injected by a current pulse
DAC cascoded output
21
Added NMOS/PMOS cascode current mirrors at DAC output to improve the output voltage, Vo, linearity
The cascode voltages, Vcn and Vcp, are provided by same periphery DACs that set the cascode voltages of the on-pixel calibration DACs (devices sized to have approx. the same ID/(W/L))
DAC buffered output linearity
22
The buffered DAC output has a best-fit INL better than 0.5 LSB for a range from approximately 0.26 to 0.80 V, i.e., ~0.54 V
At the lower end the linearity is limited by the buffer, and at the higher end it is limited by the combination of the buffer and the current mirror
Segmented DAC cascoded output
23
For the segmented DAC, cascode current mirrors are added to both the LSB and MSB DACs
The current mirrored by the MSB DAC is 9x larger than the one mirrored by the LSB DAC. The two currents are summed up and generate an output voltage, Vo, across an output resistor.
Segmented DAC buffered output linearity
24
For the segmented DAC, the output linearity of the LSB DAC is of most importance For a set of transfer characteristics of the LSB DAC covering the most linear region
of the MSB DAC, the INL is larger than 0.5 LSB only for some LSB DAC codes. However, the INL may be improved using the middle range of LSB DAC codes where the LSB DAC is more linear.
best fit from 32 to 224 LSB DAC codes
Bandgap
25
Bandgap IP block provided by Stefano Michelis (CERN) Layout area ~400 x 300 µm2
Bandgap voltage Vbg ~300 mV Power dissipation ~60 µW A slightly different bandgap (w/ diodes instead of DTNMOS) is under characterization, and
depending on the results Stefano will provide us that block for integration
Iref generation
26
Rbg implemented with unsalicided N+ poly resistor (TC1 = 150 ppm/°C) Bandgap programmable by 3 bits plus 1 bit for the output multiplexer control Two circuits to generate Iref in case the bandgap does not work as expected
Vbg variation over PVT
27
The worst relative variation of Vbg over a temperature range of -20 to 100 °C is ~1.5% Vbg is almost insensitive to Vdd variations but quite dependent on the process corners
(maximum variation of ~6% over corners)
Vbg variation over R2
28
The programmable value of R2 can be used to adjust the absolute value of Vbg by about ±10% around the nominal value of Vbg = 300 mV
Iref variation over PVT
29
The worst relative variation of Iref over a temperature range of -20 to 100 °C is ~1.5% Iref has a significant variation over process corners (about ±20%) which can be partially compensated by R2. The
variation of Iref over Vdd is negligible. For very low temperatures (< 0°C), “ff” process corner, and Vdd = 1.32V, the Iref generation performance is being
limited by the OTA used to set Vbg across Rbg. However, the chip is unlikely to operate at these low temperatures.
Periphery DACs dynamic ranges
30
Signal DAC output (Iop) M:N / R Resulting range Nominal value DAC code
Vbpcsa 0 – 12.75 µA 3:1 0 – 4.25 µA 1.50 µA 90
Vbpcsaoff 0 – 12.75 µA 300:1 0 – 42.5 nA 15 nA 90
Vcpcsa 0 – 12.75 µA 1:9 / 10 kΩ 0.05 – 1.2 V 601.5 mV 133
Vbpikrum 0 – 12.75 µA 500:1 0 – 25.5 nA 8 nA 80
Vfbk 0 – 12.75 µA 1:9 / 10 kΩ 0.05 – 1.2 V 601.5 mV 133
Vt1 0 – 12.75 µA 1:9 / 10 kΩ 0.05 – 1.2 V 601.5 mV 133
Vbncomp 0 – 12.75 µA 1:1 0 – 12.75 µA 1.50 µA 30
Vbncompoff 0 – 12.75 µA 100:1 0 – 127.5 nA 15 nA 30
Vbpcomp 0 – 12.75 µA 1:1 0 – 12.75 µA 2.50 µA 50
Vbpcompoff 0 – 12.75 µA 100:1 0 – 127.5 nA 25 nA 50
Vth,Vt2 0 – 12.75 µA 1:1 / 1:9 / 10 kΩ 0.05 – 1.2 V 579.0 mV 0 / 138
Vbpcaldac 0 – 12.75 µA 64:1 0 – 200 nA 50 nA 64
Vcpcaldac 0 – 12.75 µA 1:9 / 10 kΩ 0.05 – 1.2 V 601.5 mV 133
Vcncaldac 0 – 12.75 µA 1:9 / 10 kΩ 0.05 – 1.2 V 601.5 mV 133
Vbpbuf1 0.8 – 12.0 µA 1:1 0.8 – 12.0 µA 6.4 µA 136
Vbpbuf2 0.8 – 12.0 µA 1:2 1.6 – 24.0 µA 12.8 µA
To-do list
Finalize the integration the bandgap IP block (waiting Stefano feedback)
Final chip assembly and verification Chip tape-out planned for end Oct./2015
31
Thank you!
Backup Slides
Buffer stability vs CL & Rs at # conn. points
34
Connecting the buffered lines close to the 1st (or end) double column demands slightly less Rs to achieve the same buffer phase margin, since the contribution of Rup adds up saliently
Rs connected at middle column
Rs connected at 1st column