Class-D Garage Band Amplifier

Team: Aaron Danielson, Robert Mann, Randall Newcomb, Andrew RussellSponsor: Nigel Thompson, RT LogicAdvisor: Dr. William Harrison

Overview

• Purpose of the Class-D Garage Band Amplifier• Versus Commercial Products• System Concept• System Block Diagram• Major Tasks• Stretch Goals• Digital Signal Processor• Budget Overview• Project Schedule 2

Purpose

• Class D Amplifier Power Efficiency• Price Point • Customizability• Open Source

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To Compete withCommercial Products

Must Have Should Have Could Have

Sound Quality User Friendly Sound Effects

Power Equalizer

Low Cost

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System Concept

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FPGA Block Diagram

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System Block Diagram - Output

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Major Tasks - FPGA

• Top Level Wrapper - Randy– Contains all the modules for testing that will be

synthesized onto the FPGA.• Digital Signal Processor - Aaron

– Design 4 filters – two each for bass & treble.– Interface with menu HSM to allow user to adjust

settings.• Hardware State Machine - Rob

– Implement a menu to control all the systems (LCD, ADC, DAC, DSP, SIGGEN, USER INPUT)

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Major Tasks – Output Stage

• Amplifier Output Stage - Andrew– Order and solder breakout boards

• Surface mount pin packages (64 pin)• Used for initial testing of components

– Layout custom PCB • 4 layer for power handling capability

– Implement final design and test the output stage

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Stretch Goals

• An all digital amplifier will be implemented– No analog signals between input and speaker out

• Add sound effects to the DSP– Echo– Reverb– Vacuum tube emulation

• Speaker Enclosure– Build the enclosure– Design bandpass filters for the selected speaker

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Digital Signal Processor

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Design Choices forControlling Logic

Factor Weight PicoBlaze ScoreScore

×Weight

MSP430 ScoreScore

×Weight

Verilog ScoreScore

×Weight

Ease of use 35 Asm 3 105 C 5 175 Verilog 2 70

Existing libraries 40 None. 0 0 LCD only. 1 40 Close; in

VHDL. 1 40

Existing code from ADD class

40 None. 0 0 None. 0 0 Lots. 4 160

Total 115 105 215 27012

Design Choices for DSPFactor Weight Xilinx Intellectual

Property (IP) ScoreScore

×Weight

Built-In DSP on TAS5508C Score

Score×

Weight

Speed 30 Extra cycles in state machine 4 120 Internally buffered; does not affect ADC or DAC. 5 150

Quality 40Framework provided by PhD’s at Xilinx; parameterized by me

3 120 Designed by PhD’s at Texas Instruments 5 200

Complexity 25 Xilinx’s CoreGen tools are user friendly 2 50 Requires massive

additions to code base -5 -125

Coupling 50 Decoupled 0 0 Coupled -5 -250

Totals 150 370 20

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Will Design MeetRequirements?

Requirement Solution ≥ ?

An amplifier output will be driven by an FPGA

The Spartan 3E FPGA drives the output.

Yes.

The output stage will be a PWM H-bridge amplifier

TI’s TAS5508C contains a PWM H-bridge amplifier.

Yes.

Output of more than 100W UCC25600EVM-644 power supply delivers 600W.

Yes.

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Printed Circuit Board (PCB)

• 4 Layer PCB• Gives full ground and power planes• Necessary for high power circuits• Qualities/Needs outweigh the cost

50VPower

Signal

Ground

Signal15

12V

PCB Ground

• Analog and Digital GND

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PCB Power

• Split Planes• Half-Bridge Power

(+50V)• Regulators, Other

Circuitry (+12V)

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Noise

• PWM amplifier switching• Analog and Digital ground shorted• Crosstalk• Power Supply• How to deal with it

– Decoupling Capacitors– Maximize distance between traces– Proper component selection

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Budget

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Budget

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Project Schedule

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Conclusion

• Minimal Cost Versus Commercial Products• Design Implementation• Stretch Goals if Time Permits• Budget Situation• Task Scheduling and Project Progress

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APPENDIX

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Menu HSM

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SPI

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DSP

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Signed/Unsigned Issue

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Title

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