Class 03 Semiconductor Processing

8/22/2019 Class 03 Semiconductor Processing

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Class 03: Semiconductor Processing

Topics:

1. Introduction2. Photolithography - Overview I

3. Photolithography - Overview II

4. Photolithography - Printing Techniques

5. Photolithography - Masks and Photoresist

6. Photolithography - Photoresist and Exposure7. Photolithography - Limits of Printing

8. Photolithography - Sources of Light

9. Wafer Growth

10. Doping - Diffusion

11. Doping - Ion Implantation or II

12. Oxidation

13. Deposition

14. Etching


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Class 03: Semiconductor ProcessingPhotolithography - Overview I (Jaeger p.14)

Overall steps in Photo process Impact of Clean Room Rating on Particle Size

Stepper


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Class 03: Semiconductor ProcessingPhotolithography - Overview II (Runyan p.37; Mason)

Transfer desired pattern to an optical maskthat is clear except where a pattern/shape is desired

Cover the entire wafer surface with photoresist (~1m thick)Expose the wafer to light through the optical mask (takes ~ 1-5 seconds exposure)

Use chemical processing to remove PR only where it has been exposed to light

(the pattern is now transferred from the optical mask to the wafer surface)

Subsequent process steps (e.g. oxidation, diffusion, deposition, etching).

These will affect only the areas where there is no PR and be blocked where the PR remains.

After all necessary processing through pattern, remove all PR in chemical process.


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Class 03: Semiconductor ProcessingPhotolithography - Printing Techniques (Jaeger p. 25)

Contact Proximity Projection


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Class 03: Semiconductor ProcessingPhotolithography - Masks and Photoresist (Jaeger p.15)

Proximity printing shown,

but not done today -all projection printing

Cross section of mask shown

in the diagrams to the left

Final on-wafer layer

Positive photoresist


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Class 03: Semiconductor ProcessingPhotolithography - Photoresist and Exposure (Runyan p.174, 178)

What is resist?A resist is a combination of a:

(1) resin that can withstand the etch solution (2) sensitizer that is photosensitive

(3) adhesion promoter to stick the solution to the layer (4) thinner to modify the viscosity

Negative Resist-exposure to light makes resist more difficult to etch

Positive Resist-exposure to light makes resist easier to etch

Acid vs. Base : after exposure to light, positive resist become acidic, development in a base allows for removal of resist

Clearing the Resist : this means the action of developing the resist and washing away the exposed (+ resist) areas

Scumming : this occurs when the resist thickness and/or exposure time along with development does not sufficiently clear the resist


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Contrast-difference in amount of light needed to clear the resist and the amount of light where an image just begins to form

Resolution-minimum size feature that can be formed with the resist

Numerical aperature: NA = n sin f (fundamental to lens)

when image is formed at focal point of lens, then NA = 2 F = 2 (focal length/diameter)

Projection printing resolution: S r = 0.6 l / NA (aka Rayleigh limit)

Depth of focus: The amount of defocusing that can be tolerated across the shot (die)

Depth of focus: d = wavelength / (2NA)2

This means that resolution is obtained at the expense of DOF

As NA increases, smaller feature size (better resolution), but lower DOF

Photolithography - Limits of Printing (Runyan c.5)

Resolution of feature in the X-Y plane vs.

Spacing of features

(near the diffraction limit)

Lower resolution(bigger feature size)

Higher resolution(smaller feature size)

Lower DOF

(tighter across-

wafer variation)

Higher DOF

(looser across-

wafer variation)


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Class 03: Semiconductor ProcessingPhotolithography - Sources of Light (Runyan c.5)

Source Description Wavelength (nm) Feature size(um) Numerical Aperature Depth of Focus (um)

Hg Lamp G-line 436 0.90H-line 405

I-line 365 0.70, 0.50 0.40, 0.48 2.3, 1.6

0.35

Excimers

XeF DUV 351

XeCl DUV 308

KrF DUV 249 0.35, 0.25 0.35 1.0

ArF DUV 193 0.18, 0.15

F2 VDUV 157

Optical and UV Spectrum of

High-Pressure Hg Lamp


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Class 03: Semiconductor ProcessingWafer Growth (Runyan p.23, p.31; Mason)

Methods - (1) Czochralski (CZ) (2) Horizontal Bridgman (3) Float Zone

we will discuss only method #1 as it is the dominant production for Si

Create large ingots of semiconductor material by heating, twisting, and pulling. (~ 1-2 meters long by 100-300mm diameter)

Entire ingot aligned to the same crystal lattice orientation (single-crystal).

Remove all impurities all one element.

Slice ingot into very thin (~400-750m) discs called wafers.

Some wafer are uniformly doped with specific impurities (e.g. Boron for p-type wafer with NA

= 1014 cm-3 )


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Class 03: Semiconductor ProcessingDoping - Diffusion (Mason)

n-type substrate (N )D

n-type substrate (N )D

oxide

oxide

Before Diffusion

After Diffusion

atoms/cm3

atoms/cm3

x,depthintowafer

x

xj

A masking layer (e.g. PR) is used to block the wafer surface except where the dopants are desired.

The wafer is placed in a high-temperature furnace (~1000C) where the atmosphere contains thedesired impurity in gaseous form. Through the process of diffusion, impurity atoms, which are in

high concentration in the atmosphere, will diffuse into the substrate, where they have a low concentration

(initially zero). After some time (~0.5 10 hours) the impurity atoms are uniformly distributed into the

exposed wafer surface at a shallow depth (0.5 - 5m) at a concentration that can be reliably controlled (~10 1 2-101 9 cm-3).


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Implantation is functionally similar to diffusion, but here the atoms are shot into the wafer at high velocity

(across a very strong electric field) and they embed themselves into the wafer surface. A short (~10min.)

annealing step at elevated temperatures (~800C) is used to fit the new atoms into the substrate crystal lattice.Implantation is more uniform across the wafer than diffusion and allows for very precise control of where the

impurities will be. In addition, its peak concentration can be beneath the wafer surface, and it does not required a

long period of time at high temperature (which can be harmful). However, an implanted junction must remain near

the surface of the wafer (~ 0.1 - 2m) and cannot go as deep as a diffused junction. The impurity concentration

profile (concentration vs. depth) is different for diffusion and implantation, however both are well known and predictable.

Doping - Ion Implantation or II (Mason, Martin p.39, Runyan p.486)


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Class 03: Semiconductor ProcessingOxidation (Mason; Runyan c.3)

When a Si wafer is exposed to O2

at high temperatures (~1000C) a native oxide is grown on the surface of the wafer.

Because material (O2) is being added to the wafer, the wafer grows in thickness, and ~ 50% of the oxide grows

beneath the surface and the other half on top of the (original) surface.

Native oxide growth is used in MOS fabrication to grow the field oxide (the region outside of the active region)

and to create the gate oxide layer, the thickness of which can be well controlled

DRY oxidation

WET oxidation


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Class 03: Semiconductor ProcessingDeposition (Mason; Runyan p.124, 133)

CVD-Chemical

Vapor Deposition

Dielectrics:

Offer a variety of dielectric materials including SiO2

and SiN.

Can be deposited on top of all other materials used in semiconductor fabrication.

Can be deposited in thick layers (~1-2 m).

Polysilicon:

Granular Si with similar material properties to single-crystal Si and SiO2.

Native thermal oxide, SiO2 ,

can be grown on top of polysilicon.

Can withstand subsequent high temperature steps (unlike metal)

Can be doped to set resistance (low for interconnects, high for resistors)

Used to form MOS gates, resistors, capacitors, and memory cells.

Metals:

Form low resistance interconnections.

Can not withstand high temperature process steps.

Many metal interconnect layers can be used which are insulated by deposited dielectrics.

Sputter

Deposition


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Class 03: Semiconductor ProcessingEtching (Mason; Runyan p.269, 281)

Chemical Etching:

Selective etching of desired material.

Can be masked by PR or oxide.Isotropic etch will undercut masking layer

Chemical-Mechanical (Reactive Ion Etching):

Mechanical etching process with some chemical selectivity.

Can be masked by PR or oxide.

Anisotropic etch no undercut.

Mechanical (Ion Milling):

No material selectivity, must be blocked by thick mask.Anisotropic etch no undercut.

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Class 03 Semiconductor Processing