Cisco Lan Switch Architectures and Performance

Copyright © 1998, Cisco Systems, Inc. All rights reserved. Printed in USA.Presentation_ID.scr 1

16031041_05F9_c2 © 1999, Cisco Systems, Inc. 1© 1999, Cisco Systems, Inc. 6031041_05F9_c2

2© 1999, Cisco Systems, Inc. 6031041_05F9_c2

LAN Switch ArchitecturesLAN Switch Architecturesand Performanceand Performance

Session 603Session 603


36031041_05F9_c2 © 1999, Cisco Systems, Inc.

Introduction and Definition of TermsIntroduction and Definition of Terms

AgendaAgenda

• Queuing Models• Switching Implementations• Switching Fabrics• Example—Catalyst 4000 Series• Example—Catalyst 8500 Series• Example—Catalyst 6000 Family• Example—Catalyst 5000 Family


ObjectiveObjective

To understand the componentsof multilayer switching

architectures, how the operateand how they are utilized in the

Catalyst switch family



Definition of TermsDefinition of Terms

•• Switching fabricSwitching fabric—refers to the“highway” the data takes to get fromone port to another

•• BackplaneBackplane—a series of electric traceslocated on the “back” of the chassis onwhich data is run; may also include theswitching fabric

•• QueuingQueuing—buffer mechanisms usedto control congestion


Definition of Terms (Cont.)Definition of Terms (Cont.)

•• Local switching decisionLocal switching decision—Implementation in which switchingdecisions are made at the local portor line module

•• Local switchingLocal switching—Packets areswitched on a switching fabric localto the module or line card




•• Oversubscription (blocking)—Oversubscription (blocking)—Condition in which the totalbandwidth of the ports is greater thanthe capacity of the switching fabric

•• Non-blocking—Non-blocking—Condition in whichthe fabric contains more bandwidththan the sum total of all the ports



•• Head-of-line blockingHead-of-line blocking—Wherecongestion on an outbound portlimits throughput to uncongestedports; completely different fromover-subscription



Layer 2 vs. Layer 3 SwitchingLayer 2 vs. Layer 3 Switching

PacketPacketFrameFrame PacketPacket PacketPacket PacketPacketFrameFrameRoutingRouting

TableTable

Layer 3 Switching

Layer 2 Switching


LineLineCardCard

LineLineCardCard

LineLineCardCard

Components of MultilayerComponents of MultilayerSwitch ArchitecturesSwitch Architectures

• CongestionManagement

• SwitchingDecision

• Switching Fabric

LineLineCardCard

LineLineCardCard

LineLineCardCard

LineLineCardCard

LineLineCardCard

LineLineCardCard

Multi-Multi-GigabitGigabitSwitchSwitchFabricFabric

CPULineLineCardCard

SiSi

SiSi

SiSi

SiSi

SiSi

SiSi

SiSi



AgendaAgenda

• Introduction and Definition of Terms•• Queuing ModelsQueuing Models• Switching Implementations• Switching Fabrics• Example—Catalyst 4000 Series• Example—Catalyst 8500 Series• Example—Catalyst 6000 Family• Example—Catalyst 5000 Family


Congestion ManagementCongestion Management

• Required when multiple ports arecontending for the same port

• Important if switch fabric is congested



Dynamic Buffer QueuingDynamic Buffer Queuing

• Each buffer fixed in small increments(for example, 64 bytes each)

• Allows for efficient use of buffers

ThreeThree 64–ByteFrame Uses 192

Bytes of Memory

OneOne 256–ByteFrame Uses 256Bytes of Memory

Unused Memory


Fixed Buffer QueuingFixed Buffer Queuing

• Buffer length fixed in size (often to MTU)

• Less expensive than custom controllers

• Inefficient use of buffers

OneOne 64–ByteFrame Uses OneOne2000–Byte Buffer

OneOne 256–ByteFrame Uses OneOne2000–Byte Buffer

Wasted Memory



Input QueuingInput Queuing

• Packets buffered at the inbound port

• Results in head of line blocking

• Reduces throughput to 60% maximum

Output Port

Buffer

SwitchingSwitchingFabricFabric

Data inData in

Input Port


Head of Line BlockingHead of Line Blocking

OutputPort A

OutputPort B

Congested!Congested!Input

Module


to Bto B to Ato A to Ato A

Data to A and BBuffered at

Inbound Port

Congestion ForcingMass Queuing atInbound Port



Head of Line BlockingHead of Line Blockingwith Input Queuingwith Input Queuing

• Traffic for B cannot enter switching fabricdue to data for “A” being ahead of it

TrafficDestined

for B

TrafficDestined

for A

Data inData in SwitchingSwitchingFabricFabric


Output QueuingOutput Queuing

• Buffers at the output port

• No head of line blocking

• Can overflow buffers at peak bursts

Buffer

Output Port


Input Port

Data inData in



Output Queuing/Shared BufferOutput Queuing/Shared Buffer

• Central pool of buffers shared between all ports

• Maximum throughput with fewest buffers

• No head of line blocking

Data out to Port 1Data out to Port 1




Data inData in


Multiple Queues per PortMultiple Queues per Port

• Can be implemented in either outputqueuing or shared memory models

• Support multiple service levels for QoS

• Scheduling and/or congestion avoidancealgorithm required

Critical Data, High Priority

Non-Critical Data, Low Priority

Data inData in



AgendaAgenda

• Introduction and Definition of Terms• Queuing Models•• Switching ImplementationsSwitching Implementations• Switching Fabrics• Example—Catalyst 4000 Series• Example—Catalyst 8500 Series• Example—Catalyst 6000 Family• Example—Catalyst 5000 Family


Switching ImplementationsSwitching Implementations

• Describe where and how a switchingdecision is made

Where: Locally or centrally

How: Longest match, exact match



Centralized SwitchingCentralized Switching

• Central forwardingtable utilized

• Provides centralizedcontrol for switchingand learning

• Lookup done is ASICsfor fast processing

• Can perform a Layer 2or Layer 3 lookup

Central Switch ASIC

Switching FabricSwitching Fabric

Forwarding orForwarding orRouting TableRouting Table

00-0e1-00-00-00-00 2/3


Distributed SwitchingDistributed Switching

• Switching decisionmade locally byport or module

• L2 and L3 tablesmust besynchronized toaccount for adds,moves or changes

• Not routerson cards


Forwarding orForwarding orRouting TableRouting Table

00-0e1-00-00-00-00 2/3CPU

LookupLookupTableTable





Route CachingRoute Caching(Flow-Based Switching)(Flow-Based Switching)

• Demand-basedswitching

• Entry containingsource, destinationand/or Layer 4information

• Flows areunidirectional

LocalLocalRouteRouteCacheCache

Switching Fabric

Routing TableRouting TableRouteRouteProcessorProcessor

Central RoutingCentral RoutingCacheCache


A3BBC1

Ethernet 1FDDI 2Ethernet 5

••••••


••••••


• First packetprocessedswitched by routeprocessor

• Flow cacheenabled (centrallyand/or locally) LocalLocal

RouteRouteCacheCache




A3BBC1

Ethernet 1Gig E-net 1/0Fast Ethernet 2/0

Switching Fabric



••••••


• Subsequentpackets in thatflow switchedvia route cache

• Flow cachedecision madecentrally and/orlocally

• All packetsswitched at Layer 3




A3BBC1


Switching Fabric


SA DA InterfaceC1 BB FF 2/0


••••••


A3BBC1


Switching Fabric


Cisco Express ForwardingCisco Express Forwarding(FIB-Based Switching)(FIB-Based Switching)

• Topology-basedswitching

• Cache pre-populatedbased on routing table,not traffic

LocalLocalFIBFIB

LocalLocalFIBFIB

OSPF, IGRPEIGRP, RIP, BGP, IS-IS

RoutingProtocols

Inject Routesinto theRouting

Table

ForwardingForwardingInformationInformationBaseBase




LocalLocalFIBFIB

LocalLocalFIBFIB



• FIB calculatedbased on routingtable entries, nottraffic flows

• FIB can be keptcentral ordistributed


Switching Fabric

••••••

A3BBC1




LocalLocalFIBFIB

LocalLocalFIBFIB



• Packet entersrouter

• No processswitchingnecessary

• Decision madelocally or centrallyirregardless ofswitching fabric


A3BBC1


Switching Fabric

••••••



AgendaAgenda

• Introduction and Definition of Terms• Queuing Models• Switching Implementations•• Switching FabricsSwitching Fabrics• Example—Catalyst 4000 Series• Example—Catalyst 8500 Series• Example—Catalyst 6000 Family• Example—Catalyst 5000 Family


Single BusSingle Bus

• One central fabric element• Each port must arbitrate for access• Broadcast and multicast easy• Oversubscription normal

Ethernet SwitchModule

Fast EthernetSwitch Module

FDDI UplinkModule

ATM UplinkModule

ForwardingForwardingTableTableCPU

00-0e1-00-00-00-00 2/3



Unicast Switching overUnicast Switching overA Single BusA Single Bus

• Data enters switched port• Bus arbitration takes place• Lookup in forwarding table performed• Packet sent to destination port

Client A Client B

ForwardingForwardingTableTable

Client A Mod3/Port12

Client B Mod5/Port2…


Multicast/Broadcast overMulticast/Broadcast overA Single BusA Single Bus

• Flooded data decreases end-station performance• Destination must be only those ports who need that traffic• Multicast or VLAN mechanism must limit

traffic to certain ports

MulticastSource

Client A Client B

MulticastMulticastTableTable

Multicast A Mod3/Port12Mod3/Port12

…



Crossbar FabricsCrossbar Fabrics

• Multiple inputbuses allows formeshed fabric

• Typically (but notalways) non-blocking

• Broadcast/multicastcomplex

• More complexforwarding tablelookup CPU

Forwarding TableForwarding Table00-0e1-00-00-00-00 2/3


Unicast Switching overUnicast Switching overCrossbar FabricsCrossbar Fabrics

• Balanced traffic

• Ports/moduleshave access topart of thecrossbar

• Multiple trafficstreamssimultaneouslyin fabric



Multicast over a CrossbarMulticast over a Crossbar

• Weakness ina crossbararchitecture

• Packet replicationmust occur, possibleperformance loss

• Entire fabric must be“quiet” for multicastto occur


Shared Memory ArchitectureShared Memory Architecture

• Buffering internal to the switching fabric

• Switching inputs to memory governed by ASICs

• Uses high-speed memory and switching fabric

Module 1

Module 2

Module 3

Module 4

CPU


Shared MemoryShared MemoryPoolPool

SwitchingSwitchingCoreCore




• Switching core performs lookup, resolvesdestination to pointers in memory, switchesthe packet

Module 1

Module 2

Module 3

Module 4

CPU




High-SpeedHigh-SpeedSwitching ASICSwitching ASIC



• Buffers either fixed or dynamic,less buffers needed if architectureis non-blocking

Module 1

Module 2

Module 3

Module 4

CPU




Large Pool ofLarge Pool ofDynamicallyDynamicallyAssigned BuffersAssigned Buffers



Unicast Switching overUnicast Switching overA Shared Memory FabricA Shared Memory Fabric

• Data entersswitch module

• Switched intomemory

• Switching coreevaluates andresolvesdestination

• Packet switched tooutgoing module

Shared MemoryShared Memory

SwitchingSwitchingCoreCoreModule 1 Module 3



Module 1

Multicast/Broadcast SwitchingMulticast/Broadcast Switchingover a Shared Memory Fabricover a Shared Memory Fabric

• Data enters switchmodule and is switchedinto memory

• MAC address lookupreveals packet to bebroadcast/multicast

• Switching coreidentifiesoutgoing ports

• Packet switched tooutgoing multipleoutgoing ports

Module 2



Module 3

Shared MemoryShared Memory



Local SwitchingLocal Switching

• Local switching fabric keeps local traffic offmain fabric; increases switch bandwidth

• Local architecture can be bus, crossbar orshared memory

Main Fabric Input

Forwarding Table

Local Bus

00-0e1-00-00-00-00 2/3

•••

Packet BufferPacket Buffer


AgendaAgenda

• Introduction and Definition of Terms• Queuing Models• Switching Implementations• Switching Fabrics•• Example—Catalyst 4000 SeriesExample—Catalyst 4000 Series• Example—Catalyst 8500 Series• Example—Catalyst 6000 Family• Example—Catalyst 5000 Family



The Catalyst 4000 SeriesThe Catalyst 4000 Series

• Extension of theCatalyst 5000 Familyfor mid-rangewiring closets

• Flexible modularconfigurations

• Cost-effective,high-performance10/100/1000 Ethernetswitching

• Enterprise softwarefunctionality


Catalyst 4000 Family FeaturesCatalyst 4000 Family Features

• Catalyst family software

• Fast/Gigabit EtherChannel

• IEEE 802.1Q support

• Per-VLAN spanning tree

• UplinkFast

• Protocol filtering



Catalyst 4912 and 2948GCatalyst 4912 and 2948G

• Same architecture as theCatalyst 4000

• All ports access 24 gbps ofshared memory

• Catalyst 2948G—48 10/100 portswith two Gigabit Ethernet ports

• Catalyst 4912—12 1000BaseX ports


Catalyst 4000 ArchitectureCatalyst 4000 Architecture

24 Gbps Shared Memory24 Gbps Shared MemoryFabricFabric

SwitchSwitchControllerController

Line CardLine Card Line CardLine CardSwitching ASICSwitching ASIC

00-0e1-00-00-00-00 2/3Forwarding TableForwarding Table




Non-BlockingSwitchingFabric










12 Gbps perLine Card




Catalyst 4000 Port Interface—Catalyst 4000 Port Interface—Gigabit EthernetGigabit Ethernet

• 12 Gbps perline card

• No buffering orswitching online cards

• All intelligence inswitchingcore ASIC

Shared MemoryShared MemoryFabricFabric

Switching ASICSwitching ASIC

GBICGBIC GBICGBIC GBICGBIC GBICGBIC GBICGBIC GBICGBIC

Non-BlockingAccess into

Fabric


Catalyst 4000 Port Interface—Catalyst 4000 Port Interface—Fast EthernetFast Ethernet

• Breakout ASICconnects 8 10/100ports to single1 Gbps fabric port

• Non-blocking10/100

• All switching onsupervisor engine

BreakoutASIC

Shared MemoryShared MemoryFabricFabric

Switching ASICSwitching ASIC






00-0e1-00-00-00-00 2/3

Switch ControllerSwitch ControllerForwarding TableForwarding Table

Catalyst 4000 Shared MemoryCatalyst 4000 Shared Memory

8 MBSharedMemory



CentralizedForwardingEngine




00-0e1-00-00-00-00 2/3







00-0e1-00-00-00-00 2/3


Frame Switching in the Catalyst 4000Frame Switching in the Catalyst 4000

Packet EntersPacket EntersSwitch, StoredSwitch, Stored

in Memoryin Memory



Switching EngineSwitching EngineConsulted WhileConsulted While

Frame Is inFrame Is inMemoryMemory




00-0e1-00-00-00-00 2/3







00-0e1-00-00-00-00 2/3



Destination Found,Packet Sent to

Output Port


Catalyst 4003/4912 PerformanceCatalyst 4003/4912 Performance

• 10/100 for 96 ports14,285,760 packets per second (64 bytes)

• 1000BaseX for 12 ports17,857,200 packets per second (64 bytes)



Catalyst 2948G PerformanceCatalyst 2948G Performance

• 10/100 for 48 ports7,142,880 packets per second (64 bytes)

• 1000BaseX for 2 ports2,961,319 packets per second (64 bytes)


AgendaAgenda

• Introduction and Definition of Terms• Queuing Models• Switching Implementations• Switching Fabrics• Example—Catalyst 4000 Series•• Example—Catalyst 8500 SeriesExample—Catalyst 8500 Series• Example—Catalyst 6000 Family• Example—Catalyst 5000 Family



Catalyst 8500 SeriesCatalyst 8500 Series

Cisco IOSCisco IOS®®

Catalyst 8540Catalyst 854013 Slot13 Slot

Catalyst 8510Catalyst 85105 Slot5 Slot

Cisco Express ForwardingCisco Express Forwarding™™

Cisco IOS Routing ProtocolsCisco IOS Routing Protocols

Wire-Speed IP, IPX SwitchingWire-Speed IP, IPX Switching

Extensive QoS CapabilitiesExtensive QoS Capabilities Multiservice IntegrationMultiservice Integration

Wire-Speed IP MulticastWire-Speed IP Multicast




RouteRouteProcessorProcessor

LineLineCardCard SiSi


LineLineCardCardSiSi


00-0e1-00-00-00-00 2/3

Routing Table/Routing Table/FIB TableFIB Table















00-0e1-00-00-00-00 2/3



Catalyst 8500 SeriesCatalyst 8500 SeriesSwitch FabricSwitch Fabric

Non-Blocking,Fabric

10/40 Gbps Shared Memory10/40 Gbps Shared MemoryFabricFabric






00-0e1-00-00-00-00 2/3



Dynamic Buffering ArchitectureDynamic Buffering Architecture



Shared Memory FabricShared Memory Fabric

Dynamically AllocatedBuffers in Fabric


Multiple Queues per PortMultiple Queues per Port

• Traffic in queue 1 destined for A will beserviced more often than queue 4 for B

• User A will see less latency


Output QueuesServiced

According toPriority Queue 0–6,7

Queue 1–4,5

Queue 2–2,3

Queue 3–0,1SiSi SiSi

INTINTG1/0/0G1/0/0



Weighted Round Robin in theWeighted Round Robin in theCatalyst 8500 CSRCatalyst 8500 CSR

• Outbound schedulingalgorithm

• Service assignedvia user-defined weightson outbound port

• Scheduler enforcesbandwidth requirementsper queue

Queue 0Weight = w

Queue 1Weight = x

Queue 2Weight = y

Queue 3Weight = z

ToS = 6,7ToS = 6,7

ToS = 4,5ToS = 4,5

ToS = 2,3ToS = 2,3

ToS = 0,1ToS = 0,1



Catalyst 8500 ForwardingCatalyst 8500 Forwarding

• Cisco IOS processor maintains routing table

• Computes forwarding information base

FIB ComputedCentrally via

RoutingProtocols





00-0e1-00-00-00-00 2/3



Catalyst 8500 Distributed FIBCatalyst 8500 Distributed FIB

• FIB performs longest match networkaddress lookup in hardware

DistributedDistributedFIBFIB

DistributedDistributedFIBFIB





FIB Downloadedto Line Cards


00-0e1-00-00-00-00 2/3





FIB Computed andFIB Computed andDownloaded to PortsDownloaded to Ports

FIB TableFIB TableA3BBC1

Fast E-net 0/1Fast E-net 3/6Fast E-net 5/8

A3BB

C1

Fast E-net 0/1Fast E-net 3/6

Fast E-net 5/8•••

A3BB

C1



…

Packet Switching in thePacket Switching in theCatalyst 8500Catalyst 8500






FIB TableFIB TableFast E-net 0/1Fast E-net 3/6Fast E-net 5/8

A3BB

C1



A3BB

C1



Packet Enters Switch,Packet Enters Switch,Switching DecisionSwitching Decision

Made at Ingress PortMade at Ingress Port

…

A3BBC1



Packet SwitchedPacket Switchedinto Memory;into Memory;Pointer Set toPointer Set to

OutgoingOutgoingInterfaceInterface





A3BB

C1



A3BB

C1



…

A3BBC1




Frame RewrittenFrame Rewrittenon Egress Porton Egress Port





A3BB

C1



A3BB

C1



…

A3BBC1



Catalyst 8500 Series PerformanceCatalyst 8500 Series Performance

• Fast Ethernet forwarding rateCatalyst 8510—4.76 million pps

Catalyst 8540—19 million pps

• Gigabit Ethernet forwarding rateCatalyst 8510—5.77 million pps

Catalyst 8540—23 million pps



AgendaAgenda

• Introduction and Definition of Terms• Queuing Models• Switching Implementations• Switching Fabrics• Example—Catalyst 4000 Series• Example—Catalyst 8500 Series•• Example—Catalyst 6000 FamilyExample—Catalyst 6000 Family• Example—Catalyst 5000 Family


The Catalyst 6000 FamilyThe Catalyst 6000 Family

• Gigabit multilayerswitching from CiscoSystems:

• Key features include:Wire-speed multilayerswitching scalable to256 GbpsScalable IP and IPX routingperformance to 150million ppsMultiprotocol Cisco IOSrouting support forAppleTalk, DECnet, VINESQoS and voice support



Media Module Options

Catalyst 6000 Line ModulesCatalyst 6000 Line Modules

• 8-Port Gigabit Ethernet(GBIC support)

• 16-Port Gigabit Ethernet

• 48-Port 10/100 RJ-45 and Telco

• 24-Port 100BaseFX (MT-RJconnector)

• 24-Port 10BaseFL (future)

• ATM OC-12 (future)Single port, MM or SM

Traffic shaping

Congestion control mechanisms

AAL5 support for ABR, VBR,and UBR


Catalyst 6000 FamilyCatalyst 6000 Family

• Port densities384 10/100 ports

192 100BaseFX ports

130 1000BaseX ports

192 10BaseFLports (future)



Catalyst 6000 Series ArchitectureCatalyst 6000 Series Architecture

Gigabit EthernetGigabit EthernetModuleModule

Control BusResults Bus

Port 1–4Port 1–4

10/100 Ethernet10/100 EthernetModuleModule


64 KB64 KB Buffer Buffer


32 Gbps Switching Fabric32 Gbps Switching Fabric

Network Mgmt.Network Mgmt. NMP/MCP NMP/MCP

EARLEARLSwitchingSwitchingSystemSystem

Fabric Fabric ArbitrationArbitration

SupervisorEngine

Multilayer Multilayer Forwarding TableForwarding Table

FeatureFeatureCardCardSlotSlot

PINNACLEPINNACLEASICASIC CPUCPU

Layer 3 SwitchingLayer 3 SwitchingEngineEngine

Layer 3 Layer 3 ForwardingForwarding

TableTable

Multilayer Switching ModuleMultilayer Switching Module

COILCOILASICASIC

PINNACLEPINNACLEASICASIC














SupervisorEngine


COILCOILASICASIC





MultilayerMultilayerSwitchSwitchFeatureFeature

CardCard

Layer 3 Integrated intoEARL Switching System











COILCOILASICASIC


Traces for Future Crossbar FabricTraces for Future Crossbar Fabric







SupervisorEngine


MultilayerMultilayerSwitch Switch FeatureFeature

CardCard










COILCOILASICASIC





Centralized Switching Fabric




SupervisorEngine



CardCard











COILCOILASICASIC








SupervisorEngine



CardCard

ControlSignals










COILCOILASICASIC








SupervisorEngine



CardCard

Fabric Arbitration











COILCOILASICASIC








SupervisorEngine



CardCard

Per-PortBuffering

and ASICs



Port ASIC Built-in FeaturesPort ASIC Built-in Features

• InterSwitch Link (ISL) and 802.1Q

• In-line rewrite capability for Layer 3and QoS reclassification

• Fast and Gigabit EtherChannel

• Four groups of RMON per port

• Two queues per port

• Four drop thresholds per port



PINNACLE Controls DMA Access into Per-PortMemory and Performs Arbitration Requests

Catalyst 6000 Port ASICs—Catalyst 6000 Port ASICs—Gigabit EthernetGigabit Ethernet

Gigabit Ethernet ModuleGigabit Ethernet Module

Port 1–4Port 1–4 Port 5–8Port 5–8



per Portper Port




per Portper Port


Catalyst 6000 Port ASICs—Catalyst 6000 Port ASICs—10/100 and 100BaseFX10/100 and 100BaseFX

Fast Ethernet ModuleFast Ethernet Module

BreakoutASICs:1 Gbps

to 1210/100Ports


COILCOILASICASIC

Buffering per10/100 Port

COILCOILASICASIC

COILCOILASICASIC

COILCOILASICASIC



Dual Queues and BufferDual Queues and BufferAllocation—Gigabit EthernetAllocation—Gigabit Ethernet

Port 3/8Port 3/8Port 3/8

Switching Fabric

Single Input Queue(Store and Forward

Check andArbitration Request)

Dual OutputQueues

(Configurable)PINNACLEPINNACLE

ASICASIC

RXRX64 KB64 KB

TX(high) 256 KBTX(high) 256 KB

TX(low) 192 KBTX(low) 192 KB


Dual Queues and BufferDual Queues and BufferAllocation—Fast EthernetAllocation—Fast Ethernet

Port 4/48Port 4/48Port 4/48

Sharedbetween12 10/100

PortsRX RX

64 KB64 KB

TXhigh 256 KBTXhigh 256 KB

TXlow 192 KBTXlow 192 KB

TXhigh 32 KBTXhigh 32 KB

TXlow 24 KBTXlow 24 KB

RX RX 8 KB8 KB

Switching Bus

Dedicated per Port


COILCOILASICASIC



WeightedRound Robin

Used ToSchedulebetweenQueues

WeightedRandom Early

Discard(WRED) Usedwithin Queue

for CongestionAvoidance

PINNACLEPINNACLE

QoS Mechanisms in Catalyst 6000QoS Mechanisms in Catalyst 6000


HighPriority Queue

256 Kb

LowPriority Queue

192 Kb

PINNACLEPINNACLEWRR Queue SchedulerWRR Queue Scheduler


Catalyst 6000 Switching SystemCatalyst 6000 Switching System

Results Bus

EARL SwitchingSystem

Multilayer SwitchFeature Card (Route

Processor)

Multilayer SwitchMultilayer SwitchFeature Card (RouteFeature Card (Route

Processor)Processor)

Layer 2Forwarding

Engine

Layer 2Layer 2ForwardingForwarding

EngineEngine

Layer 2Forwarding

Table


TableTable

Layer 3Forwarding

Engine


EngineEngine

Layer 3Route Cache

(Forwarding Table)

Layer 3Layer 3Route CacheRoute Cache

(Forwarding Table)(Forwarding Table)

Access ListEngine

Access ListAccess ListEngineEngine

AccessList

Table

AccessAccessListList

TableTable

Route Processor(Control Plane)




Catalyst 6000 Switching SystemCatalyst 6000 Switching System

EARL SwitchingSystem

Multilayer SwitchFeature Card (Route

Processor)

Multilayer SwitchMultilayer SwitchFeature Card (RouteFeature Card (Route

Processor)Processor)

Layer 2Forwarding

Engine


EngineEngine

Layer 2Forwarding

Table


TableTable

Layer 3Forwarding

Engine


EngineEngine

Layer 3Route Cache

(Forwarding Table)

Layer 3Layer 3Route CacheRoute Cache

(Forwarding Table)(Forwarding Table)

Access ListEngine

Access ListAccess ListEngineEngine

AccessList

Table

AccessAccessListList

TableTable

Route Processor(Control Plane)

Lookup andForwarding ASICs

Results Bus



MACMACAddressAddress

Page 1Page 1Page 0Page 0

Page 2Page 2Page 3Page 3

ColorColor IndexIndex ControlControl

EARL Hashing AlgorithmEARL Hashing Algorithm

• Four pages ofmemory

• Hashing algorithm

• 128,000 maximumentries

• Contains L2/L3/L4information













SupervisorEngine



CardCard

COILCOILASICASIC




All Ports in theAll Ports in theCatalyst 6000Catalyst 6000

Ingress PortIngress PortArbitrates,Arbitrates,

Places Frame onPlaces Frame onFabric with SEQFabric with SEQ

3232 Gbps Gbps Switching Fabric Switching Fabric

Frame Switching in theFrame Switching in theCatalyst 6000Catalyst 6000










COILCOILASICASIC








SupervisorEngine



CardCard



EARL MakesEARL MakesSwitching,Switching,

ClassificationClassificationDecisionDecision












SupervisorEngine



CardCard

COILCOILASICASIC





DestinationDestinationReceivesReceivesPacket,Packet,Rewrites ifRewrites ifNeededNeeded





Catalyst 6000 PerformanceCatalyst 6000 Performance

• Forwarding rate: 100 and 1000 MbpsLayer 2: 15 million packets per second

Layer 3 (MSM): 5.2 million packets persecond

Layer 3 (MSFC): 15 million packets persecond



AgendaAgenda

• Introduction and Definition of Terms• Queuing Models• Switching Implementations• Switching Fabrics• Example—Catalyst 4000 Series• Example—Catalyst 8500 Series• Example—Catalyst 6000 Family•• Example—Catalyst 5000 FamilyExample—Catalyst 5000 Family


The Catalyst 5000 FamilyThe Catalyst 5000 Family

• Powerful switchingsolutions:

Multilayer,multiprotocolswitchingComplete Cisco IOSnetwork servicessupportIntegration ofgigabit/ATM/Layer 3on a common platformHigh-density LANaggregation




Port 25Port 25Port 8Port 8



EthernetEthernetModuleModule

Single BusSwitching Fabric

LCPLCP

3.6 Gbps Switching Fabric3.6 Gbps Switching Fabric


NetFlowNetFlowFeatureFeature

CardCard

RMONRMONStatisticsStatistics

SupervisorEngine III

Layer 2 TableLayer 2 TableLayer 3 Route CacheLayer 3 Route Cache

Bus ArbiterBus Arbiter

SAINTSAINTASICASIC

SAINTSAINTASICASIC

SAGE ASICSAGE ASIC LCPLCP

BufferBuffer BIGABIGAASICASIC

BufferBufferBIGABIGAASICASIC

Route ProcessorRoute Processor

SAGE ASICSAGE ASIC







Central Bus Arbiter




CardCard





SAINTSAINTASICASIC

SAINTSAINTASICASIC





SAGE ASICSAGE ASIC

LCPLCP








Per-Port ASICsand Buffering




CardCard





SAINTSAINTASICASIC

SAINTSAINTASICASIC





SAGE ASICSAGE ASIC

LCPLCP


Catalyst 5500 Port InterfaceCatalyst 5500 Port Interface

Switching Fabric

Results Bus

CPUInterface

CPUCPUInterfaceInterface

DMAEngineDMADMA

EngineEngine

10/100MAC

10/10010/100MACMAC

PacketBufferPacketPacketBufferBuffer

Transmit224 Kb

TransmitTransmit224 Kb224 Kb

Receive32 Kb

ReceiveReceive32 Kb32 Kb

RewriteEngineRewriteRewriteEngineEngine

Saint ASIC

Physical Layer Interface








LCPLCP

CentralSwitching andClassificationEngine




CardCard





SAINTSAINTASICASIC

SAINTSAINTASICASIC





SAGE ASICSAGE ASIC


Components of Catalyst 5500Components of Catalyst 5500Multilayer Switching (MLS)Multilayer Switching (MLS)

CiscoCisco7500 Series7500 Series7200 Series7200 Series4000 Series4000 Series

36003600

ororRSM

MLS-RP—MLS-RP—Route ProcessorRoute Processor

MLSP—Multilayer Switching ProtocolMLSP—Multilayer Switching Protocol for Router Registration with MLS-SE for Router Registration with MLS-SE

NFFCMLS-SE—Switch EngineMLS-SE—Switch Engine



Multilayer SwitchingMultilayer SwitchingProtocol (MLSP)Protocol (MLSP)

• Allows RSM, Cisco 7500, Cisco 4000,Cisco 3600 and Cisco 7200 seriesrouters to provide route processingfunctionality

• Used for router registration andservices (i.e., access list) updatesfor NFFC

• Not used in Layer 3 switching itself








CardCard





SAINTSAINTASICASIC

SAINTSAINTASICASIC







SAGE ASICSAGE ASIC

LCPLCP

Data Enters Port andData Enters Port andIs Sent to All PortsIs Sent to All Portsin the Switchin the Switch









CardCard





SAINTSAINTASICASIC

SAINTSAINTASICASIC







SAGE ASICSAGE ASIC

LCPLCP

NFFC IdentifiesNFFC IdentifiesPort-of-Exit andPort-of-Exit andPolicyPolicy







CardCard





SAINTSAINTASICASIC

SAINTSAINTASICASIC







SAGE ASICSAGE ASIC

LCPLCP


If L3 DecisionIf L3 Decisionand No NFFCand No NFFCEntry Exists,Entry Exists,PacketPacketGoes to RSMGoes to RSM









CardCard





SAINTSAINTASICASIC

SAINTSAINTASICASIC







SAGE ASICSAGE ASIC

LCPLCP

If NFFC Has Entry atIf NFFC Has Entry atL2 or L3, OutboundL2 or L3, OutboundPort Keeps Frame;Port Keeps Frame;All Others DiscardAll Others Discard








CardCard





SAINTSAINTASICASIC

SAINTSAINTASICASIC







SAGE ASICSAGE ASIC

LCPLCP

Outbound PortOutbound PortRewrites IP TOSRewrites IP TOSand/or and/or DestDest..MAC AddressMAC Address



Catalyst 5000 FamilyCatalyst 5000 FamilyLayer 2 PerformanceLayer 2 Performance

• Forwarding rate: 10 Mbps2,200,000 pps aggregate

• Forwarding rate: 100 Mbps2,200,000 pps aggregate

• Forwarding rate: 1000 Mbps35.7 million pps (with local switching)

• Multicast forwarding rate: 100 Mbps39.2 million pps


Catalyst 5000 Series Layer 3Catalyst 5000 Series Layer 3Forwarding RatesForwarding Rates

• Route Switch Module (RSM)—175,000 pps

• NetFlow Feature Card (NFFC-II)—2.0 million pps

• Total system throughput (includingCatalyst 8510 SRP and line cards inthe Catalyst 5500)—8 million pps



Additional TalksAdditional Talks

• Router Architecture and Performance

• Deploying Campus-Based Protocols

• Deploying High-Availability Networks

• Introduction to Campus QoS

• Deploying IP Switching Protocols

• Catalyst Product Updates


ConclusionConclusion

A switch’s performance,scalability and features rely on

critical elements within thearchitecture


117© 1999, Cisco Systems, Inc. 6031041_05F9_c2 1176031041_05F9_c2 © 1999, Cisco Systems, Inc.

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Documents

Cisco Lan Switch Architectures and Performance