Page -1

6.002 Circuits and Systems

Final Review

Jason Kim

CIRCUITS AND SYSTEMS

FINAL REVOLUTIONS

Page 0

6.002 Circuits and Systems: Outline of Topics

• Resistor Networksconcepts: Node Method, KCL, KVL, Superposition, Thevenin and Norton equivalent circuit

models, Power.

• 1st Order Circuitsconcepts: Consituitive Laws, RC netwroks, RL networks, Homogenous and Particular solution,

Time constant , response to an impulse, power, Low/High/Band/Notch pass filters, sinusodial steady-state, transients, Impedance Model, Bode Plots(Magnitude and Phase).

• 2nd Order Circuitsconcepts: LC networks, LRC networks, damping coefficient , natural frequency ,

Underdamped/Critical/Overdamped Systems, Resonance, Q factor, Half-power point, Sinusodial steady-state, transients, Power(real/reactive), Impedance Model, ELI ICE, Bode Plots(Magnitude and Phase).

• Digital Abstractionconcepts: Boolean Logic(truth table, formula, gates, and transistor level), primitive laws,

DeMorgan’s Law(formula and gate equivalent), MSP(minumum sum of products), MPS(minimum product of sums).

• MOSFET Transistorsconcepts: Large Signal Model(S, SR, SCS, SVR), Small Signal Model, Saturation/Linear Region,

Ron, Loadline, Operating Point, Input/Output Resistence, Current Gain, Power Gain, Noise Margin.

• Op-Amp Circuitsconcepts: Single/Multiple input op-amp circuits, differentiator, integrator, adder, subtractor, op-

amp with R,L,C, negative feedback, positive feedback, Bode Plots(Magnitude and Phase), Input/Output resistence, Schmitt Trigger, Hysteresis, Cascaded stages.

• Diodesconcepts: i-v characteristics, model, diode w/ R, L, C, and op-amp, Peak detection, Clipper circuits,

Incremental Analysis.

• Energy and Powerconcepts: Energy and Power relationships, nMOS and CMOS logic inverter power dissipation,

static and dynamic power, power reduction techiniques.

τ

α ωo

Page 1

Resistor: time domain: freq. domain:

Series: Parallel:

• Resistor NetworkN-unknowns & N-equations (most primitive approach)Node Analysis (KCL, KVL)

*KCL: Sum of all currents entering and leaving a node is zero.*KVL: Sum of all voltages around a closed loop path is zero. (be careful with polarities)1) LABEL all current directions and voltage polarities. (Remember, currents flow from + to -)2) write KCL & KVL Equation.3) substitute and solve.

Simplification (by inspection)

• Thevenin Equivalent Circuit Model Norton Equivalent Circuit Model

* Three variables: Vth=Voc, Rth=RN, and IN=Isc . They are related by Voc=Isc*Rth .* Vth=Voc: Leave the port open(thus no current flow at the port) and solve for Voc.

For a resistive network, this gives you a point on the V-axis of the i-v plot.* IN=Isc: Short the port(thus no voltage across the port) and solve for Isc flowing out of + and

into -. For a resistive network, this gives you a point on the I-axis of the i-v plot.* Rth: Set all sources to zero, except dependent sources. Solve the resistive network.

When setting sources to zero, V source becomes short and I source becomes open. Rth may also be found by attaching Itest and Vtest and setting Rth = (Vtest)/(Itest). If dependent sources are present, set only the independent sources to zero and attach Itest

and Vtest. Use KCL and KVL to find the expression (Vtest)/(Itest)=Rth.

* For both Thevenin & Norton E.C.M.’s, they have the same power consumption at the port as the original circuit, but not for its individual components. Power dissipated at Rth does not equal power dissipated at the resistors of the original circuit. Same holds for the power delivered by the sources in the Thevenin model and the original circuit. Thevenin and Norton E.C.M.’s are for terminal i-v characteristics only.

• Power = Real Power = IV = I2R = V2/R (energy dissipated as heat)

•

V IR= Z R=

R1 R2+ R1 R2||R1R2

R1 R2+------------------=

+-

R1

R2 VoVi +- R2

I2

ViR1

Ii

VoR2

R1 R2+--------------------Vi= I2

R1R1 R2+--------------------Ii=

Voltage Divider Current Divider

+-

Rth

Vth Voc=Vth

RNIN Isc=INsame i-v characteristics at the ports+

-

+

-

N

Itest

+- Vtest

Original Circuit

note the direction of Itestand polarity of Vtest.

RthVtestItest-----------=

Power⟨ ⟩ 1T--- I t( )V t( ) td

0

T

∫=

1. Primitive Elements

Page 2

• Superposition"In a linear network with a number of independent sources, the response can be found by summing the response to each independent sources acting alone, with all other independent sources set to zero."

1) Leave one source on and turn off all other sources.(Voltage source "off" = short & Current source "off" = open)

2) Find the effect from the "on" source.3) Repeat for each sources.4) Sum the effect from each sources to obtain the total effect.

For cases where a linear dependent source is present along with multiple independent sources, DO NOT turn off the dependent source. Leave the dependent source on and carry it in your expressions. Tackle the dependent source term last by solving linear equations. Remember that the variable which the dependent source is depended on is affected by the individual independent sources that you are turning on and off.

Capacitor: time domain: freq. domain:

High Frequency = Short & Low Frequency = Open

Series: Parallel:

Vc(0-)=Vc(0+) except when the input source is an impulse.Vc(t) is continuous while Ic(t) may be discontinuous.

"I C E" : Current(I) LEADS Voltage(EMF) by 90o (mnemonic: ELI ICE)Energy Conservation: .

Energy Stored: . (no energy dissipation)

Note: Two identical capacitors, C1 and C2, in series may act like an open circuit after a long time where the total voltage across the capacitors are split between the two cap’s. For this case, Vc does not discharge to zero but VC1=VC2.

Inductor: time domain: freq. domain:

High Frequency = Open & Low Frequency = Short

Series: Parallel:

IL(0-)=IL(0+) except when the input source is an impulse.IL(t) is continuous while VL(t) may be discontinuous.

Linear Networkwith n sources R

+

_VR

VR VR1 V2 n∼ 0=VR2 V1 V, 3 n∼ 0=

… VRn V1 n 1–∼ 0=+ +=

I C tddV= Z 1

Cs------ 1jwC----------= =

C1C2C1 C2+------------------- C1 C2+

I td∫ Q CV= =

E 12---CV2=

V L tddI= Z Ls jwL= =

L1 L2+L1L2

L1 L2+------------------

VR when only V1 is on.

C1 C2

R

+

_VC2

+

_VC1

VC1(0-) = VC2(0-)

1. Primitive Elements

Page 3

"E L I" : Voltage(EMF) LEADS Current(I) by 90o (mnemonic: ELI ICE)Energy Conservation: .

Energy Stored: . (no energy dissipation)

Note: Two identical inductors, L1 and L2, in parallel may act like a short circuit after a long time and have current flow through this loop indefinitely. For this case, iL is not zero but iL1=-iL2.

LC:Series@ = Short & Parallel@ = Open

Energy transfers between inductors and capacitors sinusodially (180o out of phase).Also, Vc peaks when IL=0 and IL peaks when Vc=0.

V td∫ λ LI= =

E 12---LI2=

ωo ωo

L1 L2i1 i2 R

iL1(0-) = iL2(0-)

1. Primitive Elements

Page 4

First Order RC & RL Circuits

RC Network RL Network

KVL: KVL:

KCL: KCL:

Differential Eq: Differential Eq:

Time Constant: Time Constant:

*one time constant charges/discharges 63% of the maximum value. Small time constant shows the effect of the exponential curve sooner, while big time constant shows a linear line for a long time before the exponential effect becomes visible.

Homogeneous:

Particular: Step Input

Total:

* Notice the Duality between vc & iL and ic & vL.

+-

R

Vi Vc

+

_C RIi VL

+

_L

iL

Vc(0+)=0 IL(0+)=0

iC

Vi IcR Vc+= Vi IcR Vc+=

Ic Ctd

dVc= Ic Ctd

dVc=

tddVc Vc

RC--------+ViRC--------= td

diL iL

LR--- ---------+

Ii

LR--- ---------=

τ RC= τ LR---=

τ

Aest

t tt t

Vi

VC

VLiC

iL

ViR_ IiR

-Vi -Ii

t tt t

Vi IiRVC

VLiC

iLViR_ Vi

R_

t tt t

Vi

VC VLiC

iLViR_ Vi

R_IiR

2. First Order Circuits

Page 5

Approach to First Order Circuits

1) Set up differential equations, using KCL and KVL. Use the constitutive laws for C and L.

2) Find Homogeneous solution by setting input to zero and substituting Vh=Aest as a solution.

3) Find Particular solution. Remember the output follows the form of the input. ;

4) Combine Homogeneous and Particular solutions, and use initial conditions to find missing variables. (Be careful when input is an impulse!)

at t=0+.

at t=0+, Vo=0 and t= , Vo=Vi.

*After a long time, transients(homogeneous solution) die away, leaving only the particular solution. Thus, the output may look different from the input in the beginning but slowly catches up to follow the input.

Impulse as Input

ex. RC circuit: and and .

➔ ➔

➔

tddVc Vc

RC--------+

ViRC--------=

Asest 1RC--------Aest+ 0= s∴ 1

RC--------–=

Vp Vi= t 0>

Vo Vh Vp+ Aet–

RC--------Vi+= =

Vo A Vi+ 0= = A∴ Vi–=

Vo Vi 1 et–

RC--------–

= ∞

Vi Qδt= Vo 0minus( ) 0= tddVo Vo

RC--------+ViRC--------=

Vod 1RC--------Vo td+ Q

RC--------δt td= Vod

0minus

0plus

∫1

RC-------- Vo td

0minus

0plus

∫+ QRC-------- δt td

0minus

0plus

∫= Vo 0plus( ) Vo 0minus( )– QRC--------=

Vo 0plus( ) 0– QRC--------= Vo∴ 0plus( ) Q

RC--------=

2. First Order Circuits

Page 6

Second Order LRC Circuits

#1 Diff. Eq.:

Time Constant:

#2 Diff. Eq.:

Time Constant:

#3 Diff. Eq.:

Time Constant:

Rii Vc=Vo

+

-CLiL

t2

2

∂

∂ Vo 1RC--------

t∂∂Vo Vo

LC-------+ + 1

C----

t∂∂ii=

Voii

------ jωLRjω( )2LCR jωL R+ +

---------------------------------------------------= τ 1LC

-----------=

H jω( ) H jω( )∠

w

"Band Pass Filter" +90o

-90o

w

+1 -1wL

1 wC

R

ωo1LC

------------= ωo1LC

------------=

+- RVi Vc=Vo

+

-C

L

iL

t2

2

∂

∂ Vo 1RC-------- t∂

∂Vo VoLC-------+ +

ViLC-------=

VoVi------ R

jω( )2LRC jωL R++---------------------------------------------------= τ 1

LC-----------=

H jω( ) H jω( )∠

w

"Low Pass Filter"

0o

-180o

w

-2

ωo1LC

------------= ωo1LC

------------=

+-

R

Vi Vc=Vo

+

-C

L

iL

t2

2

∂

∂ iL RL--- t∂∂iL iL

LC-------+ + 1L--- td

dVi=

iLVi----- jωC

jω( )2LC jωRC 1++---------------------------------------------------= τ 1

LC-----------=

3. Second Order Circuits

Page 7

• "peakiness" & Half-Power Point =

Hence, Half-power Point.

Characteristic Equation (Homogeneous Solution)

Obtain a characteristic equation by setting input to zero and replacing with s to get into the form:

where is the "resonant" or "natural" frequency and is the damping coefficient.solving s with quadratic formula,

; is the damped natural frequency

1) "Overdamped" are real

2) "Critically Damped" are real

3) "Underdamped" are complex

Approach to Second Order Circuits (Transients)

1) Set up 2nd order differential equations.

(ex. circuit #3)

2) Obtain characteristic equation and identify and .

; and

H jω( ) H jω( )∠

w

"Band Pass Filter"

+1 -1wC

1 wL

1 +90o

-90o

w

R

ωo1LC

------------= ωo1LC

------------=

Qωo2α-------= ωo α±

α α

w

Vpeak

Vpeak

2

ωo

PowerVpeak

2-------------

2 1R---

Vpeak2

2R-------------Powerpeak

2---------------------------= = =

ωo α– ωo α+

tdd

s2 2αs ωo2+ + 0=

ωo α

s1 2, α– α2 ωo2–± α– j ωo

2 α2–± α– jωd±= = = ωd

α ωo> s1 s2≠ s1 2,

α ωo= s1 s2= s1 2,

α ωo< s1 s2≠ s1 2,

t2

2

∂

∂ iL RL---

t∂∂iL iL

LC-------+ + 1

L---

tddVi=

ωo α

s2 2 R2L------ s 1

LC----------- 2

+ + 0= ωo∴ 1LC

-----------= α∴ R2L------=

3. Second Order Circuits

Page 8

3) Find Homogeneous solution.(for the appropriate system type)

Overdamped:

Critically Damped:

Underdamped:

4) Find Particular solution. Remember the output follows the form of the input. (usually a step)

5) Combine Homogeneous and Particular solutions, and use initial conditions( ) to find missing variables. (Be careful when input is an impulse!)

Thus, &

Approach to Second Order Circuits (Sinusodial Steady-State)

1) Replace the primitive elements with their impedance models and solve the network like a resistor network.

2) Put the equation into the form of a real amplitude and a complex phase.

3) Match the coefficient V and phase shift

and

*notice that at the resonant frequency , the magnitude of the output is just R, and the LC

circuit just behaves as if nothing is there (=open circuit). See circuit #1.

If the input was a sine wave instead of a cosine wave, then we would add an additional phase shift of

90 degrees, since sin( t)=cos( t- ). Thus, our new phase shift would be

Vh Aeα α2 ωo

2––( )t–Be

α α2 ωo2–+( )t–

+=

Vh Ae αt– Bte αt–+=

Vh Ae αt– ωdtcos Be αt– ωdsin t+=

Vp Vi=

v 0( ) i 0( ),

Vo Vp Vh+ Vi Ae αt– ωdtcos Be αt– ωdtsin+ += = iL Ce αt– Aωd ωdtsin– Bωd ωdtcos+( )=

Vo 0( ) Vi A+ 0= = A∴ Vi–= iL 0( ) CBωd 0= = B∴ 0=

Vo Vi 1 e αt– ωdtcos–( )= iL ViCωde α t– ωdtsin=

Rii Vc=Vo

+

-CLiL Vo

˜ 11

sL------ sC 1

R---+ +----------------------------------- ii

˜ jωL

1 ω2LC– jωL

R---+

----------------------------------------- ii˜= =

ii = I cos(wt) Vo V ωt φ+( )cos=

Vo˜ ωL

1 ω2LC–( )

2ωL

R--- 2

+

------------------------------------------------------------Ie

j 0ωL

R---

1 ω2LC–( )

-----------------------------

atan–

=

imaginary part

real part

φ

V ωL

1 ω2LC–( )

2ωL

R---

2+

------------------------------------------------------------I= φωL

R---

1 ω2LC–( )

-----------------------------

atan–=

ωo1LC

-----------=

ω ω π2--- φ' π

2--- φ–=

3. Second Order Circuits

Page 9

Poles & Zeros

obtain a transfer function of the system by replacing d/dt with s, which is also equal to j ,

Break Point Frequency:

Poles and Zeros are break point frequencies. Equate real and imaginary parts for each term in the numerator and denominator (i.e., factor and find the roots) to get the break point frequencies:

numerator:

denominator: and

Magnitude Plot

short cut: "zeros" give you a +1 slope. (constant before , +1 slope after ; in log scale)

"poles" give you a -1 slope. (constant before , -1 slope after ; in log scale)Thus, Z1: 0 +1 +1

P1: 0 0 -1P2: -1 -1 -1

: -1 0 -1

Since , which is the left most end of the frequency axis (in log scale), the magnitude plot starts off at -1 slope.

Approach to Plotting Magnitude1) Find all ZEROs and POLEs. (i.e., ’s)2) Draw and Label Axes. Denote break point frequencies.3) Beginning at the far end of the -axis, plot for very small

if ZERO at =0, start with +1 slope, (+2 slope if double Zero@ =0, and +3 for triple, ...)POLE at =0, start with -1 slope, (-2 slope if double Pole@ =0, and -3 for triple, ...)otherwise, start with a constant. (label!)

ω

H jω( ) 10 100sτ+( )sτ 10 sτ+( )

-------------------------------= 10 j 100ωRC( )+jωτ 10 jωRC+( )-----------------------------------------= roots of the numerator are "zeros"

roots of the denominator are "poles"

ωBP

ωz11

10RC--------------=

ωp1 0= ωp210RC--------=

ωz ωz

ωp ωp

ωp1 ωz1 ωp2

∑

ωp1 0=

110RC-------------- 10

RC--------

H jω( )

10

-1 slope

-1 slopeconstant

ω

*both axes are in log scale.

actual

asymptotedifference = 3dB

endlessωz1 ωp2

100

1

1RC-------- 100

RC---------

ωBP

ω ω

ω ω

ω ω

4. Magnitude & Phase Plots

Page 10

4) As you come up on the frequency axis, for each POLE you hit, go down by -1 slope, for each ZERO you hit, go up by +1 slope.

5) At , your actual curve will be off from the sharp asymptote corner by 3dB.

Phase Plotshort cut: "zeros" give you a + phase over decade.

"poles" give you a - phase over decade.

example,

Thus, Z1: 0 0 + + + +

P1: - - - - - -

P2: 0 0 0 0 - -

: - - - 0 - -

Approach to Plotting Phase1) Find all ZEROs and POLEs. (i.e., ’s)2) Draw and label all axes and break point frequencies, including their +/- decades.3) Beginning at the far left of the -axis, plot for very small

if ZERO at =0, start with + phase, (+ slope if double Zero@ =0, and + for triple, ...)

POLE at =0, start with - phase, (- slope if double Zero@ =0, and - for triple, ...)

otherwise, start at 0 phase.

4) As you come up the -axis, for each POLE you hit, make a change of - phase over a decade.

ωBP

π2--- ±

π2--- ±

0

π4---

π2---

ωz 10ωzωz10------

ω

H jω( )∠

starts a decade before ends a decade after

*note that the asymptote is back to a constantunlike the magnitude case, where the slope continued

π4---

π2---

π2---

π2---

π2---

π2---

π2---

π2---

π2---

π2---

π4---

π2---

ωp1 ωz1 ωp21100RC-----------------

1RC-------- 100

RC---------

∑ π2--- π

2--- π

4--- π

4--- π

2---

H jω( )∠

ωωz1 ωp2

1100RC----------------- 1

RC-------- 100RC---------

0

π4---–

π2---–

actual

asymptote

difference = 6o

ωBP

ω ω

ω π2--- π ω 3π

2------

ω π2--- π ω 3π

2------

ω π2--- ±

4. Magnitude & Phase Plots

Page 11

( ). For each ZERO, make a change of + phase over a decade.

5) Be careful when the regions overlap, the effect from each pole and zero may cancel each other out.6) At , the actual curve is off by 6o.

Bode Plot Building Blocks

ωp10------- ωp 10ωp∼ ∼ π

2--- ±

ωBP

H jω( ) S1S--- S 100+

1S 100+------------------

H jω( )

H jω( )∠

+1 +1 +1+1

π2---

π2---–

π2---

π4---

π2---–

π4---–

100

100010

100

100

100010 1000

0

4. Magnitude & Phase Plots

Page 12

Boolean Logic

*become comfortable expressing in different forms: truth table formula gates transistor level.

*Note that in the transistor-level implementation, transistors in series form an AND expression and those in parallel form an OR expression. The final output is always inverted in the pull-up implementation, equivalent to adding a NOT(inverter) to the output.

Primitive Rules

A + (B + C) = (A + B) + C A (B C) = (A B) C (associative)A + B = B + A A B = B A (communative)A + (B C) = (A + B) (A + C) A (B + C) = (A B) + (A C) (distributive)A + 1 = 1 A 0 =0A + 0 = A A 1 = AA + A = 1 A A = 0 (complement)A + A = A A A = A (idempotence)A + (A B) = A A (A + B) = A (absorption)A + (A B) = A + B A (A + B) = A B (absorption)

DeMorgan’s Laws

1) Gate Equivalent: =

2) Gate Equivalent: =

Minimum Sum of Products(MSP): (1)first level AND’s, (2) combine with OR’s. ex) (A B) + (B C)Minimum Product of Sums(MPS): (1)first level OR’s, (2) combine with AND’s. ex) (A+B) (B+C)

Common Gates

↔ ↔ ↔

A B C OUT00001111

00110011

01010101

10101000

↔ AB

C OUT

OUT A B⋅( ) C+=

↔A

BC

OUT

pull-up resistor

nMOS Logic

↔A

BC

OUT

A B

C

CMOS Logic

⋅ ⋅ ⋅ ⋅⋅ ⋅

⋅ ⋅ ⋅ ⋅ ⋅⋅⋅⋅⋅

⋅ ⋅⋅ ⋅ ⋅

A B⋅ A B+= CAB

AB

C

A B+ A B⋅= CAB

AB

C

⋅ ⋅⋅

AB

AB

AB

NAND NOR XOR

A B C0 0 10 1 11 0 11 1 0

A B C0 0 10 1 01 0 01 1 0

A B C0 0 00 1 11 0 11 1 0

AB

XNOR

A B C0 0 10 1 01 0 01 1 1

CAB

OR

A B C0 0 00 1 11 0 11 1 1

C C C CAB

AND

A B C0 0 00 1 01 0 01 1 1

C

5. Digital Abstraction

Page 13

Large Signal Model

S Model: SR Model:

VGS < VT VGS VT VGS < VT VGS VT

When (VDS VGS - VT), When (VDS < VGS - VT),

SCS Model (Saturation): SVR Model (Linear):

VGS < VT VGS VT VGS < VT VGS VT

MOSFET characteristics Load Line superimposed on MOS characteristicsfor operating point analysis of MOSFET Amplifier

MOSFET Amplifier

MOSFET Amplifier Large Signal Model(SCS) Small Signal Model Operating Point@VI

Small Signal gain: *Note that the output is a function of both VI(DC) and vi(AC).

Large Signal Model (SCS) is used to obtain the operating point, and Small Signal Model is used to obtain the output using Linear Approximation as shown on the right above. The Linear Approximation line is different for each VI.

D

G

S

On

D

G

S

Off

D

G

S

OnRon

D

G

S

Off

≥ ≥

≥

D

G

S

D

G

S

Off On

iDS=K(VGS-VT)2

2

D

G

S

OnRon=

K(VGS-VT)1

D

G

S

Off

≥ ≥

VGS1

VGS2

VGS5

VGS3

VGS4

Saturation Region

Line

ar R

egio

n

VD

S =

VG

S - V

VDS

iDS

VDS < VGS - VT VDS > VGS - VT

VGS1

VGS2

VGS5

VGS3

VGS4

VDS

iDS

-1RL

VS

RL

VS

Load Line

Operating Point

VO

VS

RL

+_VIiD=

K(VI-vT)2

2

vO

VS

+_VI+vi

vO

+_vi

vO

id=K(vI-vT)vi

RL(VI,VO)

vO

vIvi

vO

Linear for small vi

vovi----- K VI vT–( )RL– gmRL–= =

6. MOSFET Transistor (n-channel)

Page 14

Noise Margins

To improve noise margins: (1) increase VIL and lower VIH, and/or (2) increase VOH and lower VOL.(1) : increase vT of the MOSFET. This would make the transistor to turn on at a higher threshold

voltage, increasing VIL and lowering VIH.

(2): increase load resistance RL or (W/L) ratio of the MOSFET since and .

Parameter Value (for small signal model) Parameter Value (for small signal model)

Input Resistance Current Gain ; = if Ri=

Output Resistance Power Gain ; = if Ri=

∞K VI vT–( ) RL RO||( )

RiRO-------- ∞ ∞

RL K VI vT–( ) RL RO||( )[ ]2 Ri

RO-------- ∞ ∞

VIHVIL

VOL

VOH

VO

VI

need high gain

for large noise margins

Inverter characteristic curve

(1)

(2)

VIHVILVOL VOH

Valid ValidHighLow

Noise Margin "Low" Noise Margin "High"

Forbidden Zone

Noise Margins

VORon

Ron RL+---------------------∝ RonLW-----∝

6. MOSFET Transistor (n-channel)

Page 15

Model

• Operations* The Difference (V+ - V-) is amplified by A(~106) as Vout. The + and - terminal inputs have infinite

impedance, so no current flows into the terminals. Most Op-Amp circuits makes use of negative feedback where output tries to follow the input. A typical op-amp has output limits imposed by the power supply of +/- 15V.

• Approach1) Set V+=V-. (ideal op-amp w/ negative feedback)2) Do KCL at + and - terminal. (no current flows into the + and - terminals)3) Solve for the expression Vo/Vi.

Negative Feedback

• Inverting Op Amp:

* No current flows into the + and - terminals.* Vout=A(V+-V-) => V+-V- = Vout/A ~ 0. Thus, V+=V-.

* KCL @ V-, . In General, thus,

* Input Resistance: ; if ri= , ri term goes away

* Output Resistance:

• Non-inverting Op Amp:

* * Input Resistance: * Output Resistance:

V+

V-

+

-Vout

+-

A(V+-V-)V+

V-+-

Vout

Vin

+

-Vout

+- A(V+-V-)

Vin

+

-Vout

Rf

Ri

Rf

Ri

+- A(V+-V-)

Vin+-

Vout

Rf

Ri rt

ri

op-amp abstraction op-amp model more accurate op-amp model

VoutRfRi-----Vin–= Vout

ZfZi-----Vin–=

VoutVin---------- H jω( )

ZfZi-----–= =

Ri ri Rf rt+( )Rf rt+

A--------------- Rf rt+

A---------------≈|| ||= ∞

Rort

1 ARs

Rs Rf+-----------------+------------------------------

rt

ARs

Rs Rf+--------------------------------------≈=

Vin +-

Vout+- A(V+-V-)

VinVout

R2

R1

rt

ri

op-amp abstraction op-amp model more accurate op-amp model

R2

R1+-

+- A(V+-V-)

VinVout

R2

R1+-

VoutR1 R2+

R2------------------Vin= Ri ri

AR2R1 rt R2+ +-----------------------------≈ Ro

rt

AR2

R1 R2+-----------------------------------------≈

7. Op-Amp Circuits

Page 16

Important Circuits

Adder Subtractor

Integrator Differentiator Double Integrator

Integrator Differentiator Double Differentiator

Several of these op-amp circuits may be cascaded in stages. For such cases, you may find the Vo/Vi relationship for each stage using impedances and multiply them together to obtain the total Vo/Vi.

example:

V1

+

-Vout

R3R1

V2R2

V1

+

-Vout

R2R1

V2R1 R2

VoR3R1------V1

R3R2------V2+

–= VoR2R1------ V2 V1–( )=

Vin

+

-Vout

Cf

RiVin

+

-Vout

CiRf

Vin

+

-Vout

LiCf

Vo1

RC-------- Vi td∫= Vo RC tddVi= Vo

1LC------- Vi td td∫∫=

Vin

+

-Vout

LfRi

Vin

+

-Vout

LiRf

Vin

+

-Vout

LfCi

VoRL--- Vi td∫= Vo

LR--- td

dVi= Vo LCt2

2

d

d Vi=

+-

+-

+-

L

C

Vo

Vi

R

R

R

R td

dVi RCt2

2

d

d Vo– 2td

dVo– RL---Vo–=

Va

Vb

VaRL--- Vo td∫–=

Vb Vi– RC td

dVo–=

VoVa Vb+

2--------------------=

Thus,

7. Op-Amp Circuits

Page 17

nMOS InverterStatic: Vin [0,T/2] = high Dynamic:

Combining static and dynamic average power,

; note

When RL >> Ron,

Pstatic independent of frequency. Pdynamic related to switching capacitorMOSFET on half the time.

CMOS InverterDynamic: Vin [0,T/2] = high Dynamic: Vin [T/2,T]= low

*No static power dissipation (in ideal CMOS). This is done by implementing nMOS logic function and pMOS logic function to be opposites, using DeMorgan’s Law. This ensures that only one function (either nMOS OR pMOS) is true, shorting the output either to ground OR supply voltage.

Ex, from top of Sec. 5 Digital Abstraction,nMOS function: (AB)+C ➔ take the the opposite function: (AB)+C ➔ Use DeMorgan’s Law: (AB)+C = (AB) C = (A + B) C ; the result is the pMOS function(note, transistors in series constitutes an AND, and in parallel constitutes an OR)

Ways to reduce power... • Reduce switching speed : reduce f• Reduce supply voltage : reduce Vsupply• Reduce circuit elements; efficient circuit implementation : reduce C• Turn off clock when not in use : reduce f for part of the chip

OUT

pull-up resistor

nMOS Logic

VinC

RL

Vsupply

T

T/2 >> RC

OUT

nMOS Logic

RonC

RL

Vsupply

PVsup

2

2 RL Ron+( )------------------------------=

Since it’s for [0,T/2]which is half the period

OUT

nMOS Logic

Vsupply

C

RL

Ron

P CVdelta2f=

Vsup

0

Vout

PVsup

2

2 RL Ron+( )------------------------------ C+ V⋅

sup

2

fRL

2

RL Ron+( )2-----------------------------⋅ ⋅= Vdelta Vsup

RLRL Ron+( )

--------------------------=

PVsupply

2

2RL-------------------- C+ V⋅

sup

2

f⋅=

CMOS Logic

OUT

C

Vin

T

T/2 >> RC

Vsupply

OUT

CMOS Logic

Vsupply

CRonN

PC V⋅ sup

2 f⋅2----------------------------= OUT

CMOS Logic

Vsupply

C

RonP

PC V⋅ sup

2 f⋅2----------------------------=

P C V⋅ sup2 f⋅=

P C V⋅ supply2 f⋅=

8. Energy and Power

Page 18

Diode

• Model

DC Analysis: For the large signal model, the diode acts like a short with a voltage drop of 0.6V when the diode is on(Vd>0.6V), and like an open when the diode is off(Vd<0.6V).

where Amps for Silicon diodes.

AC Analysis: For the incremental model, the diode acts like a current dependent resistor. The resistor

value is set by the nominal(DC) operating current Id.

• Half-wave Rectifier: Clips the negative portion of the input wave and passes only the positive portion of the input wave with a diode drop of 0.6V.

• Peak Detector

Good Luck!12. 10. 2003. JK.

www.mit.edu/~jkim/6.002comments to jkim@mit.edu

+ -0.6V+ -VD

OR

"off"

"on"id

VD0.6V

slope=gd=1/Rd id+ -0.6V Rd

iD Is e

qVDkT----------

1–

= Is 10 12–∼

rdKTqId-------- 26mV

Id---------------= =

+ -VD

+Vi R+

__ Vo

ViVo0.6V

t

"on""off"

"on"Vi– iDR VD+ + 0=

+ -VD

+Vi

R+

__ Vo

Vi

Vo

t

"on""off"

"on"

C

*using ideal diode

9. Non-Linear Circuits