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1
EKT 441
MICROWAVE COMMUNICATIONS
CHAPTER 6:
MICROWAVE AMPLIFIERS
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INTRODUCTION
Most RF and microwave amplifiers today used transistor devices
such as Si or SiGe BJTs, GaAs HBTs, GaAs or InP FETs, or GaAs
HEMTs.
Microwave transistor amplifiers are rugged, low cost, reliable andcan be easily integrated in both hybrid an monolithic integrated
circuitry.
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General Amplifier Block Diagram
...33221 TOHtvatvatvatv iiio
Input and output voltage relation of the amplifier
can be modeled simply as:
VccPLPin
The active
component
vi(t)
vs(t)
vo(t)
DC supply
ZLVs
Zs AmplifierInput
Matching
Network
Output
Matching
Network
ii(t)
io(t)
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Small-Signal Amplifier (SSA)
All amplifiers are inherently nonlinear.
However when the input signal is small, the input and output
relationship of the amplifier is approximately linear.
This linear relationship applies also to currentand power.
An amplifier that fulfills these conditions: (1) small-signal operation (2)
linear, is called Small-Signal Amplifier (SSA). SSA will be our focus.
If a SSA amplifier contains BJT and FET, these components can be
replaced by their respective small-signal model, for instance the
hybrid-Pi model for BJT.
tvaTOHtvatvatvatv iiiio 133221 ...
When vi(t)0 (< 2.6mV) tvatv io 1 (1.1)Linear relation
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Example 1.1 - An RF Amplifier Schematic (1)
ZLVs
Zs AmplifierInput
Matching
Network
Output
Matching
Network
DC supply
RF power flow
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Typical RF Amplifier Characteristics
To determine the performance of an amplifier, the following
characteristics are typically observed.
1. Power Gain.
2. Bandwidth (operating frequency range).
3. Noise Figure. 4. Phase response.
5. Gain compression.
6. Dynamic range.
7. Harmonic distortion.
8. Intermodulation distortion.
9. Third order intercept point (TOI).
Important to small-signal
amplifier
Important parameters of
large-signal amplifier
(Related to Linearity)
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Power Gain
For amplifiers functioning at RF and microwave frequencies, usuallyof interest is the input and output power relation.
The ratio of output power over input power is called the Power Gain
(G), usually expressed in dB.
There are a number of definition for power gain as we will see shortly.
Furthermore G is a function of frequency and the input signal level.
dBlog10PowerInputPowerOutput10
GPower Gain (1.2)
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Why Power Gain for RF and Microwave
Circuits? (1)
Power gain is preferred for high frequency amplifiers as the
impedance encountered is usually low (due to presence of parasitic
capacitance).
For instance if the amplifier is required to drive 50 load the voltage
across the load may be small, although the corresponding current
may be large (there is current gain).
For amplifiers functioning at lower frequency (such as IF frequency), it
is the voltage gain that is of interest, since impedance encountered is
usually higher (less parasitic).
For instance if the output of IF amplifier drives the demodulator
circuits, which are usually digital systems, the impedance looking into
the digital system is high and large voltage can developed across it.
Thus working with voltage gain is more convenient.
Power = Voltage x Current
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Why Power Gain for RF and Microwave
Circuits? (2)
Instead on focusing on voltage or current gain, RF engineers focus on
power gain.
By working with power gain, the RF designer is free from the
constraint of system impedance. For instance in the simple receiver
block diagram below, each block contribute some power gain. A large
voltage signal can be obtained from the output of the final block byattaching a high impedance load to its output.
LO
IF Amp.BPF
LNABPF
RF Portion
(900 MHz)
IF Portion
(45 MHz)
RF signal
power
1 W
15 W
IF signal
power
75 W
7.5 mW
400
t
v(t) 4.90 V
R
VaverageP 2
2
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Harmonic Distortion (1)
ZLVs
Zs
When the input driving signal issmall, the amplifier is linear.
Harmonic components are
almost non-existent.
Harmonics generation reduces the gain
of the amplifier, as some of the output
power at the fundamental frequency is
shifted to higher harmonics. This result in
gain compressionseen earlier!
ff1harmonics
ff1 2f1 3f1 4f10
Small-signal
operation
region
Pout
Pin
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Harmonic Distortion (2)
ZLVs
Zs
When the input driving signal istoo large, the amplifier becomes
nonlinear. Harmonics are
introduced at the output.
Harmonics generation reduces the gain
of the amplifier, as some of the output
power at the fundamental frequency is
shifted to higher harmonics. This result in
gain compressionseen earlier!
ff1
f
harmonics
f1 2f1 3f1 4f10
Pout
Pin
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Power Gain, Dynamic Range and Gain
Compression
Dynamic range (DR)
1dB compression
Point (Pin_1dB)
Saturation
Device
Burn
out
Ideal amplifier
1dBGain compression
occurs here
Noise Floor
-70 -60 -50 -40 -30 -20 -10 0 10
Pin
(dBm)20
Pout(dBm)
-20
-10
0
10
20
30
-30
-40
-50
-60
Power gain Gp=
Pout(dBm) - Pin(dBm)= -30-(-43) = 13dB
Linear Region
Nonlinear
Region
Pin Pout
Input and output at same frequency
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Bandwidth
Power gain G versus frequency for small-signal amplifier.
f / Hz0
G/dB
3 dB
Bandwidth
PodBm
PidBm PodBm
PidBm
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Intermodulation Distortion (IMD)
...33221 TOHtvatvatvatv iiio
tvi tvo
ignored
ff1 f2
|Vi|
These are unwanted components, caused by
the term 3vi3(t), which falls in the operating
bandwidth of the amplifier.
ff1-f2
2f1-f2 2f2-f1
f2f1 2f1
f1+f2 2f2
3f1 3f2
2f1+f2 2f2+f1
|Vo|
IMD
Operating bandwidth
of the amplifier
Two signals v1, v2with similar
amplitude, frequencies f1and f2
near each other
Usually specified
in dB
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Noise Figure (F)
Vs
The amplifier also introduces noise into the output inaddition to the noise from the environment.
Assuming small-signal operation.
Noise Figure (F)= SNRin/SNRout
Since SNRinis always largerthan SNRout, F > 1 for an
amplifier which contribute noise.
SNR:
Signal to Noise
Ratio
Smaller SNRin
Larger SNRout
Zs
ZL
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Power Components in an Amplifier
ZLVs
Zs Amplifier
Vs
Zs
ZLZ1
Z2
VAmp+
-
PAoPL
PRo
PAs
PRs
Pin
2 basic source-load networksApproximate
Linear circuit
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Power Gain Definition
From the power components, 3 types of power gain can be defined.
GP, GAand GTcan be expressed as the S-parameters of the amplifier
and the reflection coefficients of the source and load networks. Refer
to Appendix 1 for the derivation.
As
LT
As
AoA
in
Lp
P
PG
P
P
G
P
PG
powerInputAvailable
loadtodeliveredPowerGainTransducer
powerInputAvailable
PowerloadAvailable
GainPowerAvailable
Amp.power toInput
loadtodeliveredPowerGainPower
The effective power gain
(2.1a)
(2.1b)
(2.1c)
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Naming Convention
ZLVs
Zs Amplifier
2 - port
Network
1 2
Source
NetworkLoad
Network
sL
2221
1211
ss
ss
In the spirit of high-frequency circuit design,
where frequency response
of amplifier is characterized
by S-parameters and
reflection coefficient is
used extensivelyinstead of impedance,
power gain can be expressed
in terms of these parameters.
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TWO-PORT POWER GAIN
Figure 7.1: A two port network with general source and load impedance.
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Power Gain Definition
From the power components, 3 types of power gain can be defined.
GP, GAand GTcan be expressed as the S-parameters of the amplifier
and the reflection coefficients of the source and load networks. Refer
to Appendix 1 for the derivation.
As
LT
As
AoA
in
Lp
P
PG
P
P
G
P
PG
powerInputAvailable
loadtodeliveredPowerGainTransducer
powerInputAvailable
PowerloadAvailable
GainPowerAvailable
Amp.power toInput
loadtodeliveredPowerGainPower
The effective power gain
(2.1a)
(2.1b)
(2.1c)
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TWO-PORT POWER GAIN
Power Gain= G=PL/ Pinis the ratio ofpower dissipated in the loadZLtothepower delivered to the inputof the two-port network. This gain is
independent of Zsalthough some active circuits are strongly dependent on
ZS.
Available Gain= GA=Pavn/ Pavsis the ratio of thepower available from
the two-port networkto thepower available from the source. This assumesconjugate matching in both the source and the load, and depends on ZSbut
not ZL.
Transducer Power Gain= GT=PL/ Pavsis the ratio of thepower delivered
to the loadto thepower available from the source. This depends on both ZS
and ZL.
If the input and output are both conjugately matchedto the two-port, then
the gain is maximized and G= GA= GT
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TWO-PORT POWER GAIN
2221212221212
2121112121111
VSVSVSVSV
VSVSVSVSV
L
L
0
0
22
211211
1
1
1 ZZ
ZZ
S
SSS
V
V
in
in
L
Lin
From the definition of S parameters:
[7.1a]
[7.1b]
Eliminating V2-from [7.1a]:
[7.2]
0
0
11
211222
2
2
1 ZZ
ZZ
S
SSS
V
V
out
out
S
Sout
[7.3]
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TWO-PORT POWER GAIN
in
inin ZZ
1
10
inS
SSVV
1
1
21
By voltage division:
ininS
inS VVV
ZZ
ZVV
11111
Using:
Solving for V1+:
[7.4]
[7.5]
[7.6]
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TWO-PORT POWER GAIN
22
2
0
2
2
1
0
11
1
81
2
1in
inS
SS
ininZ
VV
ZP
22
22
222
21
0
2
2
22
22
21
0
2
1
11
11
8
1
1
2
inSL
SLS
L
L
L
S
S
Z
V
S
S
Z
VP
20
22
12
LLZ
VP
The average power delivered to the network:
The power delivered to the load is:
[7.7]
[7.8]
[7.9]
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TWO-PORT POWER GAIN
222222
21
11
1
Lin
L
in
L
S
S
P
PG
22
0
2
1
1
8S
Ss
inavsZ
VPP
Sin
outL
outL
inSout
Souts
Lavn
S
S
Z
VPP
22
22
22221
0
2
11
11
8
The power gain can be expressed as:
The available power from the source:
The available power from the network:
[7.10]
[7.11]
[7.12]
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TWO-PORT POWER GAIN
2211
22
21
0
2
11
1
8outS
Ss
avn
S
S
Z
VP
211222
21
11
1
Sout
S
avs
avnA
S
S
P
PG
22
22
22221
11
11
inSL
LS
avs
LT
S
S
P
PG
The power available from the network:
The available power gain:
The transducer power gain:
[7.13]
[7.14]
[7.15]
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Summary of Important Power Gain Expressions
and the Gain Dependency Diagram
s
s
L
L
s
s
ss
1 1
2 2
2
2 2
1 1
1
1
1
21
222
22
21
11
1
L
LP
s
sG
2
22
11
2212
11
1
s
s
As
s
G
21
222
2221
2
11
11
sL
sL
Ts
s
G
Note:All GT, GP, GA, 1and 2
depends on the S-
parameters.
(2.2a)
21122211ssss
(2.2b)
(2.2c)
(2.2d)
(2.2e)
s L
1 2
GA GP
GT
2221
1211
ss
ss
The Gain Dependency Diagram
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TWO-PORT POWER GAIN
2
21SGT
A special case of the transducer power gain occurs when both input and
output are matched for zero reflection (in contrast to conjugate
matching).
Another special case is the unilateral transducer power gain, GTUwhere
S12=0 (or is negligibly small). This nonreciprocal characteristic is
common to many practical amplifier circuits. in= S11when S12= 0, so
the unilateral transducer gain is:
2
22
2
11
22221
11
11
inS
LS
TU
SS
SG
[7.16]
[7.17]
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TWO-PORT POWER GAIN
Figure 7.2: The general transistor amplifier circuit.
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TWO-PORT POWER GAIN
2
22
2
2
210
2
2
1
1
1
1
L
L
L
Sin
S
S
SG
SG
G
The separate effective gain factors:
[7.18a]
[7.18b]
[7.18c]
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TWO-PORT POWER GAIN
If the transistor is unilateral, the unilateral transducer gain reducesto GTU= GSG0GL, where:
2
22
2
2
210
211
2
1
1
1
1
L
L
L
S
S
S
S
G
SG
S
G
[7.19c]
[7.19b]
[7.19a]
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Example 1Familiarization with the Gain
Expressions
An RF amplifier has the following S-parameters at fo: s11=0.3
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Example 1 Cont...
Step 1 - Find s and L .
Step 2 - Find 1and 2.
Step 3 - Find GT, GA, GP.
Step 4 - Find PL, PA.
151.0146.022
11
11 j
L
L
s
Ds
358.0265.0111
222 j
sssDs
111.0
osos
ZZ ZZs 187.0
oLoL
ZZ ZZL
742.1311
12
1
2
22
22
21
L
L
s
sG
739.14
11
1
22
211
221
2
s
s
A
s
s
G
562.1211
11
21
222
2221
2
sL
sL
Ts
s
G
WP ss
Z
VA 078.0Re8
2
WZPPosZZ
sZZ
Ain
0714.012
1
1
WPGP inPL 9814.0
Try to derive
These 2 relations
Again note that this is an
analysis problem.
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STABILITY
In the circuit of Figure 7.2, oscillation is possible if either the input oroutput port impedance has the negative real part; this would imply that
|in|>1 or |out|>1.
inand outdepends on the source and load matching networks, the stability
of the amplifier depends on Sand Las presented by matching networks.
Unconditionally stable: The network is unconditionally stable if |in| < 1
and |out| < 1 for all passive source and load impedance(ex; |S| < 1 and
|| < 1).
Conditionally stable: The network is conditionally stable if |in| < 1 and
|out| < 1 only for a certain range of passive source and load impedance.
This case also referred as potentially unstable.
The stability condition of an amplifier circuit is usually frequency
dependent.
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STABILITY CIRCLES
11 22
211211
L
Lin
S
SSS
11
1 1
2 11 2
2 2
S
S
ou t
S
SSS
The condition that must be satisfied by Sand Lif the amplifier is
to be unconditionally stable:
[7.20a]
[7.20b]
The determinant of the scattering matrix:
21122211 SSSS [7.21]
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STABILITY CIRCLES
22
22
2112
22
22
1122
S
SSR
S
SSC
L
L
22
11
2112
22
11
2211
S
SSR
S
SSC
S
S
The output stability circles:
The input stability circles:
[7.22a]
[7.22b]
[7.23a]
[7.23b]
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STABILITY CIRCLES
Figure 7.3: Output stability circles for conditionally stable device.
(a) |S11
| < 1 (b) |S11
| > 1
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STABILITY CIRCLES
If the device is unconditionally stable, the stability circles must be
completely outside (or totally enclose) the Smith chart.
11
11
22
11
SRC
SRC
SS
LL[7.24a]
[7.24b]
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STABILITY TEST
12
1
2112
22
22
2
11
SS
SSK
121122211 SSSS
Rollets condition:
the auxiliary condition:
11
21121122
2
11
SSSS
S
thetest:
[7.25]
[7.26]
[7.27]
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Example 2
The S parameters for the HP HFET-102 GaAs FET at 2 GHz with abias voltage of Vgs = 0 are given as follow (Z0= 50 Ohm):
S11= 0.894 < -60.6
S21= 3.122 < 123.6
S12= 0.020 < 62.4S22= 0.781< -27.6
Determine the stability of this transistor using the K-test and the
test, and plot the stability circles on the Smith Chart
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Example 2
12
1
2112
2222
211
SS
SSK
121122211 SSSS
11
21121122
2
11
SSSS
S
For thetest:
Remember, criteria for unconditional stability is:For theK-test:
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Example 2
1607.02
1
2 112
22
22
2
11
SS
SSK
1696.0211 2221 1
SSSS
186.01
2 11 21 12 2
2
1 1
SSSSS
For thetest:
Calculation results:For theK-test:
Which indicates potential instability
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Example 2
Input stability circle and radius
Calculation for the input and output stability circles:Output stability circle center and radius:
50.0
47361.1
22
2 2
2 11 2
22
2 2
1 12 2
S
SSR
S
SSC
L
L
199.0
68132.1
22
1 1
2 11 2
22
1 1
2 21 1
S
SSR
S
SSC
S
S
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STABILITY
Figure 7.4: Example of stability circles
SINGLE STAGE TRANSISTOR
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SINGLE STAGE TRANSISTOR
AMPLIFIER DESIGN
Lout
Sin
2
22
22
2121
1
1
1ma x
L
L
S
T
SSG
Maximum power transfer from the input matching network to thetransistor and the maximum power transfer from the transistor to the
output matching network will occur when:
Then, assuming lossless matching sections, these conditions will
maximize the overall transducer gain:
[7.28a]
[7.28b]
[7.29]
SINGLE STAGE TRANSISTOR
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SINGLE STAGE TRANSISTOR
AMPLIFIER DESIGN
In the general case with a bilateral transistor, inis affected by out,
and vice versa, so that the input and output sections must be matched
simultaneously.
S
S
L
L
LS
S
SSS
S
SSS
11
2112
22
22
211211
1
1[7.30a]
[7.30b]
SINGLE STAGE TRANSISTOR
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SINGLE STAGE TRANSISTOR
AMPLIFIER DESIGN
2
2
2
2
22
1
2
1
2
11
2
42
4
C
CBBC
CBB
L
S
The solution is:
[7.31a]
[7.31b]
SINGLE STAGE TRANSISTOR
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SINGLE STAGE TRANSISTOR
AMPLIFIER DESIGN
11222
22111
2211
2222
22
22
2
111
1
1
SSC
SSC
SSB
SSB
The variables are defined as:
[7.32a]
[7.32b]
[7.32c]
[7.32d]
SINGLE STAGE TRANSISTOR
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SINGLE STAGE TRANSISTOR
AMPLIFIER DESIGN
2
22
2
212
11 1
1
1
1max
SS
SGTU
1212
21
ma x KK
S
SGT
12
21
S
SGmsg
When S12= 0, it shows that S= S11* and L= S22*, and the maximumtransducer gain for unilateral case:
The maximum stable gain withK = 1:
[7.33]
[7.34]
[7.35]
When the transistor is unconditionally stable,K> 1, and the maxtransducer power gain can be simply re-written as:
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Example 3
Design an amplifier for a maximum gain at 4.0 GHz. Calculate theoverall transducer gain, G, and the maximum overall transducer gain
GTMAX. The S parameters for the GaAs FET at 4 GHz given as follow
(Z0= 50 Ohm):
S11= 0.72 < -116S21= 2.60 < 76
S12= 0.03 < 57
S22= 0.73< -68
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Example 3 (Cont)
195.12
1
2 11 2
22
2 2
2
1 1
SS
SSK
162488.021122211
SSSS
Determine the stability of this transistor using theK-test
Since || < 1 andK> 1, the transistor is unconditionally stable at 4.0
GHz.
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54
Example 3 (cont)
For the maximum gain, we should design the matching sections for aconjugate match to the transistor. Thus, S= in* and L= out*, S
and Lcan be determined from;
61876.02
4
123872.02
4
2
2
2
2
12
1
2
1
2
21
C
CBB
C
CBB
L
S
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55
Example 3
dBS
GS
20.617.41
12
11
dBSG 30.876.62
210
dBS
GL
L
L22.267.1
1
12
2 2
2
So the overall maximum transducer gain will be;
The effective gain factors can calculated as:
dBGT
7.1622.230.820.6ma x
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56
UNILATERAL FOM
22
)1(
1
)1(
1
UG
G
UTU
T
In many practical cases |S12| is small enough to be ignored, the devicethen can be assumed to be unilateral, which greatly simplifies design
procedure
Error in the transducer gain caused by approximating |S12| as zero is
given by the ratio GT/GTU, and be bounded by:
Where Uis defined as the unilateral figure of merit
)1)(1( 2
2 2
2
1 1
2 21 12 11 2
SS
SSSSU
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57
Example 4
An FET is biased for minimum noise figure, and has the following Sparameters at 4 GHz:
S11= 0.60 < -60
S21= 1.90 < 81
S12= 0.05 < 26S22= 0.50< -60
For design purposes, assume the device is unilateral and calculate the
max error in GTresulting from this assumption.
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58
Example 4 (cont)
22 )1(
1
)1(
1
UG
G
UTU
T
059.0)1)(1(
2
22
2
1 1
2 21 12 11 2
SS
SSSSU
To compute the unilateral figure of merit;
Then the ratio of GT/GTUis bounded as;
130.1891.0 TU
T
G
G
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59
Example 4 (cont)
In dB, this is;
dBGGTUT
53.050.0
Where GTand GTUare now in dB. Thus we should expect less than
about 0.5 dB error in gain.
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60
CONSTANT GAIN CIRCLES
In many cases it is desirable to design for less than the max obtainablegain, to improve bandwidth or to obtain a specific value for an
amplifier gain.
Mismatches are purposely introduced to reduce the overall gain
Procedure is facilitated by plotting constant gain circles on the Smith
Chart Represents loci of Sand L,that give fixed values of GSand GL.
To simplify the discussion, we will only treat the case of a unilateral
device
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61
CONSTANT GAIN CIRCLES
2
1 1
2
1
1
S
S
S
SG
2
2 2
2
1
1
L
L
L
SG
2
111
1
max SG
S
The expression for the GSand GLfor the unilateral case is given by:
These gains are maximized when S= S11* and L= S22*:
2
221
1max
S
GL
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62
CONSTANT GAIN CIRCLES
)1(1
1 21 12
11
2
ma x
SSG
Gg
S
S
S
S
S
Now we define normalized gain factorsgSandgLas;
Thus we have a that: 0 gS 1, and 0 gL 1. A fixed value ofgSandgL
represents circles in the Sand Lplanes.
)1(1
1 22 22
2 2
2
max
SSG
Gg
L
L
L
L
L
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63
CONSTANT GAIN CIRCLES
211
2
11
2
11
11
11
11
11
Sg
SgR
Sg
SgC
S
S
S
S
SS
2
22
2
22
2
22
22
11
11
11
Sg
SgR
Sg
SgC
L
L
L
L
LL
Input constant gain circles:
Output constant gain circles:
[7.37a]
[7.37b]
[7.38a]
[7.38b]
E l
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64
Example 5
Design an amplifier to have a gain of 11 dB at 4 GHz. Plot constantgain circles for GS= 2 dB and 3 dB; and GL= 0 dB and 1 dB. The
FET has the following S parameters (Z0= 50 ):
S11= 0.75 < -120
S21= 2.50 < 80
S12= 0.00 < 0
S22= 0.60 < -85
E l 5 ( t)
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65
Example 5 (cont)
Since S12
= 0 and |S11
| < 1 and |S22
| < 1, the transistor is unilateral and
unconditionally stable. We calculate the max matching section gains
as;
The gain of the mismatched transistor is;
dBS
GS
6.329.21
12
11
max
dBS
GL
9.156.11
12
22
max
dBSG 0.825.62
210
E l 5 ( t)
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66
Example 5 (cont)
So the max unilateral transducer gain is
Thus we have 2.5 dB more available gain than required by specs,
since the design only requires 11 dB gain. However, the question alsoasked us to analyze the effect of having:
Condition 1: GS= 3 dB and GL= 0 dB
Condition 2: GS
= 2 dB and GL
= 1 dB
(Note that these conditions must happens at the same time in order to
keep the gain at 11 dB.)
dBGUT
5.130.89.16.3max
E l 5 ( t)
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67
Example 5 (cont)
875.0
max
S
S
S
G
Gg
For condition 1 (input side), when GS= 3 dB:
166.01111
120706.011
2
1 1
2
1 1
2
1 1
1 1
SgSgR
Sg
SgC
S
S
S
S
S
S
E l 5 ( t)
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68
Example 5 (cont)
For condition 1 (output side), when GL
= 0 dB:
440.0
1111
70440.011
2
2 2
2
2 2
2
2 2
2 2
SgSgR
Sg
SgC
L
L
L
L
L
L
640.0
max
L
L
L
G
Gg
E l 5 ( t)
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69
Example 5 (cont)
LOW NOISE AMPLIFIER DESIGN
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LOW NOISE AMPLIFIER DESIGN
In receiver applications especially, it is often required to have apreamplifier with as low a noise figure as possible since, the first
stage of a receiver front end has the dominant effect on the noise
performance of the overall system.
Generally it is not possible to obtain both minimum noise figure andmaximum gain for an amplifier, so some sort of compromise must
be made. This can be done by using constant gain circles and circles
of constant noise figure to select a usable trade of between noise
figure and gain.
2
min optS
S
N YYG
RFF [7.39]
LOW NOISE AMPLIFIER DESIGN
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LOW NOISE AMPLIFIER DESIGN
2
0
min 14
opt
N ZR
FFN
1
1
1
2
N
NNR
NC
opt
F
opt
F
For a fixed noise figure, F, the noise figure parameter, N, is given as:
The circles of constant noise figure:
[7.40]
[7.41a]
[7.41b]
E l 6
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Example 6
An GaAs FET amplifier is biased for minimum noise figure and hasthe following S-parameters (Z0= 50 ):
S11= 0.75 < -120
S21= 2.50 < 80
S12= 0.00 < 0S22= 0.60 < -85
opt= 0.62 < 100
Fmin= 1.6 dB
RN
= 20
For design purposes, assume the unilateral. Then design an amplifier
having 2.0 dB noise figure with the max gain that is compatible with
this noise figure.
E l 6 ( t)
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73
Example 6 (cont)
0986.014
2
0
min
opt
NZR
FFN
Next use the formulas to compute the center and radius of the 2 dB
noise figure circle:
The gain of the mismatched transistor is
24.011
10056.01
2
NNNR
NC
op t
F
o p t
F
E ample 6 (cont)
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74
Example 6 (cont)
The noise figure circle is plotted in the figure. Min noise figure (Fmin
= 1.6 dB) occurs for S= opt= 0.62
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Example 6 (cont)
For the output section we choose L
= S22
* = 0.5
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Example 6 (cont)