Chp 2- Mos Design and Layout

7/31/2019 Chp 2- Mos Design and Layout

1/104

MOS Design and Layout


2/104


3/104

Layout (the Final Frontier!)

Schematic

Transistors

Stick Diagram

VLSI Layout


4/104

pullup

network

VDD

pulldown

networkVSS

outinputs

CMOS Logic Circuits


5/104

Basic Idea = duality between pull-ups and pull-downs.

The structure of the pFET array is the dual of the nFET array!


6/104

Stick Diagrams VLSI design aims to translate circuit concepts onto

silicon.

Stick diagrams are a means of capturing topography

and layer information - simple diagrams.

Stick diagrams convey layer information throughcolor codes (or monochrome encoding.

Does not show exact placement, transistor sizes,

wire lengths, wire widths, tub boundaries, or anyother form of compliance with layout or design rules.

Useful for interconnect visualization, preliminarylayout, layout compaction, power/ground routing,

clock routing, etc.


7/104

MOS Layers in Stick DiagramsMetal 1

Metal 2

Poly

ndiff

pdiff

Can also draw

in shades of

gray/line style.

Blue

Purple

Red

Green

Yellow

ContactsBlack


8/104

PMOS and NMOS Stick Diagrams

S

D

G B

G B

D

S

NMOS Transistor

PMOS Transistor


9/104

Vdd

Vss

CMOS Inverter Stick Diagram

Demarcation Line

A A


10/104

CMOS NAND GATE

Vdd

Vss

A

B

O/P


11/104

Stick Diagram - Example I

NOR Gate

OUT

B

A


12/104

Logic Circuits -- Duality

1. Every input is connect to both an nFET and a pFET.

2. Two logic arrays are required - one for pull up to +5v,

one for pull down to ground.

3. When the inputs are stable, only one logic block conducts.

4. Series connected nFETs produce a NAND function.

Parallel connected nFETs produce a NOR function

5. Series connected pFETs produce a NOR function.

Parallel connected pFETs produce a NAND function


13/104

Stick Diagram - Example II

Power

Ground

B

C

OutA


14/104

Factors influencing MOS Layers in Stick Diagrams

Cost:

i) The Layer which costs more, should

be used few times.

ii) The Layer which costs less, shouldbe used frequently.

iii) The order of layers in terms of decreasing cost:

a)Polysilicon b) N-diff & P-diff c) Metal.

Complexity:

If the Layers cross over each other frequently, thencomplexity increases and vice-versa.


15/104

Logic Circuits I.

Multiplexer Example

A

S

BY

Y = S * A + S * B

Y = (S*A) + (S*B)

= (S*A) * (S*B)

Y = NAND( NAND(S,A),NAND(NOT(S),B))

DEF: (P*Q) = NAND(P,Q)


16/104

Y = NAND(NAND(S,A),NAND(NOT(S),B))

N

NS

A

Vss

Vd

P P

NAND(S,A)

N

P

NOT(S)


17/104

Y = NAND( NAND(S,A),NAND(S,B))

Vss

Vd

N

N

P P

B

NAND(NOT(S),B)S

A N

N

P P

N

P

S


18/104

Y = NAND(P,Q)

Vss

Vd

N

N

P P

B

S

A N

N

P P

N

P

P Q

N

N

P P

Y


19/104

Sticks Layout for 2:1 MUX

Vdd

Vss

A

BS

S

Area = 17 * 4 = 68 2


20/104

NMOS Encoding

Name of Layer Stick Encoding Color

Polysilicon Red

N-diff, N-active Green

Metal1 Blue

Implant Yellow

Contact Cut Black


21/104

NMOS Depletion and Enhancement


22/104

Stick diagram of nMOS invertor


23/104

NMOS Logic Example

Y=(A.B+C)

A

B C

VDD

VSS

Y


24/104

BiCMOS Encoding


25/104

Stick diagram of BiCMOS invertor


26/104

Layout


27/104

Why Design Rules

When "drawing layouts from stick diagram, there are rules that apply tospacing and sizes.

Scalability of Layout is achieved by defining the unit of measure of yourdrawing.

For example, if you draw a box to represent the diffusion mask, how big isthat box in terms of the actual size of the diffusion region created in thesilicon wafer?

One approach is to set up a translation between the scale used for thedrawing.

For example, when creating this Word document, there is a "ruler" on thetop defining the page, with units "1," "2," "3," etc.

These numbers represent inches when you print out the page withmagnification = 1.

The size of the box below is easily measured with a ruler.


28/104

DESIGN RULES

Mask layers are tools formanufacturing of ICs.

Manufacturing processes haveinherent limitations in accuracy.

Design rules specify geometry of

masks which will providereasonable yields. i.e. size andspacing of layers.


29/104

Design rules (Contd..)

Allow translation of circuits(usually in stick diagram orsymbolic form) into actual

geometry in silicon Interface between circuit

designer and fabricationengineer

Compromise

designer - tighter,smaller

fabricator - controllable,reproducible


30/104

Lambda Based Design Rules

Design rules based on single parameter, (lambda) :abstractunit.

Scale the design to the appropriate actual dimensions using(.25m) when the chip is to be manufactured.

Properties:

1) Simple for the designer

2) Wide acceptance

3) Provide feature size independent way of setting out mask

4) If design rules are obeyed, masks will produce working

circuits

5) Minimum feature size is defined as 2

6) Used to preserve topological features on a chip

7) Prevents shorting, opens, contacts from slipping out of area

to be contacted


31/104

Lambda Based Design Rules


32/104


33/104

Design rules for layers


34/104

Design rules for Transistors


35/104

Design rules for Contacts


36/104

Design rules for Contacts


37/104

Contact cuts

Butting Contact:

Poly to n-diff (p-diff)

using metal.


38/104

Double Metal Process Rules

Metal2 is another metal layer which isDark Blue or Purple.

Metal2 should be used for global powerand Clock rails.

Metal1 should be used for local signaland power rails.

The Contact between metal2 to metal1contact is calledVIA.


39/104

Advantages and Disadvantages

Advantages

Enables technology changes

Enable design reuse

Reduce design cost

Disadvantages Not optimal design


40/104

2 Double Metal Double PolyCMOS/BiCMOS Rules - Layers.


41/104

2 Double Metal Double PolyCMOS/BiCMOS Rules - Transistors


42/104

2 Double Metal Double PolyCMOS/BiCMOS Rules - Contacts


43/104

N-well Spacing and Width


44/104

BiCMOS NPN Transistor Layout


45/104

Interconnect - Wiring Concepts


46/104

Basic Wiring Concepts Interconnections between the Layers in the IC are represented by

wires.

These Wires have parameters such as

Resistance Capacitance

Delay

Rise and Fall Time Estimation.

These parameters have different values for different Technologies

(1.2m, 2m, 5 m).

Interconnect parameters impact

reduce reliability

effect performance and power consumption


47/104

Modern Interconnect


48/104

RESISTANCE


49/104

Sheet Resistance (Rs)

Resistance of a square slabof Conducting layer or

material is SheetResistance (Rs) .

Length (L) = Width (W)

Parameters of the layer.

Let is Resistivity

Let A is Area.

t w L

X

Y


50/104

Sheet Resistance (Rs)

Rs=/t where = Resistivity,

t = Thickness,

Rs is Independent of Area of square. Rs of Layers depends on Resistivity and Thickness.

For Poly and Metal Layers

Resistivity and Thickness are known easily.

For Diffusion layers Diffusion Depth - Thickness.

Doping Level Resistivity.


51/104

Sheet resistance for layers


52/104

Silicide

Silicides: WSi2, TiSi2, PtSi2and TaSi

Silicides are the interconnecting medium forthe Polysilicon due to its low resitivity thanPolysilicon.

Properties: Conductivity: 8-10 times better than Poly Resistivity : very less then Poly

Examples:


53/104

Silicide - Polycide Gate MOSFET

n+n+

SiO2PolySilicon

Silicide

p

Silicides: WSi2, TiSi2, PtSi2and TaSiConductivity: 8-10 times better than Poly

Resistivity : very less then Poly


54/104

Dealing with Resistance

Selective Technology Scaling

Use Better Interconnect Materials

reduce average wire-length

e.g. copper, silicides

More Interconnect Layers

reduce average wire-length


55/104

Interconnect Resistivity - Metals


56/104

Intel 0.25 micron Process

5 metal layers

Ti/Al - Cu/Ti/TiN

Polysilicon dielectric


57/104

CAPCITANCE


58/104

Area Capacitance of Layers

Conductive Layers are separated by

dielectric in MOS Transistor, so parallel

plate capacitive effects must be

present.

Area Capacitance is denoted by C.

C = 0insA / D Farads


59/104

Standard Area Capacitance values


60/104

Standard unit of Capacitance

Standard unit of Capacitance is the

gate to channel capacitance of MOS

Transistor having W=L feature size.

It is denoted by Cg.

Cg can be evaluated for MOStransistors of different feature size.


61/104

Multilayer capacitances


62/104

Wiring Capacitances


63/104

Area Capacitance - Parallel Plate Model

SiO2

Substrate

L

W

H

tox


64/104

Fringing fields Capacitance

For wide conductors with W >> H, capacitance to substrate (of any groundplane) can be determined as a parallel plate capacitor

For most real conductors in todays IC technology, fringing fields contributea major part of the line capacitance and must be included in thecapacitance calculations.

For W =~ H (below), fringing fields add more than the parallel plate portion tothe total line capacitance.!

R. W. KnepperSC571, page 4-15


65/104

Fringing Capacitance effect for different W,H values

W - H/2H

+

(a)

(b)

W>>H

W=H W=H/2


66/104

Fringing Capacitance: Values


67/104

Interlayer Capacitance

Substrate

SiO2

Insulator

Level1

Level2

Creates Cross-talk

The capacitance effects when multiple layers cross or underlies

another is known interlayer capacitance.

This Capacitance leads to Cross-talk.


68/104

Peripheral capacitance

N-diffusion regions form junction with p-well andP-diffusion regions form junction with n-well,which leads to Peripheral capacitance.

The smaller area of diffusion regions leads tohigh value of peripheral capacitance.

Diffusion formed by implant have negligible

peripheral capacitance due to negligible depth. This capacitance value is greater than area

capacitance.

Interconnect Cross-section for Dual Metal, Single Poly System


69/104


70/104

Delay Unit ()

When one standard gate area capacitance(1Cg) is charged through one feature size ofn-channel resistance (1Rs), then delay unit() is

= 1Rs x 1Cg sec.

Delay unit can be calculated for 5m, 2m,

1.2m technologies respectively.

value can be increased by a factor of 2 or 3,if we consider worst case delays.


71/104

Delay Unit ()

Delay unit value is approximately equal to Transit time(sd).

Since Transit time depends on Vds, so as Delay unit ().

So, can be calculated with Vds. All timings in the system can assessed with , so is

the fundamental time unit.


72/104

Inverter Delays


73/104

Series NMOS Inverters Delay

Pull-down delay = Rpd x 1 Cg

Pull-up delay = Rpu x 1 Cg

Asymmetry in rise and fall due to resistance differencebetween pull-up and pull-down (factor of 4) (due to

mobilities of carriers)

Delay through a pair of inverters is (fall time) + 4

(rise time)

Delay through a pair of NMOS inverters is therefore 5


74/104

Series CMOS Inverters Delay

Pull-down delay = Rpd x 2 Cg

Pull-up delay = Rpu x 2Cg

Asymmetry in rise and fall due to resistance differencebetween pull-up and pull-down (factor of 2.5) (due to

mobilities of carriers)

Delay through a pair of inverters is 2 (fall time) + 5

(rise time)

Delay through a pair of CMOS inverters is therefore 7


75/104

Formal Estimation of CMOS Inverter Delay

A CMOS Inverter discharges or charges through a Loadcapacitor CL , through which we can find Rise and FallTimes.

Rise Time Estimation:

Fall Time Estimation:


76/104

Factors effecting Rise and Fall Time Delays

Mobility:

Since mobility of electrons is 2.5 times greater thanmobility of holes, Rise times have 2.5 times more delay

than Fall times.So, the Width of P-Channel should be 2.5 times greaterthan n-channel.

Load capacitance:

Both Rise and Fall times are proportional. Source Voltage:

Both Rise and Fall times are inversely proportional.


77/104

Effects of Delay Unit

In high speed digital circuits, signals on an interconnect line

are delayed by , which places a limiting factor on the

speed of the network

VLSI processing are directed toward minimizing both

Rsand Cg.

Circuit designers are then faced with creating the fastest

switching network within the limits of delay.

Buffers may be used in long lines to reduce the total line

delay.


78/104

Propagation Delays


79/104

Cascaded Pass Transistors

Pass Transistors are used in series or parallel for switchlogic.

If a signal Vdd is sent through a series of pass transistors,

then the signal is degraded to Vdd-Vtp. A pass transistor can be assumed as RC network during

the operation.

Propagation Delay (p) can be calculated w.r.t distance xof the network.

Overall Delay (d) is of n pass transistors can also becalculated through the series RC network.

If n increases then d increases. So, the max value of n=4.


80/104

Long Poly and Diffusion wires

Long Polysilicon wires also represents RC networks,which increase signal delay.

This results in slow rise time and then noise.

If noise is present, output values will switch between0 and 1 for inverters.

Long Diffusion wires have high C value, which alsoincrease signal delay.

So both Poly and diffusion wires should be used forshorter distances only.


81/104

Minimizing Propagation Delay

In series pass transistors network, if a repeater is placed after 4

pass transistors, then delay will be decreased.

For Polysilicon wires, use of repeaters (buffers or inverters).

1) speed-up the rise time.

2) guard the effects of noise.

So the output will not be toggled especially for inverters.


82/104

Nature of Interconnect

Local Interconnect

Global Interconnect

SLocal = STechnology

SGlobal = SDie


83/104

IDEAL WIRE

No impact on electrical behaviour ofcircuits

Whole wire is an equi-potential region


84/104

Scaling of MOS Circuits


85/104

Scaling - Introduction

VLSI technology is constantly evolvingtowards smaller line widths

Reduced feature size generally leads to Better / faster performance

More gate / chip

More accurate description of moderntechnology is ULSI (ultra large scaleintegration.


86/104

Scaling - Introduction


87/104

Properties of IC effected by Scaling

Minimum feature size.

Number of gates on one chip.

Power dissipation.

Maximum operational frequency.

Die size

Production cost.


88/104

Full Scaling


89/104

Scaling Rules


90/104

Scaling Models

Constant Electric field Scaling

Constant Voltage Scaling

Combined Voltage and Dimensionscaling.


91/104



92/104

Constant Electric field ScalingBefore Scaling After scaling


93/104



94/104

Constant Voltage Scaling

Scaling Factors - Combined


95/104

Scaling Factors Combinedvoltage & Dimension scaling

In our discussions we will consider 2scaling factors, and

1/ is the scaling factor for VDD andoxide thickness D

1/ is scaling factor for all other linear

dimensions We will assume electric field is kept

constant

Scaling Factors for Device


96/104

Scaling Factors for DeviceParameters

It is important that you understand how the followingparameters are effected by scaling

Gate Area

Gate Capacitance per unit area

Gate Capacitance Charge in Channel

Channel Resistance

Transistor Delay

Maximum Operating Frequency

Transistor Current Switching Energy

Power Dissipation Per Gate (Static and Dynamic)

Power Dissipation Per Unit Area

Power - Speed Product


97/104

Limitations of scaling


98/104

Substrate Doping

Built-in-potential VB dependson substratedoping level NB.

VB should be added toVdd for obtainingeffective voltage.

To scale down depletion width, NB should beincreased andVB should also increase.

Then Vdd should also be scaled.

Now the total is the sum of VB andVdd


99/104

Channel Length (L)

Scaling of Length depends on photolithographictechnology.

If Channel length (L) scaling is more, then

depletion width decreases and depletion

region of source comes closer to drain.

To maintain proper transistor action, Channel Lengthshould be twice the depletion width.

It also depends on substrate doping and supplyvoltage.


100/104

Scaling Limits


101/104

Scaling of Interconnects

Resistance:

Resistance of track R ~ L / wt

R (scaled) ~ (L / ) / ( (w/ )*

(t /))

R(scaled) = R

Therefore resistance increaseswith scaling.

Thickness should be scaled lessto decrease resistance.

t w L

A

B


102/104

Scaling - Time Constant

Time constant of track connected to gate,

T = R * Cg

T(scaled) = R * ( / 2) *Cg = ( / ) *R*Cg

Let = , therefore T is unscaled!

Therefore delays in tracks dont reduce with scaling

Therefore as tracks get proportionately larger, effectgets worse

Cross talk between connections gets worse becauseof reduced spacing


103/104

Scaling - Time Constant (Contd..)

Scaling device dimensions lengthens theinterconnections in the chip.

So resistance, capacitance and time constant

increases. The effects are

1) Increased Propagation delay.

2) Signal decay.3) Clock Skew.

But delay of device will not increase.


104/104

Scaling - Time Constant (Contd..)

Remedies:

Multilayer interconnections with thicker and widerconductors reduce both R and C.

Inclusion of cascaded drivers and repeaters in longinterconnects.

Optical fibers, Lasers are used as longer interconnects dueto its advantage of high speed.

The values of R and C are very less for optical fibers whencompared to Metal (Al).

Integration of GaAs with optical fibers is more compatiblethan integration of Silicon with optical fibers

Documents

Chp 2- Mos Design and Layout