Chongli Cai Ailing Mei 9/11/2012

Iowa State University

EE 465 Lab Report Lab 3: Standard Cell Characterization

Chongli Cai

Ailing Mei

9/11/2012

Page 1 of 13

Introduction

In last lab, you have built the standard cell DFF with Cadence Virtuoso. In this lab, you will learn how to characterize the cell. In particular, the objective of this lab is to: Get to know about standard cell library, Learn simulation in analog environment and Perform cell characterization and analysis. For a signal rising from low voltage to high voltage, the

transition time (i.e., slew) is calculated starting at the point when the signal passes 30% of the

full voltage and stopping at the point when the signal passes 70% of the full voltage. The

definitions are similar for a falling signal. The delay for a rising signal is calculated starting at

the point when the input signal passes 50% of the full voltage and stopping at the point when the

output signal passes 50% of the full voltage. The definitions are similar for a falling delay.

Procedures and Analysis of Result In the last lab, we build the standard cell without considering power, size, delay etc. In this lab, we

will rebuild the DFF standard cell with considering both size and delay. For the task 1, we will make

the DFF with only considering the area, and for the task2 we will design the DFF to make it small in

area and as fast in timing as possible.

We design a positive-edge-triggered DFF as shown in the following Figure

Figure 1: DFF gate level schematic

Task 1: Try your best to redraw your DFF layout to make it as small in area (calculated in

layout environment) as possible.

Power supply: 1.3V

Maximum metal layer: 4

Page 2 of 13

Design Strategy:

In the task 1, we only need to consider the size, which means we need to make the size of the DFF

Standard Cell as small as possible. So we consider the minimum size strategy for both nmos and pmos,

which sets Wn =Wp= 1.5µ and Ln=Lp= 0.6µ.

Figure 2: Layout of the DFF in task; Area = 1459.67 um2

Cell area(um2) : 1459.67

Output Rise delay

value at pin Q (ns)

input_net_transition at pin CP (ns)

0.056 0.392 1.728 7.088

tota

l_o

utp

ut_

net

_cap

acit

ance

at p

in Q

(p

F)

0.1 15.125 15.504 16.6848 21.08

0.2 25.2393 25.552 26.7389 31.168

0.4 45.4476 45.8378 46.9496 51.512

0.6 65.7435 65.9685 67.2328 71.553

Output

Rise_transition at

pin Q (ns)


0.056 0.392 1.728 7.088

tota

l_o

utp

ut_

net

_cap

acit

ance

at p

in Q

(p

F)

0.1 10.1252 10.121 10.1439 10.12

0.2 19.171 19.1742 19.1816 19.173

0.4 37.187 37.2801 37.2823 37.215

0.6 55.4287 55.2433 55.3313 55.266

Figure 3: timing table

Page 3 of 13

The following schematic is the simulation circuit:

Figure 4: testbench circuit

The following four schematics are the simulation result under different input net transition time.

Figure 5: simulation result for 0.056ns input net transition time

Page 4 of 13

Figure 6: Simulation result for 0.392ns input net transition time

Figure 7: Simulation result for 1.728ns input net transition time

Page 5 of 13

Figure 8: Simulation result for 1.728ns input net transition time 7.088ns

The LVS output file is like:

Figure 9: LVS output

Page 6 of 13

The trend charts for both rise delay and rise transition is as follows:

Figure 10: output rise delay

Figure 11: output rise transition

Result Analysis

The area of the layout is relatively but the output rise delay and transition time is really large,

which is because we minimize each transistor, resulting in the resistance for each transistor

become larger. So to the same load capacitor, the RC delay is large.

13

23

33

43

53

63

73

0.056 0.392 1.728 7.088

Ou

tpu

t _r

ise

de

lay

(ns)

input_net_transition (ns)

output rise delay

0.1pF

0.2pF

0.4pF

0.6pF

9

13

17

21

25

29

33

37

41

45

49

53

57

0.056 0.392 1.728 7.088

Ou

tpu

t_ri

se_t

ran

siti

on

(n

s)


output rise transition

0.1pF

0.2pF

0.4pF

0.6pF

Page 7 of 13

Task 2

Improve the circuit design in the task 1 with considering both area and timing

Design strategy

In order to improve the timing of the circuit, we firstly size the transistors of all two inputs

NAND gate to Wn = 2Wmin=3µ, Wp=3Wmin=4.5µ and Ln=Lp=0.6µ and the three input NAND gate

to Wn = 3Wmin=4.5µ, Wp=3Wmin=4.5µ and Ln=Lp=0.6µ. By this way, the propagation delay for

rising and falling is equal. In addition, the second stage 2 two-input NAND actually drive the

load capacitor. So in order to decrease the propagation delay of the circuit, one strategy is to

increase the w/L of the transistors in the last stage to decrease the resistor and increase the

drain/source current. By doubling the width of both nmos and pmos in the last stage and keep

the length constant, the propagation delay is halved.

The layout of the circuit is as follows:

Figure 12: Layout of improved DFF circuit

Area = 2208.02 um2

Page 8 of 13


Output Rise delay

value at pin Q (ns)


0.056 0.392 1.728 7.088

tota

l_o

utp

ut_

net

_cap

acit

ance

at p

in Q

(p

F)

0.1 4.4773 4.7456 5.67 9.103

0.2 5.4673 5.7366 6.6569 10.102

0.4 7.3891 7.6598 8.5862 12.024

0.6 9.3089 9.5775 10.506 13.941

Output

Rise_transition at

pin Q (ns)


0.056 0.392 1.728 7.088

tota

l_o

utp

ut_

net

_cap

acit

ance

at p

in Q

(p

F)

0.1 1.468 1.4731 1.4694 1.496

0.2 2.303 2.3037 2.2996 2.311

0.4 4.0153 4.0148 4.0133 4.017

0.6 5.7431 5.7406 5.7407 5.741

Figure 13: Table of delay for different CP and load

The following table is the value of Cell_area*Cell_rise_delay


Output Rise delay * Cell

Area (ns * um2)


0.056 0.392 1.728 7.088

tota

l_o

utp

ut_

net

_cap

acit

ance

at p

in Q

(p

F)

0.1 9885.31 10478.4 12519.5 20099.6

0.2 12071.9 12666.5 14698.6 22305.4

0.4 16315.3 16913 18958.5 26549.2

0.6 20554.2 21147.3 23197.5 30782

Page 9 of 13

Output Rise_transition

* cell Area (ns* um2)


0.056 0.392 1.728 7.088

tota

l_o

utp

ut_

net

_cap

acit

ance

at p

in Q

(p

F)

0.1 3241.37 3252.63 3244.46 3303.2

0.2 5085.07 5086.62 5077.56 5102.73

0.4 8865.86 8864.76 8861.45 8869.62

0.6 12680.9 12675.4 12675.6 12676.2

Figure 14: table of Cell_area*Cell_rise_delay

The following four schematics are the simulation result under different input net transition time.


Page 10 of 13


Figure 17: simulation result for 1.728 ns input net transition time

Page 11 of 13

Figure 17: simulation result for 7.088 ns input net transition time

The LVS output file is like:

Figure 18

Page 12 of 13

The trend charts for both rise delay and rise transition is as follows:

Figure 19: output rise delay

Figure 20: output rise transition

Analysis

By improving the circuit, the output rise delay at pin Q decreases by 80% of original one and the

output rise transition delay at pin Q decreases by 90% of original one, while the layout area

only increases 748 µm2. It seems to be a really good trade-off. We use only a small increase in

are to trade a significant improve in the speed of the circuit.

3

5

7

9

11

13

15

0.056 0.392 1.728 7.088

Ou

tpu

t_ri

se_d

ela

y (n

s)

input_net-transition (ns)

output rise delay

0.1pF

0.2pF

0.4pF

0.6pF

1

2

3

4

5

6

0.056 0.392 1.728 7.088

Ou

tpu

t_ri

se_t

ran

siti

on

(n

s)


output rise transition

0.1pF

0.2pF

0.4pF

0.6pF

Page 13 of 13

Conclusion The DFF is an important standard Cell in the digital circuit design. In this lab, we do the

improvement on the circuit designed in the lab2 by considering increasing the speed of the

circuit. Using a small increase in the layout area to trade off a significant increase in the circuit

speed is a really good deal. In addition, when doing the simulation part of this lab, we need to

include the parasitic capacitance of the mos transistor even though it has not a significant

influence on the simulation result.

Documents

Chongli Cai Ailing Mei 9/11/2012