CBP 2009 Comp 3014 The Nature of Computing

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Choices in Designing an ISA

• Uniformity. Should each instruction– Be the same length (in bits or bytes?)– Take the same time to execute?

• Complexity. – How many different instructions?– How closely linked to High Level languages?

• Tradeoffs – Complex Instructions– Take up less code memory to store them– Need a rather complex CPU design

CBP 2009 Comp 3014 The Nature of Computing

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Instruction Encoding Example

add rd rs rt unused

rd <- rs + rt

e.g. add r3, r1, r2 means r3 = r1 + r2

010110 00011 00010 00001 unused

All Sam’s instructions take up 32 bits.

Sam’s instructions start with the opcode then the destination reg- ister then the source register

opcode

destination

Source regs

First 6 bits for the opcode.

3 2 1

CBP 2009 Comp 3014 The Nature of Computing

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Intel 80x86 ISA The most popular of

all• 1971: Intel invents microprocessor 4004/8008, 8080, 8085 • 1975: Major design effort for new 16-bit ISA, (iAPX432) but …• 1978: 8086 dedicated registers, segmented address, 16-bit

• 8088; 8-bit version of 8086 added as after thought• 1980: IBM selects 8088 as basis for IBM PC • 1980: Intel 432 finally ready but…• 1980: 8087 floating point coprocessor: • 1982: 80286 24-bit address, protection, memory mapping• 1985: 80386 32-bit address, 32-bit GP registers, paging• 1989: 80486• 1992 Pentium• 1995 Pentium Pro• 1997 Pentium Pro with MMX multimedia acceleration

CBP 2009 Comp 3014 The Nature of Computing

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Some x86 instructions

mov ax , [bx + c]

mov [ax] , bx

add ax , bx

add [bx] , ax

These look rather like Sam’s RISC ops

But this is not. Here the contents of ax is being added straight into memory ! The x86 is a register – memory ISA and Sam is a register – register ISA

ldi r1 , aldi r2 , badd r3,r1,r2 st r3 , b

mov ax, aadd b,ax

Let’s compare the RR and RM ISA’s. Clearly RR needs more memory

while the RM uses stronger operations

Sam

Intel x86

CBP 2009 Comp 3014 The Nature of Computing

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Variable Length Instructions

0% 10% 20% 30%

1

2

3

4

5

6

7

8

9

10

Expresso

Gcc

Spice

Nasa

All Sam’s instructions had the same length, 32 bits. This is also true for other RISC ISA’s such as SPARC

and MIPS. Compare this with the x86 instruction vary from 1 to 17 bytes. Here’s some stats.

Instr

ucti

on

Len

gth

(b

yte

s)

Frequency of use

Clearly long complex

instructions are used infrequently

But the use does depend on the

app.

CBP 2009 Comp 3014 The Nature of Computing

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Variable Time InstructionsHere’s a timing diagram for an Intel

add

T1 T2 T3 T4 T5

Fetch Decode, Reg Op

ALU Mem Access

Reg Write

T1 T2 T3 T4 T5

Fetch Decode, Reg Op

ALU Mem Access

Reg Write

add ax , [bx + c]

[bx + c] ax = ax + mem[..]

We need two adds. The first to get the address summed up …

… and the second to actually add memory to register ax

CBP 2009 Comp 3014 The Nature of Computing

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strcmp(str, Greenspan);

Potent x86 Instructions

mov x,2 Immediate to memory 6

xlat x Translate al via table 1

imul x Multiply memory with ax

4

inc x Increment memory by 1

4

Repne scasb Scan string for match ! various

Greenspan

1.Application

2.High-Level Language

(‘C’)

3.Intel ISA code

CBP 2009 Comp 3014 The Nature of Computing

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Top 10 Intel x86 InstructionsTop 10 Intel x86 Instructions

Rank Instruction Usage

1 load 22% 2 conditional branch 20% 3 arithmetic / logic 19% 4 compare 16% 5 store 12 % 6 move reg - reg

4% 7call - return2%

We see that most instructions are Simple load, store, calculate, branch. None of Intel’s potent stuff figures here. So why did Intel design instructions no-

one uses ?

CBP 2009 Comp 3014 The Nature of Computing

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Semantic Gap Twixt HLL and MLIn the 1970’s Hardware costs decreased.

So we got faster CPUs but Memory was expensive.

– Bigger programs means more expensive programs

–Shortage of Good Programmers– Unreliable Software

– Response : Reduce programming Costs– Develop powerful HLL easy to learn so no mistakes–But is Semantic Gap between HLL and ML– Software runs inefficiently - Poor Performance– Compilers become Complex

– So Close the Semantic Gap– Machine executes HLL constructs in hardware– Lots of addressing Modes

Add the column of sales figures

ld r1,B ld r2,0 ld r3,[r1 + r2] add r4,r4,r3 addi r2,r2,1 str r4,[r2+5] …

…

…

add r4,r3,r2

But this potent stuff is not being used !

CBP 2009 Comp 3014 The Nature of Computing

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ISA R&D into the 80’s

1980 Berkeley Patterson RISC

(SPARC)

1981 Stanford Hennessy MIPS

- Easy to Decode Ops - Fast Issue Rate - Only load and Store references memory - Lots of registers

Emerging Design Guidelines

Let’s downshift and make things simpler …

• Use simple instructions, load, store, add

• Many of these will do one x86 potent op

• Need more memory, but memory is becoming cheap

• More CPU cycles, but can still be faster