Chip Design Trend Fabrication Prospects in India 1196826532302711 2

8/8/2019 Chip Design Trend Fabrication Prospects in India 1196826532302711 2

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Chip Design Trend & Fabrication Prospects in India

BY:Bibhuti Bikramaditya

Technical Leader DCA Electronic System DesignPune


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Topics of DiscussionChip design in Brief Chip design application AreasLatest chip design trendFabrication prospectconclusion


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Chip design in brief

H istorical journeyVLSI TechniquesFPGA Vs. ASICsNew FPGA RevolutionEmbedded advantages


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Historical JourneyJ ust after Invention of Transistors in theend of 19 47 and the beginning of 19 48 ,valve era supposed to become obsoleteand the journey of Modern Electronics

began.Miniaturization of ICs started with theidea of putting more no. of Transistorsinto one silicon chipSSI : < 1 2 Gates.MSI:


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IC Era (from SSI To VLSI)

IC in 1960sO nly 2 transistors and one

resistor.

Size of chip was more thanrequired.Unable to deal with complex

functionalities.Excess power dissipation.

Speed was not significant .

IC in 2003s

More than 40 million transistorsand other components and expectedto be of order of Billions of transistors by 2005.

Every part of the chip is utilized.

Efficient in dealing with complex

functionalities.Power dissipation brought in

control.

Million of operations can be done

in just one second.


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IC Design Tec h nique from layout level tosystem level

The introduction of H DLs have made possible thedesign of complete System on Chip(S O C), with thecomplexities rising from 1 million to 10 milliontransistors.Recently System C has been introduced

for 100 million to 1000 millions of transistors.


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IC Design Growth at frequency level

Th e clock frequency increased for h igh performance micro processor and industrial microcontrollers wit h th e tec h nology scale down. h eremotorola micro controler h as been taken as t h eexampleused for h igh performance automotive industryapplications.


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Intel Microprocessor Growt h

Describes the evolution of complexity of intel@ micro processors in terms of no. of devices on the chip the pentium 4 processor produced in 2 003 is 5 0 millionMO S devices integrated on a single pieceof silicon no larger than 2 x 2 c.m.


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Evolution of Memory Size

First 1 kb memory produced by Intel in197 1 , semiconductor memory haveadvanced both in density as well asperformances. With the production of 2 56 Mb memories in 2 000 and 1Gb in 2 00 4

according to the estimates , it willexpected to increase up to 1 6 Gb in 2 00 8 .


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Evolution of Lith ograp h y

Trend towards the smaller dimension hasbeen accelerated since 199 6 . in 2 00 7 ,the lithography is expected to decreasedown to 0.0 7 um .


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Evolution of silicon area for NAND GateFig shows how fabrication for Simple

NAND gate become complex as itsfeature size is decreasing almostexponentially .


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Typical Structure ICs


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Moors Law Vs.IC Tech nology Growth F irst Law: Silicon Technology will double the

number of transistors per chip every 18 months !!!all above example shows its validity.

In other way ,its minimum feature size mustdecrease by a factor of 0.7 every three years


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VLSI Tech niquesStands for Very Large Scale Integration.This is the technology of Putting millionsof transistors into one silicon chip.Tools (for VLSI)(1) Model sim 5.5b : Simulation

Simulation is used for the testing thebehavior of outputs on the waveformaccording to their input given.

(2 ) Leo nar do Sp ect rum 3 : SynthesisSynthesis tool is used for looking the

hardware according to the programwritten in their languages likeVH DL/VERILO G.

(3 ) Xilinx 6.1 ISE Pa ck : ChipDownloading


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VLSI Tech niques

Evolution O f Programmable Devices

(1) PR O M: Programmable R O M(2 ) PAL: Programmable Array Logic(3 ) PLA: Programmable logic Array.(4 ) CPLD: Complex Programmable

Logic Devices.(5 ) FPGA: Field Programmable Gate

Arrays.(6 ) ASIC : Application Specific ICs.


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P LD Trend


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Xilinx FP GA Arch itecture


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C P LD Vs. FP GA

A rchitecture PLA like Gate array like

Density Low to medium Medium to high

Speed Fast, predictable Application dependent

Interconnect Crossbar Routing

Power consumption High Medium


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ASIC Vs. FP GA


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New FP GA Revolution

All Dis advantages of AS ICs

(1) Longer time to market

(2) Complex Design methodology

have been overcome by FPGA

In terms of No. of Transistors per chip ,FPGA Vendors have increased its

capacity and astounding result is comingas time pass through.

Inclination Towards FPGA is increasing day by day.


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New FP GA Revolution


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New FP GA Revolution: SP ARTAN 3Recently Introduced


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New FP GAP rice Revolution

Price of 100k gates over time


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Cost Management t h rough SystemIntegration


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Embedded Advantage

Complete System Design PossibleReal time application.Low cost ChipVLSI Goes on embedded as wecan write program in Linux and

Unix Environment.System C developed by Xilinx.


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Ch ip Design Application AreasNetworking (PCI,Ethernet,USB)DSP & CommunicationSpeech Processing &Image

processingTele mobile communication.Micro processor & Micro controller Based System.H ome appliances


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DSP VLSI &CommunicationTrend is now to implement all DSP Function and algorithm into VLSI so as it

could make complete chip being largely used for H igh speed Multimediaapplication, tele-mobile communication and GPS System

DSP Performance and Flexibility: FPGASolution


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Conventional DSP Software VS.FP GAP erformance advantage


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Image P rocessing


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Image P rocessing : M P EG-4

The Brilliant Engineers of DCAElectronic System Design is alsoworking on complete ImplementationO f MPEG- 4 using VLSI andEmbedded Technology


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Latest Ch ip DesignTrend

Auto motive Sector Biometric analysis for SecurityNeural network & Artificialintelligence.System O n Chip Design withVirtual Component.Bio Chips: Rule Based System

Neuro Chips.


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Auto motive Electronics Market Overview


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Auto motive Applications


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FP GA Solution for Car Manufacturers


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CARCUB E : Telematics P latforms fromAcuna & Xilinx


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CARCUB E : Arch itectural Description


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Auto motive Sector : Issues and Ch allenges


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Auto motive Sector : In Veh icle Networking

LAN: Local Area Network,

CAN: Control Area Network


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Auto motive Sector : MOST Application


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Auto motive networks


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Car Multimedia System


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Security System: Encryption & DecryptionAES Algorith m Implementation


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Security System: Encryption & DecryptionAES Algorith m Implementation

h h


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System On Ch ip Design : with VirtualComponent

System On Chip may contain both a system bus connect and Peripheral bus connectcustom I/ O block that provide functions notcommercially available,may also be included

In the recycling age, designing for reusesounds like a great ideabut with increasing requirements and chipsizes,its no easy task.

Ch h l


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System On Ch ip Design : with VirtualComponent

Adv. Of System On Chip:(1) Increased levels of design reuse.(2 ) More effective hardware-software co-design.(3 ) Better trade-offs between general-purpose vs. domain-specific

architectures and algorithms.(4 ) Greater integration of functionality on-chip (hardware-software,

analog-digital).


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B io Ch ips : A medical Revolutiondeveloped to sequence unknown genes and to study gene expression. but

the working principle suggest that they can be used for engineeringapplication that require parallel processing.DNA chips are proposed here as the physical substrate to store andevaluate a set of rules for knowledge based systems.

In DNA chips, each cell uses millions of copies of DNA sequencecalled probes. The colors indicate that probes are different between

cells


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B io Ch ips : Design Steps

Fig(1) Single stranded DNA sequencesFig2 Nucleotide with pyrimidinebase and Purine base

Simplified Diagram for Fig3


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B io Ch ips : Design Steps

Fig4 :DNA sequence tagged with the

quantum dots. H ere half circle representSingle stranded DNA Sequence andSmall dot is the quantum dot

Fig5 :Complementary probes and target bind tofluorescent DNA helix. In practice , there aremillions of probes per cells ,so millions of targets

are required to produce Fluorescent cell after hybridization

Fig6 : plant states are sampled and A/DNA Converter produce millions of two tagged DNA sequences. Smalldot is quantum dot used to identify helix

Fig7 :DNA chip is injected with millions of tagged DNAstrands. After Scanning the chip and processing therules o/p is produced

Fig8 : DNA chip can be used to detect faults in theplant. State variables are sampled ,converted into DNA

target and injected into chip. The green cells arefluorescent probes after being excited with UV light


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Look up tables as DNA Ch ips: Rule Based SystemBasically , look up table is derived from the pastexperience and it can be used to improve the

performance of the closed loop with an existingcontroller (fig 9) .The rules are stored on the chip and theevaluation of the complete rule base at each

sampling instant is carried out in parallel usingthe hybridization of DNA strands.

Applications:

(1) To store boolean or fuzzy rules

(2 ) Rule Based System

(3 ) Plant Behavior

fig9


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Time Delay Neural Network :P h oneme Recognition(Speec h Recognition )

Fig1: component of Speech Recognition SystemFig2 :Neuron Unit Schematic Diagram

Fig3 : Error Signal Generator Schematic Diagram Fig4 :Synapse Unit Schematic Diagram Used for storageand updates of weight

Conclusion: Using Small dimension CM O S processes, such as 0. 3 5 um ,a 5 mm by5 mm chip could include up to 1 5 0 neurons, 1 5 0 synapses and 1 5 0 error signalgenerator unit to construct full time delay neural network for phoneme recognition,

using just a Single Chip . This chip could then be interfaced with computer togenerate fully generated phoneme recognition system


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Neuro Ch ip : Design Dreams

Recently revolutionary Invention of Neuro Chip wondered the world : if itmixed with our nervous system ,it willcontrol Brains nervous system and

then according to the program one cancontrol on his thinking ability also.Are you not thinking that designingdream is also not impossible ?

See my article in The Times Of India Education Times datedsept,30,03 on VLS I DSP &Embedded Systems : EmergingCareers


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FABRICATIONP ROSP ECT

1. Chip Design Productivity

2. Chip Design Forecast

3. World Fab Industry Vs. Indian FabIndustry

4. Why Fab lab doesnt exist in India?

5. Challenges before Chip Design &Fab lab


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Ch ip Design P roductivity

Fig1: Actual No. of Transistors in millions per ICdesign. This data illustrates that there is littlecorrelation between transistors count and

engineering effort

Fig2

: Normalized Transistors count Vs.Persons week

Fig 3 : Factors Influencing IC Design Effort

Design Productivity = output produced /labour expended= output per unit worker hour

Manufacturing productivity = value added/labour expended= value added per unit worker hour.= (end product selling price- material cost of the

product) worker hour = dollars per worker hour

Chip design productivity transistor /gate per unit engineering effort.Chip design productivity = chip design complexity/ engineering effort.

= complexity per unit engineering hour.


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Ch ip Design Fore cast1.According to a Gartner forecast: 3 per cent

growth in global semiconductor revenue,2 003 "after its worst fall ever in 2 001."

(2 ) India's chip design industry :revenues of Rs 1, 5 00 crore ($ 3 00 million),

(3 ) Indian Market Share : not up to the markbut in three-four years ,it will reach onstandard mark. According to a Monster India.com report, "The integrated circuit (chipdesign industry is pegged to grow into a multimillion dollar industry in India, thanks to theUS slowdown."(4 ) Indian Design Industry: performing welland going global. large semiconductor

vendors are growing their operations in India.


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World Fabrication Industry Vs. Indian FabricationIndustry 5 . Fab Industry:

(a) Around 5 0 Fab lab Exist in the world,another 5 0 in near future

(b) First fab lab by Intel J ust open in Taiwan ,first in South Asia.(c) No Complete VLSI Fab Industry In India,

(d) SCL ,Chandigarh has its own LSI Fab lab.

(e) Proposal : Rs.1 5 00 crore (for Indian Govt)

(f) Recently Two Companies joined forces in Fab Industry like

IBM/siemens for 6 4 Mb Technology and

IBM, Siemens &Toshiba for 2 56 Mb Technology.

6 .H uge Investment Required for Design and Fab Lab:

According to Mr Girish of Texas Instruments, "It's not feasible for man

small Indian companies to make sustained investments for a longperiod of time, which is required for product development (including th

area of chips design/manufacture). I don't think we can do that now.

Also, to get into full-scale manufacturing, the government should also

take some efforts. It has to take a decision to shift manufacturing uni

to smaller towns instead of concentrating on the metros."


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Fab lab does not exist : w h y?

1. Huge Fabrication lab cost According to Mr Girish of Texas Instruments, "It's not feasible for many small

Indian companies to make sustained investments for a long period of time,which is required for product development (including the area of chipsdesign/manufacture). I don't think we can do that now. Also, to get into full-scale manufacturing, the government should also take some efforts. It hasto take a decision to shift manufacturing units to smaller towns instead of

concentrating on the metros .

(2)Design Incompetency, Probably India is not prepared .

The actual problem is that quality talent with the right skills is becoming

scarce. The skills required are in vertical domains (DSP, telecom etc.)along with in-depth understanding of chip design challenges like designingfor high speed, low power, small size, handling large complexities,accounting for deep sub-micron effects like signal integrity. This isassuming that these engineers come with basic microelectronics skills

including an understanding of semiconductors and design basics likelanguage-based design methodologies. Exposure to contemporary design

tools is also important."

h h


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Ch allenges before Ch ip Design andFab Industry

1. System Level Integration: According to Mr. S.Surinder Lall , Sr Marketic Manager , Xilinx Inc.(St.Pitsberg) during my words with him :There is still requirement of System Engineers who can understand the complete system. The trendtowards coding is to write code in C/C++, Matlab/ J ava and then convertedinto VH DL/VERILO G, is not suitable. Chip Design has a long walk totravel.

2. Chip Design Limits : There is Physical Limits to the ChipDesign , reported by New york Times by at Paul Packan, a scientist withIntel Corp., the world's largest chipmaker, said semiconductor engineershave not found ways around basic physical limits beyond the generationof silicon chips that will begin to appear next year. Packan called theapparent impasse "the most difficult challenge the semiconductor industryhas ever faced."

"These fundamental issues have not previously limited the scaling of

transistors," Packan wrote in the Sept. 24 issue of Science. "There arecurrently no known solutions to these problems."

According to Dennis Allison, a Silicon Valley physicist and computer designer

If the miniaturization process for silicon-based transistors is halted, hopes for continued progress would have to be based on new materials, newtransistor designs and advances like molecular computing, the Times

reported . This Mystry will be solved ultimately .


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Conclusion:

Despite all these stiff challenges ,Chip Design Industry is growing notwittingly fast and are affecting evencommon mass to go nuclear as wellas global . Indian FabricationIndustry is the biggest challengeand dream also .

Let us see when this dream comestrue.


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Chip Design Trend Fabrication Prospects in India 1196826532302711 2