Chess - Compilationof ParametricDataflowApplicationsfor Software-Defined-Radio ... · 2018. 4. 3. · Compilationof ParametricDataflowApplicationsfor Software-Defined-Radio-DedicatedMPSoCs

Compilation ofParametric Dataflow Applications for

Software-Defined-Radio-Dedicated MPSoCsDREAM seminar

Mickaël Dardaillon

Research Intern with NOKIA Technologies

January 27th, 2015

Context Programming Model for SDR Micro-Scheduling Experimentations on Magali Perspectives

Evolution of telecommunication protocols

13/01/20153

What we know about 5G What we know about 5G What we know about 5G What we know about 5G demandsdemandsdemandsdemandsHigher capacity, lowest latency and more consistent experience

Flexibility for what is unknown today

Real-time control

Multimedia

Monitoring & sensing

NextGen media

2G

1G

Text

Mail

Voice

3G

4G

Push & pull of technology

M2M

?

Tactile

MTC

1ms

10ms

100msAudio

Visual

Tactile

2 / 33


4G LTE-Advanced: Downlink

0 1 2 3 4 5 6 7 8 91 sub-frame (1 ms)

1 frame (10 ms)

I MIMO: 4× 2 antennasI LTE throughput: 1.4 GbpsI LTE-Advanced: 7 GbpsI Latency: 2 msI Power budget: 500 mW

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4G LTE-Advanced: Downlink

0 1 2 3 4 5 6 7 8 91 sub-frame (1 ms)

1 frame (10 ms)

Control

User 1

User 2

User 3

Data

...

14 OFDM Symbols

2048 subcarriers (20 MHz)

I MIMO: 4× 2 antennasI LTE throughput: 1.4 GbpsI LTE-Advanced: 7 GbpsI Latency: 2 msI Power budget: 500 mW

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Magali SDR

LTE demonstrator[Clermidy et al., 09]Power consumption: 231mW

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Magali SDR

DSPdsp2

DSPdsp3

DSPdsp5

DSPdsp4

DSPdsp1


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Magali SDR

OFDMofdm1

OFDMofdm2

OFDMofdm3

OFDMofdm4

TURBOturbo

DEMODdemod

MODmod

LDPCldpc

WIFLEXwiflex

DSPdsp2

DSPdsp3

DSPdsp5

DSPdsp4

DSPdsp1


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Magali SDR

OFDMofdm1

OFDMofdm2

OFDMofdm3

OFDMofdm4

TURBOturbo

DEMODdemod

MODmod

LDPCldpc

WIFLEXwiflex

DMAdma2

DMAdma3

DMAdma1

DMAdma4

DMAdma5

DSPdsp2

DSPdsp3

DSPdsp5

DSPdsp4

DSPdsp1


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Magali SDR

OFDMofdm1

OFDMofdm2

OFDMofdm3

OFDMofdm4

TURBOturbo

DEMODdemod

MODmod

LDPCldpc

WIFLEXwiflex

ARMarm

80518051

DMAdma2

DMAdma3

DMAdma1

DMAdma4

DMAdma5

DSPdsp2

DSPdsp3

DSPdsp5

DSPdsp4

DSPdsp1


4 / 33


Problem statement

– How should we program aCell processor?

– Any way you want!

How to program and compile a telecommunicationprotocol to an heterogeneous MPSoC?

5 / 33


Problem statement

– How should we program aCell processor?– Any way you want!

How to program and compile a telecommunicationprotocol to an heterogeneous MPSoC?

5 / 33


Outline

Context

Programming Model for SDRDataflow Model of Computation

Dataflow Refinement and Buffer VerificationMapping and SchedulingMicro-Scheduling

Experimentations on MagaliCode GenerationExperimental Results

Perspectives

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State of the Art in SDR ProgrammingImperative Concurrent

Platform LanguageExoCHI [Wang et al., 07] OpenMP + CBEAR [Derudder et al., 09] Matlab + C

Dataflow

Platform LanguageSimulinkLabViewGNU Radio Python + CRVC-CAL [Lucarz et al., 08] XML + CDiplodocusDF [Gonzalez-Pina et al., 12] UMLMAPS [Castrillon et al., 13] C like

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Static Dataflow (SDF) [Lee et al., 87]

Decod1Src110 Ctrl10

1 1

8 / 33


Phase Approach with Static Dataflow

...

Decod2 Sink1 10100 10Src2



Decod1Src110 Ctrl10

1 1

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Dynamic Dataflow (DDF) [Buck, 93]

SDF DDF

Analysable Expressive

KPN

Scenario Aware DataFlow (SADF) [Theelen et al., 06]Mode Controlled DataFlow (MCDF) [Moreira et al., 12]Schedulable Parametric DataFlow (SPDF) [Fradet et al., 12]Parameterized and Interfaced dataflow Meta-Model (PiMM)[Desnos et al., 13]Boolean Parametric DataFlow (BPDF) [Bebelis et al., 13]

Kahn Process Network (KPN) [Kahn, 74]

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Dynamic Dataflow (DDF) [Buck, 93]

SDF DDF

Analysable Expressive

KPNMCDFSPDF BPDFSADFPiMM

Scenario Aware DataFlow (SADF) [Theelen et al., 06]Mode Controlled DataFlow (MCDF) [Moreira et al., 12]Schedulable Parametric DataFlow (SPDF) [Fradet et al., 12]Parameterized and Interfaced dataflow Meta-Model (PiMM)[Desnos et al., 13]Boolean Parametric DataFlow (BPDF) [Bebelis et al., 13]Kahn Process Network (KPN) [Kahn, 74]

10 / 33


Schedulable Parametric DataFlow (SPDF)

Decod1

Src10

10 1 1 Ctrl

[Fradet et al., 12]I Model of ComputationI AnalysisI Quasi-Static Scheduling

11 / 33


Schedulable Parametric DataFlow (SPDF)

Decod1

Src10

10 1 1 Ctrlset p[1]

Sinkp 10

10010

p

Decod2

[Fradet et al., 12]I Model of ComputationI AnalysisI Quasi-Static Scheduling

...

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Front End ImplementationFront End

PaDaF(C++)

C++ Front End(CLang)

LLVM IR

GraphConstruction

Graph +LLVM IR

SDR Programming ModelI Propose SPDF for SDRI C++ input format

Front EndI Based on LLVM frameworkI Derived from SystemC analysis

[Marquet et al., 10]I Static graph structure

12 / 33


Outline

Context




Perspectives

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SPDF Mapping

demod dma2

dma1

arm

Decod1

Decod2

Src10

Ctrlset p[1]

Sink

10 1

p

1

10100

10

p

DEMODdemod

ARMarm

DMAdma2

DMAdma1

14 / 33


SPDF Quasi-Static Scheduling [Fradet et al., 12]

Decod1

Decod2

Src10

Ctrlset p[1]

Sink

10 1

p

1

10100

10

p

demod dma2

dma1

arm

S(dma1) = (Src)S(arm) = (Ctrl; set(p))

S(demod) =(Decod1;get(p); (Decod2)10

)S(dma2) = (get(p); (Sink)p)

15 / 33


SPDF Symbolic Execution

Time

arm

demod

dma2

dma1

D1 (D2)10

Src

Ctrl

(Sink)p

S(dma1) = (Src)S(arm) = (Ctrl; set(p))

S(demod) =(Decod1;get(p); (Decod2)10

)S(dma2) = (get(p); (Sink)p)

16 / 33


SPDF Buffer Sizing

Decod1

Decod2

Src10

Ctrlset p[1]

Sink

10 1

p

1

10100

10

p

demod dma2

dma1

arm

[100]

[10][1]

[10*pmax]

Problem: overestimates buffer size

e.g. MagaliI FFT size: 2048I Buffer size: 16

17 / 33


SPDF Model Refinement

Decod1

Decod2

Src10

Ctrlset p[1]

Sink

10 1

p

1

10100

10

p

demod dma2

dma1

arm

[10]

[10][1]

[pmax]

Src::compute() {[...]out[1].push(ctrl, 10);for(int i=0; i


Micro-Scheduling: an Example

Time

arm

demod

dma2

dma1

D1 (D2)10

Src

Ctrl

(Sink)p

µS(Src) =(pushSrc,D1(10);pushSrc,D2(10)

10)

µS(D2) =(popSrc,D2(10);pushD2,Sink(p)

)µS(Sink) =

(popD2,Sink(1)

10)

19 / 33


Buffer Sizing Verification

How to verify buffer sizes using micro-schedules?

Proposed Verification MethodI Based on Model CheckingI Derived from buffer minimization [Geilen et al., 05]

ModelI ScheduleI Buffer sizes+ Micro-Schedule+ Parameter values

Model CheckerI SPINI Check for deadlocks

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Micro-Scheduling Implementation

Mapping

Scheduling

Front End Back End

PaDaF(C++)


LLVM IR

ConstructionGraph

Graph +LLVM IR

Buffer Verification(SPIN)

Micro-SchedulingI SPDF model

refinementI Sequential

communications

Buffer VerificationI Model checking

21 / 33


Outline

Context




Perspectives

22 / 33


Code GenerationGraph +LLVM IR

OFDM

OFDMofdm1

DMAdma2

DMAdma3

DMAdma1

DMAdma4

DMAdma5

DSPdsp2

DSPdsp3

DSPdsp5

DSPdsp4

OFDMofdm2

OFDMofdm3

OFDMofdm4

ARMarm

80518051

LDPCldpc

WIFLEXwiflex

TURBOturbo

DSPdsp1

MODmod

DEMODdemod

DEMOD code generationcontrol

code generationcommunication

(C)Control code

(ASM)Magali code

code generationARM

TURBODSP

DMA

code generationARM

23 / 33


Benchmarks using LTE

OFDM: compilation

Sink4200600

ofdm1 dma3

FFTSrc 7168

dma1

Defram1024 1024 1024

Demodulation: communications

dma2

Src

Src DeinterBit Depunct Decod

Turbo

Demap DeinterWord Sink

1200

1200 12001200

900 900 900

900900 300 1353 1353

57

57

dma1 demod

dma3

turbo

dma4

24 / 33


Benchmarks using LTE

Parametric Demodulation: parameter

dma2


Turbo

Split Demap DeinterWord

set p[1]Control


Turbo

Split Demap DeinterWord Sink

1440

1440240 240

240

240

60 60 60

60 60 30 93 93 4

8

pp

1440

1440

1200

1200

12001200

300p 300p 300p

300p300p 300 1353 1353

57

57

dma1 demod

dma3

turbo

dma4

arm

25 / 33


Results: Estimated Development Time

Compiler DevelopmentI Front-End : 4 man-monthsI Back-End : 8 man-months

Native PaDaFApplication C / ASM (#lines) (hours) C++ (#lines) (hours)OFDM 150 / 200 40 60 1Demodulation 300 / 600 160 160 4Param. Demod. 500 / 800 480 260 8

Takeaway Message:Reduces development time

26 / 33


Results: Buffer Verification Time

Evaluation frameworkI 2.4 GHz Intel Core i5, 8 GB RAM, OS X 10.9.2.I SPIN Model Checker

Application States Transitions Exec. Time (s)

OFDM 1.28× 104 2.56× 104 0.1Demodulation 2.12× 106 1.07× 107 9Param. Demod. 6.07× 107 2.22× 108 199

Takeaway Message:Reduces development time, improves verification

27 / 33


Results: Execution Time

Evaluation frameworkI SystemC TLM based on 65 nm CMOS implementationI ARM code run on QEMU Virtual Machine

Application Native Generated

Optimized

(µs) (µs)

(µs)

OFDM 149 168 (+13%)

149 (+0%)

Demodulation 180 283 (+57%)

180 (+0%)

Param. Demod. 419 558 (+33%)

288 (-31%)

Takeaway Message:Reduces development time, improves verification

, maintainsperformances

28 / 33


Execution ModelSink4200600

ofdm1 dma3

FFTSrc 7168

dma1

Defram1024 1024 1024

Phase Approach

Time

dma1

ofdm1

dma3

arm

Distributed

Time

dma1

ofdm1

dma3

arm

29 / 33


Execution ModelPhase Approach

Time

dma1

ofdm1

dma3

arm

25 µs 37 µs 16 µs 21 µs

Distributed

Time

dma1

ofdm1

dma3

arm

25 µs74 µs 25 µs23 µs

29 / 33


Results: Execution Time

Evaluation frameworkI SystemC TLM based on 65 nm CMOS implementationI ARM code run on QEMU Virtual Machine

Application Native Generated Optimized(µs) (µs) (µs)

OFDM 149 168 (+13%) 149 (+0%)Demodulation 180 283 (+57%) 180 (+0%)Param. Demod. 419 558 (+33%) 288 (-31%)

Takeaway Message:Reduces development time, improves verification, maintainsperformances

30 / 33


Back End Implementation

Mapping

Scheduling

Front End Back End

PaDaF(C++)


LLVM IR

GraphConstruction

Graph +LLVM IR


CodeGeneration

MPSoC Code(ASM)

Magali SupportI ComputationI CommunicationI Control

LTE ExperimentationI Performance close

to nativeI Buffer verificationI Central controller

31 / 33


Outline

Context




Perspectives

32 / 33


PerspectivesOn dataflow programmingI CompilerI Runtime Mapping

Scheduling

Front End Back End

PaDaF(C++)


LLVM IR

GraphConstruction

Graph +LLVM IR


CodeGeneration

MPSoC Code(ASM)

On heterogeneous MPSoC

PublicationsI Survey: [Dardaillon et al., IWCMC 12]I Compilation flow: [Dardaillon et al., CASES 14]

I INSA-Lyon, CITI-InriaI Tanguy RissetI Kevin Marquet

I CEA GrenobleI Jérôme MartinI Henri-Pierre Charles

33 / 33


PerspectivesOn dataflow programming

On heterogeneous MPSoCI Future of dedicated platformsI Development on such platforms

13/01/20153

What we know about 5G What we know about 5G What we know about 5G What we know about 5G demandsdemandsdemandsdemandsHigher capacity, lowest latency and more consistent experience

Flexibility for what is unknown today

Real-time control

Multimedia

Monitoring & sensing

NextGen media

2G

1G

Text

Mail

Voice

3G

4G

Push & pull of technology

M2M

?

Tactile

MTC

1ms

10ms

100msAudio

Visual

Tactile




33 / 33


PerspectivesOn dataflow programming

On heterogeneous MPSoC




33 / 33

ContextProgramming Model for SDRDataflow Model of Computation



Perspectives

Documents

Chess - Compilationof ParametricDataflowApplicationsfor Software-Defined-Radio ... · 2018. 4. 3. · Compilationof ParametricDataflowApplicationsfor Software-Defined-Radio-DedicatedMPSoCs