Charging Precision Analysis of a 40-kW 3-kV Soft-Switching

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Charging Precision Analysis of a 40-kW 3-kV Soft-Switching Boost Converter for Ultraprecise Capacitor Charging

Dominic Gerber and Jürgen Biela, Member, IEEE,

mailto:[email protected]

1274 IEEE TRANSACTIONS ON PLASMA SCIENCE, VOL. 42, NO. 5, MAY 2014

Charging Precision Analysis of a 40 -kW 3 -kVSoft-Switching Boost Converter for

Ultraprecise Capacitor ChargingDominic Gerber and Juergen Biela, Member, IEEE

Abstract— In this paper, the charging precision of a 40 -kW3 -kV soft-switching boost converter for capacitor charging isinvestigated. At the beginning, an overview on the topologyand the control of the converter is given. Then, two differentfeedback controllers are presented and compared analytically todetermine their sensitivity on noisy input variables. An algorithmto investigate the charging precision is illustrated. This algorithmconsiders the signal-to-noise ratio (SNR) of all measured signals,the controller output limitations, quantization related errors, thefinite resolution in the digital domain, and the switching signaljitter to calculate the charging precision. All effects mentionedbefore are analyzed separately. This analysis shows that theoutput voltage measurement SNR is the key parameter for thecharging precision. Then, measurements are performed to verifythe model used to calculate the precision. These measurementsshow that the measured precision is only 6% higher than theprecision predicted by the model for the used setup. Finally,the charging precision of the presented converter is analyzedincluding all considered effects. The repetition accuracy of theconverter is determined to be 8.3 ppm at an output voltageof 3 kV, neglecting the load connection and the input voltagevariation during one switching cycle.

Index Terms— Boost converter, capacitor charging, precisionanalysis, soft switching.

I. INTRODUCTION

ACOMPACT and cost-effective X-ray free electron laserfacility is built at the Paul Scherrer Institute in

Switzerland [1]. This laser system requires modulators withthe specifications shown in Table I. There, especially the highoutput voltage repetition accuracy of 10 ppm is challenging.The considered modulator including the capacitor chargingunit is connected to the grid via an isolated power factorcorrection ac/dc inverter, as shown in Fig. 1.

To reduce the input current ripple, two interleaved boostconverters are used to charge the main capacitor bank.

To achieve the targeted pulse repetition accuracy of10 ppm, the capacitor bank has to be charged even moreprecise between two consecutive pulses. In [2], the basicconcept of the capacitor charger and the control strategyhave been presented. The converter shown in Fig. 2

Manuscript received August 29, 2013; revised January 31, 2014; acceptedFebruary 11, 2014. Date of publication March 11, 2014; date of current versionMay 6, 2014.

The authors are with the Laboratory for High Power Electronic Systems,ETH Zurich, Zurich 8092, Switzerland (e-mail: [email protected];[email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPS.2014.2308318

TABLE I

SPECIFICATIONS FOR THE CONSIDERED CONVERTER AND MODULATOR

Fig. 1. Schematic diagram of the modulator system with two interleavedboost converters.

Fig. 2. (a) Picture of the prototype and (b) measured inductor current (cyan)and switch voltage (red) with an ohmic load at an output voltage (yellow) of3 kV and an output power of 3 kW.

is a metal-oxide–semiconductor field-effect transistor(MOSFET)-based 40 -kW boost converter with a nominalinput voltage of 1.3 kV and output voltage of 3 kV.The converter is operated in boundary conduction mode(BCM) enabling zero-voltage switching (ZVS) under certainconditions, which leads to high efficiency. Another advantageof the BCM is that each switching cycle is independentof the preceding cycles. Therefore, only the last switchingcycle determines the output voltage precision. The usageof MOSFETs instead of insulated-gate bipolar transistorsenables a switching frequency of 70 kHz at the nominaloperating point and up to 250 kHz at lower output power.The charge transmitted to the capacitive load during one cycleis lower with a high switching frequency and the system isless sensitive to random errors.

0093-3813 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

GERBER AND BIELA: CHARGING PRECISION ANALYSIS OF A 40 -kW 3 -kV SOFT-SWITCHING BOOST CONVERTER 1275

In this paper, the precision of the boost converter isinvestigated. Since absolute accuracy is not required, it isnot necessary to investigate system-related constant errors, forexample, component tolerances or sensor gain errors. Onlyrandom errors, such as noise, jitter and quantization-relatederrors, have to be considered.

To investigate the repetition accuracy, the complete chainfrom the measurements, the quantization, the digital controller,and digital-to-analog (D/A) conversion, to jitter in the switch-ing signal is analyzed in this paper.

The operating principle of the converter is presented inSection II. Then, the feedback controller is explained andan overview of the control hardware is given. In Section III,different factors influencing the output voltage precision areinvestigated. It includes an analytical analysis of the controllersensitivity on the input and output voltage measurement aswell as a numerical simulation of the converter and thecontrol hardware. The simulation includes the quantizationnoise, the noise of the sensors, the analog-to-digital converter(ADC) resolution, the D/A converter (DAC) resolution, andthe jitter of the switching signal. The jitter is determinedby measurements on the converter prototype. Afterward, themodel is verified with a test setup. Finally, the rms outputvoltage jitter is calculated including all effects mentionedbefore.

II. CONVERTER

The basic circuit of the boost converter including thesnubber circuits is shown in Fig. 3. The converter operationand the feedback controller are presented in detail in [2] andshortly mentioned in the following.

A. Operation

In the following, the operation of the converter is explained.1) Zero-Voltage Switching: The inductor current and the

switch voltage waveform are shown in Fig. 3. The switchesare turned ON at the beginning of interval T1. The inputvoltage Vin is applied across the inductor and the current rises.At the beginning of interval T2, S1 is turned OFF. The diodesare still blocking at that time. The inductor and the snubbercapacitances across the diodes and switches form a resonantcircuit. The positive inductor current charges the snubbercapacitors. When the snubber capacitors across the diodesare charged to zero, the diodes start to conduct (beginningof interval T3). Now, the difference between Vin and vout isapplied across the inductor, causing the inductor current todecrease. As soon as the inductor current reaches zero, thediodes stop conducting and another resonant transition takesplace. The snubber capacitors in parallel to the switches arecharged. At a certain point, the snubber capacitors in parallelto the switches are discharged to zero while the inductorcurrent is still negative (beginning of interval T5). The bodydiode of the MOSFETs starts to conduct. At that point, theMOSFETs are turned on at zero voltage before the inductorcurrent becomes positive again to initiate the next switchingcycle.

Fig. 3. Boost converter structure with snubber circuits and the correspondingwaveforms.

2) ZVS Boundary: To achieve ZVS, certain conditions haveto be met. The resonant transition during interval T4 can bemodeled as a resonant circuit with an equivalent capacitance of

Ceq = CS1 + CD1. (1)

The input capacitor is modeled as a voltage source. At thebeginning of the resonant transition, Ceq is charged to theoutput voltage. The inductor current is zero. With these initialconditions and assuming a linear capacitance, the circuit oscil-lates around the input voltage with an amplitude of vout − Vin.Hence, the condition for ZVS is

2 · Vin − vout < 0. (2)

Obviously, ZVS is achieved for Vin < vout/2.In a real system, the assumption of a linear equivalent

capacitance is not entirely valid. The capacitances of thesemiconductors show a strong voltage dependency.

Because the capacitance increases significantly at lowervoltages, more energy would be required to meet the ZVScondition. The only possibility to do so would be to store thisadditional energy in the inductor before T4. This is not possible


Fig. 4. Minimum peak switch current for the presented converter.

because the diodes are only capable of carrying current in onedirection; the ZVS input voltage range of the real system isdecreased.

The influence of the nonlinear capacitance of the semi-conductors is reduced by the snubber capacitors. The upperboundary of Vin for ZVS with different snubber capacitorvalues for the presented system is presented in [2].

If the diodes would be replaced by switches, the convertercould be operated under ZVS conditions in the whole operat-ing area because the amount of stored energy in the resonantcircuit can be controlled.

3) Minimum Peak Switch Current: To transmit power tothe output of the converter, the snubber capacitors have to becharged such that the diodes start to conduct. This is alwaysthe case outside the ZVS operating area since the systemis complementary to the one for the ZVS conditions of theMOSFETs.

Inside the ZVS operating area, a minimum inductor currentis required to transmit power to the output. The minimumcurrent for linear capacitances is

iLp,min =√

C

L· √

(vout − 2 · vin) · vout (3)

where C is the equivalent capacitance during the resonanttransition and L is the boost inductance. The minimum peakswitch current for the presented system is shown in Fig. 4.

4) Switch Control: The turn-ON time of the switch canbe controlled either by an ON-time control or by a peakcurrent control. Both methods are mathematically equivalent.The peak current control additionally provides an overcurrentprotection and is independent of the exact turn-ON time ofthe switch. The disadvantage of this control strategy is thatthe source current of the MOSFETs has to be measured. TheON-time control requires only a zero-crossing detection of theinductor current to determine when the ON-time starts.

The feedback controller for the ON-time control differsfrom the peak current control. Therefore, the output voltageprecision also depends on the control method. A detailedanalysis for both methods is presented in Section III-B1.

As already mentioned before, the switch has to be turnedON during the time interval T5 in case of ZVS or at the endof T4 if no ZVS is possible. The optimal time instance to turnON the switch is always at the end of T4, regardless if ZVS ispossible or not. This reduces the losses, since the conductionlosses of the switch are lower than those of the internal bodydiode.

Fig. 5. Sketch of the last switching cycle of the charging period.

There are several possibilities to determine the end of theinterval T4. The first one is based on a lookup table. Theinductor current zero crossing, which marks the beginning ofinterval T4, is detected. A simple lookup table for the lengthof T4 is then used to determine when S1 has to be turned ON

again.Another way would be by measuring the switch voltage

during T4. As soon as the voltage becomes zero, the switchis turned ON. Obviously, this method works only if ZVS ispossible. Outside the ZVS operating range, the switch voltagestarts to rise before it reaches zero. Since the minimum ofthe switch voltage is at the inductor current zero crossing, azero-crossing detection can be used in that case. The zero-crossing detection can be implemented using a saturabletransformer [3].

The lookup-table-based version is implemented in thepresented converter since it does not require a switch voltagemeasurement.

B. Converter Control

The feedback control for a capacitive load as well as thecontrol hardware are explained in the following. The feedbackcontroller for an ON-time controlled system and a peak currentcontrolled system differ slightly, which will be shown.

1) Charging Controller: Since the converter is operated inBCM, the switching cycles are independent as the convertercould stop operating at the end of each cycle. Hence, it ispossible to use a cycle-to-cycle-based feedback controller,which calculates the required peak current iLp or the ON-timeTon depending on the implemented converter control. To do so,the converter is modeled as a time discrete system, as shownin Fig. 5. The change of the output voltage vout,n+1 − vout,nfor a capacitive load within one switching cycle is

vout,n+1 − vout,n = √a + Vin − vout,n (4)

with

a = Z2(i2Lp−i2

Lp,min)+(Vin−vout,n)2, Z =√

L1

Cout. (5)

The required peak switch current can be calculated using (4)and (5) with vout,n+1 = vout,set

iLp =√

C

L· α + Cload

L· β (6)


Fig. 6. Switching period adjustment by set peak current.

with

α ={

(vout,n − 2Vin)vout,n, vout ≥ 2Vin

0, vout < 2Vin(7)

β1 = vout,set + vout,n − 2Vin (8)

β2 = vout,set − vout,n (9)

β ={

β1 · β2, vout,n < vout,set

0, vout,n > vout,set.(10)

It has to be noted that α becomes zero outside the ZVSoperating area.

For an ON-time control-based controller, the ON-time canbe calculated with

Ton = L

Vin· iLp = L

Vin·√

C

L· α + Cload

L· β. (11)

If multiple interleaved converters are used, the controllerhas to be slightly modified. By assuming that all n convertersare running with the same output power, the system can bemodeled as if every converter is running with an individualcharging controller charging only 1/n of the load. Hence, theinterleaving can considered using Cload/n instead of Cload.

2) Interleaving Controller: In the considered system, twoconverters are interleaved to reduce the input current rippleand increase the output power. In BCM, the set peak currentdirectly influences the switching period. This means that thephase shift ϕ = �Tn/Ts,0 between two converters can beadjusted by reducing or increasing the peak current iLp,1 ofone converter (Fig. 6). The peak current iLp,0 of the otherconverter is used as a reference for the interleaving.

Therefore, it is theoretically possible to achieve the desiredphase shift by setting iLp,1 to the appropriate value within oneswitching cycle. This is not always possible in a real systembecause the range of iLp,1 is limited. In that case, multipleperiods are required to achieve the desired phase shift. Thephase shift between two converters can be easily measuredusing the zero-crossing detection. The phase shift is set to0.5 for two converters. The optimal phase shift for morethan two converters depends on the number of interleavedconverters; the inductor values and the operating point andcould be calculated as desired [4].

The interleaving control requires four steps: 1) the periodlength Ts,0, as shown in Fig. 6, has to be measured; 2) theactual shift �Tn has to be measured; 3) the required periodlength Ts,1 to achieve the desired phase shift has to be calcu-lated; and 4) the corresponding peak current iLp,1 is calculated.

The main challenge of the interleaving control is the cal-culation of the required peak current iLp. The period lengthTp(iLp) as a function of the peak current can be analytically

Fig. 7. Waveforms with nonequal inductor values.

Fig. 8. Interleaving controller with offset compensation.

calculated. Unfortunately, the period length includes somenonlinear terms depending on iLp because of the resonanttransitions. Hence, the calculation of the required peak currentfor a given period length would be very time consuming. Tosimplify the calculation, Tp(iLp) is linearized

iLp,1 = iLp,0 + �iLp (12)

Tp(iLp,1) = Tp(iLp,0) + dTp(iLp)

diLp

∣∣∣∣iLp = iLp,0

�iLp

= Tp(iLp,0) + �Tp. (13)

Using (13), the required peak current to achieve the desiredphase shift can be easily calculated

�iLp = �TpdTp(iLp)

diLp

∣∣iLp = iLp,0

. (14)

For the sake of brevity, the linearized term dTp(iLp)/diLp

∣∣iLp = iLp,0

is not presented as it is very long.If both converters are exactly identical, the controller is

able to adjust the phase shift to the desired setpoint using(12) and (14). This is the case because both converters have thesame switching frequency at the peak current iLp,0. In a realsystem, the converters are, in general, not identical becauseof component tolerances, temperature drifts, and so on.Therefore, different peak currents are required for the sameswitching frequency (Fig. 7). This in turn leads to a staticdeviation of the setpoint such that

iLp,comp = �TpdTp(iLp)

diLp

∣∣iLp=iLp,0

. (15)

Hence, a compensation of the feedforward part iLp,0 isrequired. The simplest way to do this is an additionalcontroller. The phase shift offset compensation controlleradjusts iLp,0 to the value where both converters have the sameswitching frequency but at a different iLp,n . A simple integralcontroller or a proportional–integral controller can be used asoffset compensation controller.


Fig. 9. Feedback controller for n interleaved converters.

Fig. 10. Schematic diagram of the control hardware for one converter.

A block schematic view of the interleaving controller isshown in Fig. 8. The feedforward part iLp,0 is provided by thecharging controller.

Without the offset compensation, the controller is a simpleproportional controller with a feedforward part. The propor-tional gain is provided by the linearization and is thereforeadjusted depending on the operating point.

Combining the charging controller and the interleavingcontroller as presented, each converter is controlled by an indi-vidual controller. One converter is controlled by the chargingcontroller and is used as the reference for the interleaving(master converter). All other converters (slave converters) arecontrolled by an individual interleaving controller, as shownin Fig. 9. Since the slave converters infer with the chargingcontroller, the charging controller is not able to charge theload capacitor with the required precision. Therefore, theinterleaved converters are turned OFF shortly before the desiredoutput voltage is reached.

3) Control Hardware: A schematic diagram of the controlhardware is shown in Fig. 10. The control hardware incorpo-rates three measurement inputs: 1) the converter input voltage;2) the output voltage; and 3) the switch current. The voltagesare measured using a resistive capacitive voltage divider. Thesource current of the MOSFETs is measured with a shunt.The measured signals are fed via a preamplifier stage to theADC inputs and the comparator input, respectively.

The input and output voltages are sampled by an ADC thatis connected to a field-programmable gate array (FPGA). TheFPGA itself contains the feedback controller and the switchcontrol.

The feedback controller output is converted to an analogoutput signal by a DAC. This signal is then compared with

Fig. 11. Flow chart for calculating the output voltage distribution.

the measured switch current to determine when the switcheshave to be turned OFF for a peak current controlled system.

The switch control implemented in the FPGA generatesthe switching signal depending on the operating conditions.Finally, the switching signal is converted into an optical signal,which is transmitted to the converter.

III. PRECISION ANALYSIS

In the following, the output voltage precision is investigated.A flow chart including all the relevant effects influencing theprecision is shown in Fig. 11. First of all, the measurement ofthe input voltage, the output voltage, and the source currentinclude noise, e.g., thermal noise or flicker noise. The standarddeviation σ of the noise is equal to its rms value since the meanvalue of the noise is zero.

The input and output voltage measurements are sampledwith an ADC. The input stage of the ADC adds someadditional noise to the signal. In addition, the quantizationof the sampled signal limits the maximum possible signal-to-noise (SNR) ratio.

The sampled signals are then computed in the FPGAusing (6) for a peak current controlled system or (11)for an ON-time controlled system. The computation does notinfluence the precision significantly since the number of bitsis not limited to a fixed number in an FGPA. Since the inputand the output voltages are noisy signals, the controller outputis also a noisy signal.

The controller output is converted into an analog signalwith a DAC. The DAC has a finite resolution, which addssome additional noise. The DAC output is compared withthe measured source current to generate the switching signal.The switching signal itself is generated in the FPGA andis then transmitted to the switches. The signal generationand the signal transmission have a certain jitter. This jitterand all effects mentioned before result in a certain outputvoltage distribution for multiple charging cycles starting at thesame point. The output voltage distribution can be calculatedusing (4).


In the following, first, the algorithm used to calculate theoutput voltage distribution is described.

Second, both controllers are analyzed analytically to com-pare the control methods described in Section II-B. Only thesensitivity of iLp (6) and (11) on the input variables Vin andvout is investigated to compare the peak current controlledand the ON-time controlled system. Only the more precisecontroller is further investigated.

Third, all effects mentioned before are investigated sepa-rately to analyze their influence on the controller output andthe output voltage.

Fourth, all effects are included to calculate the outputvoltage precision of the presented converter.

A. Algorithm

The calculation of the output voltage distribution includesthe following effects.

1) Input voltage SNR.2) Output voltage SNR.3) Current measurement SNR.4) Controller limitations.5) ADC quantization noise.6) DAC quantization.7) Switching signal jitter.

It is also assumed that all measured values as well as theswitching signal jitter are independent normal distributedrandom variables.

A flow chart of the algorithm is shown in Fig. 11. First,all values used in the digital domain are transformed to theirquantized value. Then, a normal distributed set of pointswith a mean value of the real voltages μVin and μvout,n isgenerated for the input voltage Vin and the output voltagevout,n . The standard deviations σVin and σvout,n are determinedusing the SNR of the signals. The quantization is consideredby rounding toward their next integer value. This is also donewith the targeted output voltage vout,set. In general, somepoints in the measured output voltage distribution will belarger than the targeted output voltage vout,set. In these cases,the controller considers the charging cycle as finished andstops charging. Therefore, these points are directly forwardedto the final output voltage distribution of vout,n+1 after thecharging cycle.

As a next step, the required peak current iLp with thepreviously generated points is calculated the same way as it isdone by the controller implemented in the FPGA. Again, thecalculated values are rounded toward their next integer valueto consider the resolution of the DAC. Since the peak switchcurrent is limited by the switches and the inductor, all valuesabove this limit are set to the maximum peak switch current.

Afterward, the propagation delay tpd of the switching signalis scaled to a peak switch current offset using

ipd,scaled = tpd · Vin

L. (16)

To consider the current measurement SNR as well as theswitching signal, a normal distributed set of points im,normalwith a mean value μipd,scaled of the scaled propagation delay is

Fig. 12. Ratio (dB) of the input voltage sensitivities of both controllers.

generated. The standard deviation corresponds to the SNR ofthe measured switch current σis,m and the switching signal jitterσipd,scaled scaled to a current jitter. This is done by summing uptheir variances.

Then, the sum of the controller output distribution and thepreviously generated normal distribution is calculated

iLp,switched = iLp + im,normal. (17)

The result is the current switched by the converter iLp,switched.Using an appropriate converter model, the output voltagedistribution is calculated.

To investigate the influence of the effects mentioned atthe beginning of this section, all effects can be included orexcluded as desired in the algorithm.

B. Feedback Controller Sensitivity

The standard deviation of the controller output σc with theindependent random variables Vin and vout can be estimatedby taking the partial derivatives of the transfer functions

σ 2c =

(∂ fc(Vin, vout,n)

∂Vin

)2

σ 2Vin

+(

∂ fc(Vin, vout,n)

∂vout,n

)2

σ 2vout,n

where fc(Vin, vout,n) is the controller transfer function, σVin

and σvout,n are the standard deviations of the input variables.It is assumed that the standard deviations σVin and σvout,n aresmall compared with the related derivatives and Vin as well asvout,n are independent.

In the following, the controllers are compared with eachother by calculating their sensitivity on the input and outputvoltage measurement. To do so, the normalized derivatives of(6) and (11) are compared.

1) Controller Comparison: First, the output voltage sensi-tivity is investigated. The squared normalized coefficients forboth controllers are

a2Ton

=(

∂Ton(Vin,vout,n )∂vout,n

)2

T 2on

(18)

a2iLp

=(

∂iLp(Vin,vout,n )∂vout,n

)2

i2Lp

. (19)

a2Ton

and a2iLp

can be calculated using (6) and (11). After doingso, it turns out that both terms are equal. Hence, the outputvoltage sensitivity is the same for both feedback controllers.


Fig. 13. Contour plot of 20 · log kiLp for vout,set = 3 kV.

Second, the input voltage sensitivity is investigated

b2Ton

=(

∂Ton(Vin,vout,n )∂Vin

)2

T 2on

(20)

b2iLp

=(

∂iLp(Vin,vout,n)∂Vin

)2

i2Lp

. (21)

Comparing b2Ton

and b2iLp

, it turns out that

b2Ton

> b2iLp

. (22)

This result can be explained by the fact that the ON-time ofS1 is calculated using the peak current, the input voltage, andthe inductor value.

To compare both controllers for the given system, the ratio

k = 20 · logb2

Ton

b2iLp

(23)

for the presented converter with vout,set = 3 kV is shown inFig. 12.

Summarizing the results of this paper, the ON-time con-trolled system shows a larger sensitivity on the input voltagemeasurement uncertainties. Hence, a peak current controlledconverter is used and the ON-time controlled system is notfurther investigated.

2) Sensitivity on Input and Output Voltages: The input andoutput voltage sensitivity is compared by calculating the ratioof the absolute value of the partial derivatives of (6)

kiLp =∣∣∣ ∂iLp(Vin,vout,n)

∂vout,n

∣∣∣∣∣∣ ∂iLp(Vin,vout,n)∂Vin

∣∣∣ . (24)

The output voltage sensitivity is bigger than the input voltagesensitivity if kiLp > 1. This is the case when

vout,n >1

2(vout,set − Vin) with Cload � C. (25)

kiLp is shown in Fig. 13 for the presented converter forvout,set = 3 kV. The boundary for the output voltage givenby (25) is only relevant if it is possible to reach the targetedoutput voltage vout,set with vout,n+1 and the output voltagevout,n is in the region where kiLp < 1. This means that theoutput voltage step vout,n+1 − vout,n would have to be verylarge. Hence, the output voltage sensitivity is always bigger

Fig. 14. Standard deviation of iLp without limitations for 18 -bit resolutionwith the maximum possible output voltage SNR.

Fig. 15. Standard deviation of iLp without limitations for 24 -bit resolutionwith the maximum possible output voltage SNR.

than the input voltage sensitivity for large capacitive loads forthe presented converter.

C. System Analysis

In the following, different factors influencing the outputvoltage precision are investigated.

1) Quantization Noise: The variance of the quantizationerror for a signal uniformly distributed within the interval[−�/2,�/2] is given by

σ 2 = �2

12. (26)

Equation (26) is only applicable if the quantization step issufficiently small compared with the standard deviation of theinput signal. The effect on the quantization error of inputsignals with a standard deviation close to the quantizationinterval has been investigated in [5] and [6] for signals withand without bias within the quantization cell. These investiga-tions showed that the maximum deviation from (26) becomessmaller than 10−4 for standard deviations bigger than 0.7�.

The standard deviation of the analog input stage wasdetermined by performing a SPICE simulation and was deter-mined to be approximately 1.05� with the used 18 -bit ADC.Therefore, (26) can be used as an estimation for the quantiza-tion error. In that case, the maximum SNR for an N-bit ADCis given by

SNRmax = (1.76 + 6.02 · N) dB. (27)

2) Voltage Measurement SNR: In the following, the fullscale measurement range of the input and output voltage


Fig. 16. Standard deviation of iLp limited to 80 A for 18 -bit resolution withthe maximum possible output voltage SNR.

Fig. 17. Standard deviation of iLp limited to 80 A for 24 -bit resolution withthe maximum possible output voltage SNR.

Fig. 18. Standard deviation of iLp without limitations for 18 -bit resolutionwith the maximum possible input voltage SNR.

measurement is set to [0 −1650 V] and [0 −3300 V],respectively. To investigate the influence of the SNR, only thestandard deviation of the controller output is investigated toexclude interferences with other error sources. The followingsimulations are performed at an input voltage of 1300 V anda targeted output voltage of 3000 V. The ADC resolutionis set to 18 and 24 bits to investigate the influence of theresolution. Furthermore, it is investigated how the maximumswitch current of 80 A influences the standard deviation ofthe controller output. This is done by liming all output valuesto 80 A.

First, the results for the input voltage SNR are presented.The output voltage SNR is set to its maximum value. Voltagevout,n denotes the output voltage at the beginning of the switch-ing cycle in all following plots. Figs. 14–17 show the stan-dard deviation of the controller output for these simulations.

Fig. 19. Standard deviation of iLp without limitations for 24 -bit resolutionwith the maximum possible input voltage SNR.

Fig. 20. Standard deviation of iLp limited to 80 A for 18 -bit resolution withthe maximum possible input voltage SNR.

Fig. 21. Standard deviation of iLp limited to 80 A for and 24 -bit resolutionwith the maximum possible input voltage SNR.

The results shows that limiting the controller output to 80 Ahas no effect. The increased ADC resolution slightly influencesthe result that can be explained by an increased resolution ofthe controller output due to a higher number of possible inputvalues.

Second, the same simulations are performed for the outputvoltage SNR. The input voltage SNR is set to the maximumvalue.

Figs. 18–21 show that an higher ADC resolution leads to aslightly higher standard deviation at the controller output. Thiscan be explained by the decreased resolution at the controlleroutput for 18 bits, since the output values are shifted towardtheir next possible value. Hence, the values at the side of thedistribution are shifted toward the mean value. In contrast tothe case investigated before, the limitation of the controlleroutput to 80 A has a large influence. With a decreasing SNR,more output values are limited to the maximum value. This in


Fig. 22. Standard deviation of vout,n+1 depending on the switch currentmeasurement SNR.

Fig. 23. Standard deviation of vout,n+1 depending on the switching signaljitter.

turn leads to a lower standard deviation since the distributionbecomes narrower and more values are accumulated at 80 A.The same effect causes the standard deviation to decrease atlower values for vout,n , since the mean value of the unlimitedoutput increases when more charge is needed to achieve thetargeted output voltage.

When the influence of the input and output voltage SNR iscompared, the output voltage SNR has a much bigger influenceon the controller output distribution, as expected according toSection III-B2.

Summarizing the results of this section, the output voltageSNR is much more important than the input voltage SNR.In addition, the limitation of the controller output to 80 Adecreases the standard deviation at the output.

3) Current Measurement SNR: To investigate the influenceof the current measurement noise on the output voltagedistribution, all other effects have to be excluded. Hence, thecontroller output has to be equal to the value, which leads tothe targeted output voltage. The output voltage distribution iscalculated depending on the SNR of the current measurement.The full scale value is set to 100 A. The switching signal jitteris set to zero.

The resulting standard deviation output voltage distributionis shown in Fig. 22. The result shows that the error caused bythe current measurement noise is small even at a low SNR.

4) Switching Signal Jitter: The switching signal jitter ismodeled similar to the current measurement. It is modeledas a propagation delay with mean value μipd,scaled and standarddeviation σjitter. Afterward, it can be expressed as an amplitude

Fig. 24. Measured and predicted controller output without values outsidelimits.

Fig. 25. Measured and predicted controller output with values outside limits.

TABLE II

STANDARD DEVIATIONS AND MEAN VALUES OF THE

PERFORMED MEASUREMENTS

error in the switched current using

σ 2im =

(σtpd · Vin

L

)2

+ σ 2is,m (28)

μim = μtpd · Vin

L(29)

where σis,m denotes the standard deviation of the currentmeasurement noise. The mean value μjitter is set to 260 ns,which was determined by measurements. It is necessary toset μjitter large enough compared with σjitter. Otherwise, thiswould result in negative propagation delays, which is notpossible in a real system.

The result of the simulation (Fig. 23) shows that the outputvoltage error increases with increasing jitter as expected.In addition, the influence of the switching signal jitteris far below the targeted 30 mV even at a jitter of50 ns. The jitter of the real system is assumed to be lessthan 10 ns.


TABLE III

PARAMETER FOR THE PERFORMED PRECISION MEASUREMENT

IV. ALGORITHM VERIFICATION

Before the output voltage precision of the converter canbe calculated, the model presented in Section III has to beverified. First, the controller model is verified. Then, theprecision for a former test system predicted by the algorithmis compared with the measurements.

A. Controller Model

To verify the controller model, a test signal at the input ofthe control hardware is applied. Then, the sampled controllerinputs and outputs are recorded at the same time. The modeledcontroller output is calculated with these input values andcompared with the recorded output values. Two differentmeasurements were performed. First, the test signal is set suchthat the controller output always stays within the upper andlower boundaries (Fig. 24). Second, the test signal is set suchthat some controller output values are outside these limits(Fig. 25). A total of 51 200 samples were recorded in bothcases. The standard deviation σ and the mean value μ of bothmeasurements are given in Table II.

Both measurements match almost perfect with the predictedoutput of the controller model. The small deviation can beexplained by the method used to record the samples.

To maximize the amount of recorded samples, the length ofthe sample segments was set such that exactly one input andoutput value is recorded inside one segment. In the consideredmeasurements, the propagation delay of the controller islonger than the segment length. Therefore, the output valuecorresponding to a certain input value is recorded later inanother segment. This means that there is a certain amountof input and output pairs at the beginning and at the end ofeach record, which do not match.

B. Overall Model Validation

The overall model is validated by measuring the outputvoltage distribution of a former test system. To predict theaccuracy on a system level, the most important parameters forthe model have to be measured. The theoretical investigationmade in Section III shows that the precision is mainly givenby the output voltage measurement. Hence, only the SNR ofthe voltage measurements is measured. The SNR of the usedmeasurements system is 52.5 dB.

The model is verified by recording the reached voltage ofmultiple charge cycles. The reached voltage was measuredwith a PXI-4071 7.5 -digit digital multimeter (DMM). Theparameters for the measurement are shown in Table III.

The predicted standard deviation with these parameters andthe measured SNR is 970 mV. The specified 24 -h accuracy of

TABLE IV

PARAMETERS FOR OVERALL OUTPUT VOLTAGE PRECISION SIMULATION

Fig. 26. Standard deviation of iLp,switched for vout,set = 3 kV.

Fig. 27. Standard deviation of vout,n+1 for vout,set = 3 kV.

the DMM with the parameters for this measurement is 4.5 mVwith a temperature coefficient of 0.3 mV/°C. Therefore, theaccuracy of the DMM is sufficient for the measurement.

The measured standard deviation after 93 charging cyclesis 1.03 V. The measured standard deviation is 6% higher thanthe predicted standard deviation. A higher standard deviationcan be expected since the converter model is an idealizedmodel and therefore represents a lower limit for the chargingprecision. The model does not included effects, such as thenonlinear output capacitance of the MOSFETs, conductionlosses, component tolerances, temperature drifts, or the res-onance caused by the cable connecting the output capacitor ofthe converter and the load.

V. SYSTEM OUTPUT VOLTAGE PRECISION

As a last step, the output voltage accuracy including alleffects mentioned before is evaluated. The output voltageprecision depends only on the last switching cycle since the


converter is operated in BCM. Hence, only starting valuesvout,n are considered where the system can reach the targetedvoltage vout,set within one switching cycle.

The system was simulated with the parameters shown inTable IV.

First, the system is simulated for a targeted output voltageof 3 kV. Fig. 26 shows the standard deviation of the switchedsource current. The maximum deviation is around 25% of themaximum switch current. This can be explained by the smallvoltage step vout,n+1−vout,n compared with the targeted outputvoltage vout,set. Therefore, a very high SNR would be requiredto calculate the peak current more accurate, as already shownbefore. The result shows that a 12 -bit DAC is sufficient sinceits resolution is much higher than the standard deviation ofthe controller output.

The standard deviation of the reached output voltage isshown in Fig. 27. The maximum standard deviation is around25 mV, which corresponds to 8.3 ppm.

These results show that a very high SNR is required toachieve a charging precision of less than 10 ppm. As anext step, the final prototype has to be built based on theexperience made with the first test setup. The most difficultpart is the output voltage measurement because the converterincludes several noise sources like the fans used to cool thesystem as well as the noise caused by switching transients.Therefore, all critical components require a good shielding.Another challenging task is the design of a fast enough low-noise analog circuitry, which is required to drive the ADC.

VI. CONCLUSION

In this paper, the charging precision of a 40 -kW 3 -kV soft-switching boost converter is analyzed. The converter operatingprinciple as well as the control strategy are briefly introduced.Two different control methods are investigated analytically bycomparing their sensitivity on the input and output voltagemeasurement.

Afterward, an algorithm to investigate the charging repe-tition accuracy is presented. The analysis includes the SNRof all measured signals, the controller output limitations,quantization-related errors, the finite resolution in the digitaldomain, and the switching signal jitter.

All effects mentioned above are investigated separately todetermine their effects on the output voltage precision. Itturned out that the output voltage precision is mainly limitedby output voltage measurement SNR.

Then, the model used to calculate the precision is verifiedby the measurements. First, the controller model is verifiedby comparing the calculated controller output and the mea-sured controller output for a given set of controller inputs.The measurement shows that the controller model fits verywell with the implemented controller.

Second, the overall model is verified by measuring a set ofcharging cycles and comparing it with the predicted standarddeviation of the model. The SNR of the voltage measurementsis measured to match the predicted precision with the per-formed measurement. The measured standard deviation is only6% higher than the predicted precision.

Finally, the output voltage precision including all errorsources mentioned before is analyzed. This paper shows thatthe repetition accuracy of the presented converter and controlhardware is 8.3 ppm at an output voltage of 3 kV with a loadof 2.88 mF.

REFERENCES

[1] (2014, Mar.). SwissFEL [Online]. Available: http://www.psi.ch/swissfel/[2] D. Gerber and J. Biela, “40kW, 3kV soft-switching boost converter for

ultra precise capacitor charging,” in Proc. 4th Euro-Asian Pulsed PowerConf., 2012, pp. 1–10.

[3] J. Biela, D. Hassler, J. Miniboeck, and J. W. Kolar, “Optimal designof a 5kW/dm3 / 98.3% efficient TCM resonant transition single-phasePFC rectifier,” in Proc. Int. Power Electron. Conf. (IPEC), 2010,pp. 1709–1716.

[4] S. Waffler, J. Biela, and J. Kolar, “Output ripple reduction of anautomotive multi-phase bi-directional dc-dc converter,” in Proc. EnergyConvers. Congr. Exposit. (ECCE), 2009, pp. 2184–2190.

[5] I. Kollar, “Bias of mean value and mean square value measurementsbased on quantized data,” IEEE Trans. Instrum. Meas., vol. 43, no. 5,pp. 733–739, Oct. 1994.

[6] A. B. Sripad and D. L. Snyder, “A necessary and sufficient conditionfor quantization errors to be uniform and white,” IEEE Trans. Acoust.,Speech Signal Process., vol. 25, no. 5, pp. 442–448, Oct. 1977.

[7] G. Chiorboli and M. Fontanili, “Analysis of roughly quantized Gaussiansignals,” in Proc. 16th IEEE Instrum. Meas. Technol. Conf., vol. 2.May 1999, pp. 1167–1171.

Dominic Gerber received the M.Sc. degree in elec-trical engineering and information technology fromETH Zurich, Zurich, Switzerland, in 2010, wherehe is currently pursuing the Ph.D. degree with theLaboratory for High Power Electronic Systems.

He focused on power electronics, drive systems,and high-voltage technology during his studies. Hiscurrent research interests include solid-state modu-lators, high-accurate capacitor charging, and currentmeasurement based on the Faraday effect.

Juergen Biela (S’04–M’06) received the Diploma(Hons.) degree from Friedrich-Alexander-Universitaet, Erlangen-Nuernberg, Nuremberg,Germany, and the Ph.D. degree from the SwissFederal Institute of Technology (ETH) Zurich,Zurich, Switzerland, in 1999 and 2006, respectively.

He dealt, in particular, with resonant dc-linkinverters with the University of Strathclyde,Glasgow, U.K., and the active control of series-connected IGCTs with the Technical University ofMunich, Munich, Germany, during his studies. In

2000, he joined the Research Department, Siemens Automation and Drives,Erlangen, Germany, where he was involved in inverters with very highswitching frequencies, SiC components, and EMC. In 2002, he joined thePower Electronic Systems Laboratory (PES), ETH Zurich, for working towardthe Ph.D. degree, focusing on optimized electromagnetically integratedresonant converters. From 2006 to 2007, he was a Post-Doctoral Fellow withPES and a Guest Researcher with the Tokyo Institute of Technology, Tokyo,Japan. From 2007 to 2010, he was a Senior Research Associate with PES.Since 2010, he has been an Associate Professor in high-power electronicsystems with ETH Zurich. His current research interests include the design,modeling, and optimization of PFC, dc–dc and multilevel converters withemphasis on passive components, and the design of pulsed-power systemsand power electronic systems for future energy distribution.

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Charging Precision Analysis of a 40-kW 3-kV Soft-Switching