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Characterization Presentation Spring 2010

ASIC Tester

Abo-Raya Dia- 4th year student

Damouny Samer- 4th year student

10-April

Supervised by: Ina Rivkin

210-April

Overview :

• Objective: testing the ASIC’s functional correctness

• Comparing the provider’s input with the expected outputs

• Providing options for viewing and analyzing the results

310-April

PC ASIC tester

Project Description :

FPGANOGAStarII

DUT

Adaptive board

User Interface

GiDEL PROCe

PCIe

4

So Far

10-April

510-April

Technical specifications :• The tester supports up to 96 inputs/outputs and up to

48 bi-directional pins.

• Samples I/O signals up to 100 MHz rate.

• Independent voltage suppliers: -10 v- 10v.

• 1G memory for each input and output vectors .

• Two clk pins .

610-April

FPGA

FIFO IN

FIFO OUT

DDRA

DDRB

CONTROLER

PSDB

DUTPLL

Hardware :• Sending the vectors from DDR A to FIFO IN (working with the high Freq. )

• Transferring the vectors to the DUT via the voltage translators on the PSDB (working with the DUT Freq. )

• Sampling the DUT outputs and saving them in DDR B

710-April

Software:

• Configuring the ports • Defining the ASIC’s work conditions (clocks & voltage level )• Sending the input vectors to the DDR • Comparing the outputs with the expected outputs .

Configuration mode screen

Debug mode screen

810-April

New Features

910-April

1. The Loop command :

Send the vectors between lines a & b N times .

Requirements:

a. Loop nesting :2.b. Writing the output vectors to the output file in a cyclic

way. c. The need to match between the inputs & outputs .

Hardware Changes:

1010-April

2. Embedded Logic Analyzer :

Allow the user to see the signals between the FPGA & the DUT, when a trigger occured .

Requirements :

a. In order to see the signals , the User should launch Altera Signal Tap , with no need to compile the design .

b. To raise the trigger when we recognize a combination of the input Data .

1110-April

3. Waves Library:

Creating an input vectors based on waves library , e.g. : counter (increment/decrement), pulse, random , const. value ,compound clk (clk edges time ,frequency , Duty cycle ) .

Counter : start from a , each clock cycle increment or decrement the vector by x , till you reach b .

Software Changes:

1210-April

4. Sampling frequency:

Allow the user to sample the outputs with a higher frequency than the DUT.

5. Graph :

A graph for all the output files, when each file was with another frequency .

1310-April

Summary:The new debug mode

Logic Analyzer Loop Load wave

Sampling Freq.

Summary Graph

1410-April

Gant chart :