Characterization of Large and Small Periphery GaN HFETs Under High Voltage and High Current Pulses

Characterization of Large and Small Periphery GaN HFETs under High Voltage and High Current PulsesS. K. Murad1, L. Harm1, J. Klappe1, T. Rdle1 , F. van Rijs1 , P. van der Wel1, P. Waltereit2, W. Bronner2, R. Quay2, M. Dammann2, F. van Raay2, M. Mikulla2,M. Musser2, S.Muller2, D. Floriot3, F. Bourgeouis3, J. Thorpe3, R. Behtash3, H. Blanck3, M. Hosch, and K. Riepe3 NXP Semiconductors, Gerstweg 2, 6534 AE, Nijmegen, The Netherlands 1 Fraunhofer Institute for Applied Solid State Physics, Tullastrasse 72, 79108 Freiburg, Germany2 United Monolithic Semiconductors, Wilhelm-Runge-Strasse 11, 89081 Ulm, Germany3

OutlineWhy do we need to do pulsed IV measurement on large packaged devices. A 30A, 600 W Drain pulse head as a prototype from Auriga. Measurement setup. The problem and solutions with measurement of large packaged devices, i.e. a 12mm or a 36mm power devices during pulsed IV. Determination of Ids-max (when does the Ids saturate) Importance for load lines and VSWR Cold and Hot drain lag on large devices compared to small device peripheries Gate lag measurements on various device sizes. Conclusions

COMPANY CONFIDENTIAL 2 Subject / Department / Author February 20, 2012

The necessity of Pulsed IV measurementGaN power devices are capable of very high power densities, measuring the Ids-sat capabilities in these devices using DC is impossible because of the huge dissipation power. For example a 12 mm device can work at 50V and have an Ids-max(Ids-saturation of >1A/mm), I.e 600W of DC dissipation.This would lead to device destruction.

For modeling purposes, it is also essential that the models cover all regions of device operation under large signal RF.

Pulsed IV is also can also reveal trapping effects in the devices


For modeling its essential that all RF trajectories are covered1639w2,36mm,Q00Limits Vg=-1.5 Vg=0.5 30.0 Vg=-3.0 Vg=-1.0 Vg=1.0 Vg=-2.5 Vg=-0.5 Vg=1.5 Vg=-2.0 Vg=0.0 Vg=2.0

25.0

Ids at Pmax

20.0 Id (amps)

15.0

If Ids-max at +1V

10.0

5.0

0.0 0.0

10.0

20.0

30.0

40.0 50.0 Vd (volts)

60.0

70.0

80.0


Auriga A4550 Pulsed IV systemThe pulsed IV system from Auriga is an integrated system that can deliver pulses up to 200V and 600W. It uses two pulses, one at the Gate and one at the Drain, pulses are synchronized and can deliver clean pulses down to 500nsec reliably @ 150V and 600W. Pulse heads are easily interchangeable and have different power rating to suit the device size. Pulse traces can be viewed live for the all pulses, that is Vgs, Ig, Vds and Id during typical FET measurements. Ultimately the pulse shapes are also affected by the measurement system that they feed, for a stable system an oscillation free setup is required.


1usec pulses during device operation @ 600WVg Ig Vd Id

Vg

Ig

Vd

Id

Gnd Gnd

Gnd Gnd

Gnd Gnd

Gnd Gnd

Q AptQ Apt Non-Q Apt

Non-Q Apt

0.00

0.25u

0.50u

0.75u

1.00u 1.25u Time (sec)

1.50u

1.75u

0.00

0.25u

0.50u

0.75u 1.00u 1.25u Time (sec)

1.50u

1.75u

20Ax30V pulses=600W

pulses=12Ax50=600W


@ 500 nsec pulsesVg Ig Vd IdVg Ig Vd Id

Gnd Gnd

Gnd Gnd

Gnd

Gnd

Q Apt

Non-Q Apt

0.0

100.0n

200.0n

300.0n

400.0n

500.0n

600.0n

700.0n

800.0n

900.0n

1000.0n

Q Apt0.0 100.0n 200.0n 300.0n 400.0n 500.0n

Non-Q Apt600.0n 700.0n 800.0n 900.0n

Time (sec)

Time (sec)

20Ax20V pulses=400WCOMPANY CONFIDENTIAL 7 Subject / Department / Author February 20, 2012

A 600W capability, But how!!36mm, Q0m7VLimits Vg=-1.5 30.0 Vg=-4.0 Vg=-1.0 Vg=-3.5 Vg=-0.5 Vg=-3.0 Vg=0.0 Vg=-2.5 Vg=0.5 Vg=-2.0 Vg=1.0

25.0

20.0

600 W power compliance

Id (am s) p

15.0

10.0

5.0

0.0COMPANY CONFIDENTIAL

0.0

10.0

20.0

30.0

40.0

50.0

60.0

Vd (volts)

70.0 80.0 90.0 100.0 Subject / Department / Author February 20, 2012

8

Measurement set upTo stabilize the large power bars devices, 7.2mm devices were first used, a simple test structure shown below was used. Low frequency oscillation were observed 20-600 MHz, also the decoupling capacitors were problematic for pulses.

Gate Pulse

Drain Pulse

Ground

Ground

R50Ohm Load

D 50Ohm Load S GroundCOMPANY CONFIDENTIAL 9 Subject / Department / Author February 20, 2012

Measurement set-up continue - Oscillation can be detected on the pulses, low frequency oscillationscaused by absence of large decoupling capacitors. - Large decoupling capacitors charge up during pulses and cannot be used. - A 7.2mm device IV curves show oscillations - Need to improve the set up.Vg Ig Vd Id

Tas402w7,7p2mm-Q00-1u,Id Tas402w7,7p2mm-Q0m5V-1u,Id 7.00 6.00 5.00 Id A 4.00 3.00 2.00 1.00 0.00 0 10 20 30 40 50 Vgs (V)3.8u 4.3u 4.8u 5.3u 5.8uGnd Gnd

Gnd Gnd

60

70

80

90 100

Q Apt

Non-Q Apt

0.3u

0.8u

1.3u

1.8u

2.3u



A 1 usec pulse; effect of having larger decoupling capacitorsVg Ig Vd Id

-Capacitors start charging and discharging when the time constant (I.e capacitor size) is too large compared to the pulse frequency.Gnd Gnd Gnd Gnd

-Typically capacitors few 100 pF will not have a impact on pulse shapes -But not totally avoidable, need to be far enough from the measurement window.

Q Apt

Non-Q Apt

0.00

0.25u

0.50u

0.75u

1.00u Time (sec)

1.25u

1.50u

1.75u


Making a stable measurement set up for large devicesThe measurement system was fitted with input and output Tuners, as well as damping elements (LCR network) at the input. However the LCR network depends on the device size.

Gate Pulse

Drain Pulse

Ground

Ground D Tuner Dir.Coup

R50Ohm Load Tuner

50Ohm Load

S Ground Spectrum analyzerCOMPANY CONFIDENTIAL 12 Subject / Department / Author February 20, 2012

7.2mm:- After stabilization with the LCR network at the input of the gate pulse, pulses become more regular, and no Oscillation is observed. - IdVd curves for a 7.2mm device measured with a 500nsec pulse, 1% duty cycle and 120W compliance.Vg Ig Vd Id

Id vs VdLimits Vg=2.0 7.0 Vg=-2.0 Vg=3.0 Vg=-1.0 Vg=4.0 Vg=0.0 Vg=1.0

6.0

Gnd

Gnd

5.0

Id (amps)

4.0Q Apt0.0 100.0n 200.0n 300.0n 400.0n 500.0n

3.0

Non-Q Apt600.0n 700.0n 800.0n 900.0n

2.0

Time (sec)

1.0

0.0 10.0 20.0 30.0 40.0 50.0 60.0 Vd (volts) 70.0 80.0 90.0COMPANY CONFIDENTIAL 13 Subject / Department / Author February 20, 2012

100.0

12mm Stabilization:- Tuned solution with LC shunted in the input, again no Oscillations. - IdVd curves with a 500 nsec pulse, 1% duty cycle.

Vg

Ig

Vd

Id

1639w2-12mm-Q00-20C-1usec-LPtu,2NF,cap,shunt,input.csvLimits Vg=-1.0 Vg=1.0 10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.00.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0

Vg=-2.5 Vg=-0.5 Vg=1.5

Vg=-2.0 Vg=0.0 Vg=2.0

Vg=-1.5 Vg=0.5

Gnd Gnd

Gnd Gnd

Id (amps)

Q Apt

Non-Q Apt

33.0n

133.0n

233.0n

333.0n

433.0n

533.0n

633.0n

733.0n

833.0n

933.0n

Time (sec)

90.0

100.0

Vd (volts)


Stabilization of 36mmPower bars:The power bars are too large to be measured to Ids-max level, Using the 10A Drain pulse head. Before stabilization


Power Bars: Stable measurement - A 36 mm packaged (SOT502) power bar measured using a 1usecpulse, 1% duty cycle and 600W power compliance.36mm, Q0m7VLimits Vg=-1.5 30.0 Vg=-4.0 Vg=-1.0 Vg=-3.5 Vg=-0.5 Vg=-3.0 Vg=0.0 Vg=-2.5 Vg=0.5 Vg=-2.0 Vg=1.0Vg Ig Vd Id

25.0

Gnd Gnd

Gnd Gnd

20.0 Id (amps)

15.00.00

Q Apt

Non-Q Apt

0.25u

0.50u

0.75u


1.50u

1.75u

10.0

5.0

0.00.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 100.0

Vd (volts)


Depending on Epi and Technology, a 30A is easily reached and no longer enoughGF0426w11 Vds=+1 to -4 V in 0.5V step GF0426w11-36mm-Q00,to+2V 30.0 25.0 20.0 Id A 15.0 10.0 5.0 0.0 0 20 Vds (V) 40 60COMPANY CONFIDENTIAL 17 Subject / Department / Author February 20, 2012

Determination of Ids-maxAt what Vgs level should we fix Ids-max. If we defined Ids-max as Ids @ Vgs=+1V, where the Schottky nominally should open while measuring at Vds=10V. Does not reflect the true value of the saturated current.

One way of looking at it, is to calculated Ids-max from the actual P-max measured using IS95 signal, compared to Pulsed IV measured Ids using a similar Quiescent point to have equal thermal dissipation.


Ids-max if P-max is measured, Ids-max is >30A compared to 24A when Ids at +1V1639w2,36mm,Q00Limits Vg=-1.5 Vg=0.5 30.0 Vg=-3.0 Vg=-1.0 Vg=1.0 Vg=-2.5 Vg=-0.5 Vg=1.5 Vg=-2.0 Vg=0.0 Vg=2.0

Ids @ VSWR Ids at Pmax

25.0

20.0 Id (amps)

15.0

If Ids-max at +1V

10.0

5.0

0.0 0.0

10.0

20.0

30.0

40.0 50.0 Vd (volts)


60.0

70.0

80.0

Test signal: IS95 signal

PpeakPAR: Peak to Average Ratio

Pout Pav Time IS95 Signal: PAR =9.8 dBPpeak of Amplifier = Pav_of_output_signal + PAR _of output signalPpeak ~ 10 Peak

Ids-max= 4 Ppeak of Amplifier / (Vds-Vkee)COMPANY CONFIDENTIAL 20 Subject / Department / Author February 20, 2012

Measurement of Pmax using IS95 signal versus WgPpeak vs Wg Tuned at Max Pout 10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 0

[W/mm]

1037VIII 1639_2

Max Pout

Tasman301 FG0622_06 EP

Si 50 mm

Power Bar50 60

10

20

30

40

1037VIII 1639w2 Tasman -402 Tasman 301 FG0622 Si 50 mm

Wg [mm]


Calculated Ids-max from measured Pmax using IS95 compared Idsmax at Vgs=+1V measured from pulsed IV curves - This shows a low estimate for Ids-max of up 40%Measured and Calculated Ids-max

1.00 0.90 0.80 0.70 Id A/mm 0.60 0.50 0.40 0.30 0.20 0.10 0.00 0 5 10 15 20Wg (mm)COMPANY CONFIDENTIAL 22 Subject / Department / Author February 20, 2012

1639w2, Imax from Pmax Tasman402-w7, Imax from Pmax Tasman301 Imax from Pmax 1639w2, Imax meas @ Vgs=1V Tasman402-w7, Imax meas @ Vgs=1V Tasman301 Imax meas @ Vgs=1V

25

30

35

40

Calculated Ids-max from measured Pmax using IS95 compared to Ids-max at Vgs=+2V measured from pulsed IV curves; - Measured Ids @ 2V is still lower than IS95 extracted Ids for 12mm. But for 36mm is higher. - Measurement of Ids-max should be measured at Vgs of >/= to +2V. - Ids-max scaling with Wg is extremely flat.Measured and Calculated Ids-max

1.00 0.90 0.80 0.70 Id A/mm 0.60 0.50 0.40 0.30 0.201639w2, Imax meas @ Vgs=2V 1639w2, Imax from Pmax Tasman301 Imax from Pmax

0.10Tasman301 Imax meas @ Vgs=2V

0.00 0 5 10 15 20Wg (mm)COMPANY CONFIDENTIAL 23 Subject / Department / Author February 20, 2012

25

30

35

40

Drain and Gate lag measurementsThe gatelag effects that are attributed to surface traps or interface traps between SiN and semiconductor layer. Gate lag is measured using two different quiescent bias condition, first Q point was set Vds and Vgs=0V, and IdVd measured. Then Q point was set to Vds=0V and Vgs=-7V.

Cold Drain-lag (device in Pinch-Off); This describes the slow response of the drain current when the Vds is pulsed from predefined quiescence point. This slow response is attributed to the traps in the buffer layer or nucleation layer Cold Drain Lag is measured at two different Drain Quiescent points, first Q point is at Vds=0V, Vgs=-7V and compared to Vds=50, Vgs=-7V.

Hot drain-lag (the device is under a predefined quiescent point). This is important to show the current slump when the device operates at a quiescent point similar to QP in RF operation. Typically at 20 to 40 mA/mm @ 50V.


Cold drain lag on small device peripheries On 2.4mm Packaged device

- @ 50V, -5V Drain = 15% - @ 28V, -5V Drain lag= 7%

Drain Lag of Packaged 2.4mm, IAF processing @Vds=28V and @50V, Vgs=-5V

1037II,2p4mm, Id,Q0m5V, packaged 1037II,2p4mm, Id,Q50Vm5V, packaged

Vg

Ig

Vd

Id

2.00

1037II,2p4mm, Id,Q28Vm5V,packagedGnd Gnd Gnd Gnd

1.50 Id A/mmQ Apt Non-Q Apt

1.00

0.00

0.25u

0.50u

0.75u


1.50u

1.75u

0.50

Pulses during cold Drain lag

0.00 0 20 40Vgs (V)

60

80

100


Hot and cold drain lag on 12 mm devices, - Cold Drain lag=13% reduction compared to 15% on 2.4mm- Hot Drain lag= 23% when Pdiss at 2W/mm - Knee voltage walkoutHot (2W/mm) and cold Drain Lag, GF0426w11,12 mm Vds=+3 to -3V in 1V step

13.8GF0426w11-12mm-Q0m7V

11.8 9.8 Id A 7.8 5.8 3.8 1.8 -0.3 0 20 40

GF0426w11-12mm-Q50m7V GF0426w11-12mm-Q50m2p7

60 Vds (V)

80

100COMPANY CONFIDENTIAL 26 Subject / Department / Author February 20, 2012

Cold Drain lag at higher Drain voltage;Q80,-7V, a slight increase in drain lag compared to Q50,-7V

Cold Drain Lag, GF0426w11,12 mm Vds=+3 to -3V in 1V stepGF0426w11-12mm-Q50m7V

13.8 11.8 9.8 Id A 7.8 5.8 3.8 1.8 -0.3 0 20 40

GF0426w11-12mm-Q80m7V, to Vgs=+2V GF0426w11-12mm-Q0m7V

60 Vds (V)

80

100


Cold drain lag on 36mm devices:- Q(0,-7V) compared to Q (50V, -7V) - Cold Drain lag= 16% is similar to 2.4mm (15%) from the same wafer - Knee voltage walkout - Most of Drain lag is Buffer relatedCold Drain lag Lag, GF0426w11 Vds=+1 to -4 V in 0.5V step 30.0 25.0 20.0 Id A 15.0 10.0 5.0 0.0 0 20 40 Vds (V) 60 80 100COMPANY CONFIDENTIAL 28 Subject / Department / Author February 20, 2012

GF0426w11-36mm-Q50m7V GF0426w11-36mm-Q0m7

Gate Lag on small devices (2.4mm Packaged) - Shows no Gate lag

Q@ Vds=0V,Vgs=0V, nQ=Vds=0V,Vgs=-5V

2.50 1598w12-2p4mm,A73-packaged-4usec-Q00,Id 2.00

1598w12-2p4mm,A73-packaged-4usec-Q0m5V,Id

1.50 Id A/mm 1.00 0.50 0.00 0 10 20 30 40 50 Vgs (V) 60 70 80 90 100


1639w2, 12 mm, 10% gate lag observed, in contrast to smaller devices from the same waferGate Lag, 1639w2,12 mm Vds=+4 to -2 V in 1V step

1639w2-12mm-Q00

1639w2-12mm-Q0m7

14.0 12.0 10.0 8.0 Id A 6.0 4.0 2.0 0.0 0 20 40 Vds (V)COMPANY CONFIDENTIAL 30 Subject / Department / Author February 20, 2012

60

80

1598w12, 36mm,- 18% gate lag observed, in contrast to no gate lag on smaller devices from the same wafer - No knee voltage walkoutGate Lag, 1598w12, 36mm Vgs=+1 to -2.5 V, in 0.5V step 30.001598w12-36mm,1u,Q0m7V

25.00 20.00 15.00 10.00 5.00 0.00 0 -5.00 10 20 30

1598w12-36mm,1u,Q00

Id A

40

50

60

70

Vds (V)


Gate lag on 36mm: - Different Epi supplier and processed at UMS, again gate lag on large devicesGate Lag, Tasman 301, 36mm, Vgs=+2 to -2 V, in 0.5V step

25.00 20.00 15.00 10.00 5.00 0.00 0 10 20 30 40

Tas,301,Q00,Id Tas 301, 36mm,Q0m7V,Id

Id A

50

60

70

80

Vds (V)


ConclusionsAuriga Pulsed IV system with a 600W and 200V, 500 nsec capability is very well suited for large device isothermal characterization and it is recommended for any modeling group. Ultimately the pulse shapes are also affected by the measurement system that they feed, for a stable system an oscillation free setup is a MUST. Oscillation problems during pulsed IV in large devices can be solved using Tuners and additional damping elements depending on device sizes. Measurements of Ids-max @ +1V or +2V under estimates the true Ids-max, pulsed large signal RF (IS95 signal as an example) are required to validate current capabilities for any technology. The GaN technology developed in the Philugan project can deliver a very high power densities @ 50V, Ids scaling is very flat from 2.4 to 36mm. Drain lag is not affected by device scaling for our Technology. Gate lag on large devices can still be an issue even if it does not exist for small devices. Leading to a reduction in Pmax.COMPANY CONFIDENTIAL 33 Subject / Department / Author February 20, 2012

Documents

Characterization of Large and Small Periphery GaN HFETs Under High Voltage and High Current Pulses