CHAPTER 9a Digital Analog and Analog Digital Convertersweb.cecs.pdx.edu/~chiang/ECE_510_Spring_2012/Allen_3ed_ch9a.pdf · Figure 9.3-9 M + K-bit DAC using an M-bit charge scaling

CMOS Analog Circuit Design Allen/Holberg Copyright (c) 2012 Oxford University Press, Inc.

CHAPTER 9a

Digital–Analog and Analog–Digital Converters


Figure 9.1-1 Digital–analog converter in signal-processing applications.


Figure 9.1-2 (a) Digital–analog converter in signal-processing applications. (b) Clocked digital–analog converter for synchronous operation.


Figure 9.1-3 Block diagram of a digital–analog converter.


Figure 9.1-4 Ideal input–output characteristics of a 3-bit DAC.


Figure 9.1-5 Quantization noise for the 3-bit DAC of Fig. 9.1-4.


Figure 9.1-6 (a) Illustration of offset error in a 3-bit DAC. (b) Illustration of gain error in a 3-bit DAC.


Figure 9.1-7 Illustration of INL, DNL, and nonmonotonicity in a 3-bit DAC.


Figure 9.1-8 The 4-bit DAC characteristics for Example 9.1-1.


Figure 9.1-9 Input–output test for a DAC.


Figure 9.1-10 Spectral output test for a DAC.


Figure 9.2-1 Classification of digital–analog converters.


Figure 9.2-2 General current scaling DAC.


Figure 9.2-3 Binary-weighted resistor DAC implementation.


Figure 9.2-4 R–2R ladder implementation of the binary-weighted resistor DAC.


Figure 9.2-5 Current scaling using matched MOSFETs.


Figure 9.2-6 General voltage scaling DAC.


Figure 9.2-7 (a) Implementation of a 3-bit voltage scaling DAC. (b) Input–output characteristics of (a).


Figure 9.2-8 Alternate realization of Fig. 9.2-7(a).


Figure 9.2-9 General charge scaling DAC.


Figure 9.2-10 Charge scaling DAC. All switches are connected to ground during 1. Switch Si closes to VREF if bi = 1 or to ground if bi = 0 during 2.


Figure 9.2-11 Equivalent circuit of Fig. 9.2-10.


Figure 9.2-12 Binary-weighted, charge amplifier DAC implementation.


Figure 9.3-1 Combining an M-bit and K-bit subDAC to form an M + K-bit DAC by dividing the output of the K-LSB DAC.


Figure 9.3-2 Combining an M-bit and K-bit subDAC to form an M + K-bit DAC by dividing the VREF to the K-LSB DAC.


Figure 9.3-3 Combination of current scaling subDACs using a current divider.


Figure 9.3-4 Combination of two, 4-bit charge scaling subDACs to form an 8-bit charge scaling DAC.


Figure 9.3-5 Simplified equivalent circuit of Fig. 9.3-4.


Figure 9.3-6 Combination of two, 4-bit, binary-weighted, charge amplifier subDACs to form an 8-bit, binary-weighted, charge amplifier DAC.


Figure 9.3-7 M + K-bit DAC using an M-bit voltage scaling subDAC for the MSBs and a K-bit charge scaling subDAC for the LSBs.


Figure 9.3-8 (a) Equivalent circuit of Fig. 9.3-7 for the voltage scaling subDAC. (b) Equivalent circuit of the entire DAC of Fig. 9.3-7.


Figure 9.3-9 M + K-bit DAC using an M-bit charge scaling subDAC for the MSBs and a K-bit voltage scaling subDAC for the LSBs.


Figure 9.4-1 Simplified schematic of a serial charge-redistribution DAC.


Figure 9.4-2 Waveforms of Fig. 9.4-1 for the conversion of the digital word 1101. (a) Voltage across C1. (b) Voltage across C2.


Figure 9.4-3 Pipeline approach to implementing an algorithmic DAC.


Figure 9.4-4 Equivalent realization of Fig. 9.4-3 using iterative techniques.


Figure 9.4-5 Output waveform for Fig. 9.4-4 for the conditions of Example 9.4-2.

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CHAPTER 9a Digital Analog and Analog Digital Convertersweb.cecs.pdx.edu/~chiang/ECE_510_Spring_2012/Allen_3ed_ch9a.pdf · Figure 9.3-9 M + K-bit DAC using an M-bit charge scaling