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2007 Fall: Electronic Circuits 2
CHAPTER 9Operational-Amplifier andOperational Amplifier and Data-Converter Circuits
Deog-Kyoon Jeongdkj @ [email protected]
School of Electrical EngineeringS l N ti l U i itSeoul National University
Introduction
In this chapter, we will be covering…
The Two-Stage CMOS Op Ampe o S age C OS Op pThe Folded-Cascode CMOS Op AmpThe 741 Op-Amp CircuitThe 741 Op Amp CircuitD/A ConverterA/D ConverterA/D Converter
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9.1 The Two-Stage CMOS OP AMP
C ti it CCompensation capacitance Cc(together with Cgd6) is Miller-multiplied by the gain of the second stage
Systematic output dc offset
)/()/( LWLW
Systematic output dc offset → can be eliminated by keeping
5
7
4
6
)/()/(2
)/()/(
LWLW
LWLW
⋅=
Figure 9.1 The basic two-stage CMOS op-amp configuration.
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9.1 The Two-Stage CMOS OP AMP
Input Common-Mode RangeTo Keep Q1 & Q2 in saturation
To Keep Q5 in saturation
tpOVtnSSICM VVVVV −++−≥ 3
15 SGOVDDICM
VVVV
VVVV
−−−=
−−≤
Input common-mode range
15 OVtpOVDD VVVV=
Input common mode range
513 OVOVtpDDICMtptnOVSS VVVVVVVVV −−−≤≤−++−
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9.1 The Two-Stage CMOS OP AMP
Output SwingTo keep Q6 & Q7 saturated,
We need to keep the magnitude of Vo
76 OVDDOOVSS VVVVV −≤≤+−
We need to keep the magnitude of Vovas low as possible
However, counteracted by the need to have high fT for Q6
fT is proportional to Vov (in Section 6.2.3)
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9.1 The Two-Stage CMOS OP AMP
Voltage Gain
Figure 9.2 Small-signal equivalent circuit for the op amp in Fig. 9.1.
)2/(2211
IIggG
Rin
=⋅
===
∞=
and,|| 442
2421
11211
VrV
rwhererrR
VVggG
AA
OVOVmmm
===
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2/ and
2/ ,|| 42421 I
rI
rwhererrR oooo
9.1 The Two-Stage CMOS OP AMP
Voltage Gain (cont)
Figure 9.2 Small-signal equivalent circuit for the op amp in Fig. 9.1.
6
662
2
OV
Dmm V
IgG ⋅==
6
7
7
77
6
66762
6
,||D
A
D
Ao
D
Aooo
OV
IV
IV
randIVrwhererrR ====
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676 DDD
9.1 The Two-Stage CMOS OP AMP
Voltage Gain (Cont.)
111 m RGA −= 222 m RGA −=
421
2)||( oom
V
rrg−= 7662
)||( oom
V
rrg−=
42
1
11
AA
OV
VV
V
+−=
76
6
11
AA
OV
VV
V
+−=
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42 AA VV 76 AA VV
9.1 The Two-Stage CMOS OP AMP
Voltage Gain (Cont.)
The overall dc voltage gain
)||()||( 2211
21
mm
v
rrgrrgRGRG
AAA
===
Output resistance of the op amp)||()||( 766421 oomoom rrgrrg=
|| rrR
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76 || ooo rrR =
9.1 The Two-Stage CMOS OP AMP
Frequency Response
Capacitance C1, C2
C C C C C C
&
1 2 2 4 4 6
2 6 7 7
gd db gd db gs
db db gd L
C C C C C C
C C C C C
= + + + +
= + + +
Pole & Zero (in Section 7.7.1)
: dominant pole: dominant pole11
2Pf
R G R C≅1
1 2 2
22
2
2
Pm C
mP
fR G R C
GfC
π
π≅
2
2
2
2m
Z
CGf
C
π
π≅
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2 CCπ
9.1 The Two-Stage CMOS OP AMP
Frequency Response
To guarantee stability, unity-gain frequency ft must be
lower than fp2 & fz, so that 20log|Av| crosses 0 db at its
-20db/dec decaying section20db/dec decaying section
1m ffGfAf
9.1 The Two-Stage CMOS OP AMP
Simplified Equivalent Circuit
Figure 9.3 An approximate high-frequency
equivalent circuit of the two-stage op amp.
This circuit applies for frequencies f >> fP1.
Based on the assumption that |A2| is large and a virtual ground appears at the input terminalappears at the input terminal
The second stage effectively acts as an integrator that is fed with the output current signal of the first stage : Gm1Vid
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9.1 The Two-Stage CMOS OP AMP
Phase Margin Excess Phase Shift
)(tan2
12
P
tP f
f−−=φ
)(tan 1z
tz
ffff−−=φ : right half plane zero
)(tan)(tan90 12
1
z
t
P
ttotal f
fff −− ++°=φ
180PM total−°= φ
Phase Margin
)(tan)(tan90 12
1
z
t
P
t
total
ff
ff −− −−°=
φ
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Figure 9.4 Typical frequency response of the two-stage op amp.
9.1 The Two-Stage CMOS OP AMP
Phase Margin
Problem: Additional phase lag by zero
Solution: Include R in series with CC. The transmission zero can be Cmoved to other less-harmful locations
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9.1 The Two-Stage CMOS OP AMP
Phase Margin
0V = 1
1
0
222 VG
R
VV
imi
o
=+
=By selecting . ,
1Z
2
∞== fG
Rm
1R
)1(
1
RCs
sCR
C
=
+
2
1
mGR >By selecting
fz is at a negative real-axis: the extra phase
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)(2
RG
Cm
C − adds to the phase margin
9.1 The Two-Stage CMOS OP AMP
Slew Rate
1V applied at the inputA large signal will exceed the voltage required to turn off one side of the pairg g g q pand switch the entire bias current I to the other side
tCItvo =)( CC
o )(
C
mt
OmmtOVOVt
C CGf
VIgGVVf
CISR
πωπ
2, since ,2 1
111 ======
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COVC CVC π21
9.1 The Two-Stage CMOS OP AMP
Example 9.1 ( ) ( )( )1 2 4 6 6 7
2 2 21 1v m o o m o oA g r r g r r
I IV V
=
( )( )
6
6
2
2 2 21 1 2 2 2
DA A
OV OV D
A
I IV VV I V I
VV
= × × × × ×
⎛ ⎞= ⎜ ⎟⎝ ⎠
v A
2
To obtain A =4000, given V =20V,4004000 0.316V
OV
OV
V
VV
⎝ ⎠
= ⇒ =OVV
1 2
' 2 21
To obtain the required (W/L) ratios of Q and Q ,1 1100 80 0.3162 2D p OV
W WI k VL L
⎛ ⎞ ⎛ ⎞= ⇒ = × ×⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠1 1
1 2
2 225 25 and 1 1
For Q3 and Q4
p L LW m W mL m L m
μ μμ μ
⎝ ⎠ ⎝ ⎠
⎛ ⎞ ⎛ ⎞∴ = =⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
2
3 3 4
For Q3 and Q41100 200 0.3162
W W WL L L
⎛ ⎞ ⎛ ⎞ ⎛ ⎞= × × ⇒ =⎜ ⎟ ⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠ ⎝ ⎠
2
101
1 50F Q 200 80 0 316
mm
W W m
μμμ
=
⎛ ⎞ ⎛ ⎞⎜ ⎟ ⎜ ⎟
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25
5 5
50For Q , 200 80 0.3162 1
W W mL L m
μμ
⎛ ⎞ ⎛ ⎞= × × ⇒ =⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
9.1 The Two-Stage CMOS OP AMP
Example 9.17
7 5
Since Q is required to conduct 500 A,1252.5
1W W mL L m
μμμ
⎛ ⎞ ⎛ ⎞= =⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠7 5
26
6
1For Q , 500 200 0.3162
50
WL
W
μ⎝ ⎠ ⎝ ⎠⎛ ⎞= × ×⎜ ⎟⎝ ⎠
⎛ ⎞
6
REF
50 1
Finally, let's select I =20 A, thus
W mL m
μμμ
⎛ ⎞⇒ =⎜ ⎟⎝ ⎠
8
0.1W WL L
⎛ ⎞ ⎛ ⎞=⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠5
51
mm
μμ
=
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9.1 The Two-Stage CMOS OP AMP
Example 9.13 | 5| | 1|
1.33 0.52
6 | 7|
The input resistance is practically infinite,
and the output resistance is
1 20 6 7
12
200.5
20
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9.1 The Two-Stage CMOS OP AMP
Example 9.1 P26
To determine f2 2 0.5 3 2 /DIG g mA V×= = = =2 6
32
2 122
3.2 /0.316
3.2 10 6372 2 0.8 10
m mOV
mP
G g mA VV
Gf MHzCπ π
−
−
= = = =
×⇒ ≅ = =
× ×
32
To move the transmission zero to s=1 1 316
3.2 10mR
G −
∞
= = = Ω×
oFor a phase margin of 75 , the phase shift due tothe ot
1
second pole at f=f , must be 15 , that is,
t 15 637 t 15 171o otf f MH− ⇒12
tan 15 637 tan15 171o ot tP
f f MHzf
= ⇒ = × =
11 1
2 100 where 0.63 /2 0.316V
mC m m
t
G AC G g mA Vf
μπ
×= = = =
3
6
6
0.63 10 0.62 171 10
2 2 171 10 0.316 340
t
C
t OV
f
C pF
SR f V V sπ
π π μ
−×⇒ = =
× ×= = × × × =
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t OV
9.2 The Folded-Cascode CMOS OP AMP
Q Q i t diff ti l iQ1, Q2: input differential pairQ3, Q4: cascode transistorsEach of Q1, Q2 is operating at aEach of Q1, Q2 is operating at abias current (I/2)The bias current of each of Q3,Q4 is (I I/2)Q4 is (IB – I/2)The cascode current mirror Q5to Q8: for high output resistance
Figure 9.8 Structure of the folded-cascode CMOS op amp.g p p
CL: the total capacitance at the output nodeThe load capacitance contributes to frequency compensation
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The load capacitance contributes to frequency compensation
9.2 The Folded-Cascode CMOS OP AMP
Input common-mode range and the output voltage
swing Assuming that Q9 and Q10 are operated at the edge of saturationp g
tnOVDDICM VVVV +−= 9max ||
tnOVOVSSICM
tnOVDDICM
VVVVVVVVV
+++−= 111min9max ||
SGOVDDBIAS VVVV −−= 4101 ||
Figure 9.9 A more complete circuit for the folded-cascode CMOS amplifier of Fig. 9.8. tnOVOVSSo
OVOVDDo
VVVVvVVVv+++−=
−−=
57min
410max ||||
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9.2 The Folded-Cascode CMOS OP AMP
Input common-mode range and the output voltage
swing
Figure 9.10 Small-signal equivalent circuit of the folded-
cascode CMOS amplifier. Note that this circuit is in effect
an operational transconductance amplifier (OTA)an operational transconductance amplifier (OTA).
)2/(2
1121
OVOVmmm V
IVIggG ====
)(||)]||)([(|| 8661024464 oomooomOOO rrgrrrgRRR ==
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)}(||)]||)({[( 866102441 oomooommOmV rrgrrrggRGA ⋅==
9.2 The Folded-Cascode CMOS OP AMP
Frequency response
OL
Om
id
O
RsCRG
VV
+=
1 OLid
1The dominant pole has a frequency fP
OLP RC
fπ2
1=
The unity-gain frequency ft
mGfRGfL
mPOmt C
fRGfπ2
==
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9.2 The Folded-Cascode CMOS OP AMP
Slew rate
When IB>I, the current that will flow into CL will be I4-I6 = IB-(IB-I) = I
I12 OVt
L
VfCISR π==
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9.2 The Folded-Cascode CMOS OP AMP
Example 9.2
22 2 20A DiD D V II I W⎛ ⎞⎜ ⎟ ' 2, , 0.25
A DiD Dm o
iOV D D OV
g rV I I L k V
⎛ ⎞= = = = =⎜ ⎟⎝ ⎠
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9.2 The Folded-Cascode CMOS OP AMP
Example 9.2 Note that for all transistors, 160V/V, 1.0Vm o GSg r V= =
11 1 9
1.25V 3V
m o GS
SS OV OV tn ICM DD OV tn
ICM
V V V V V V V VV
− + + + ≤ ≤ − +
⇒ − ≤ ≤
7 5 10 4
1.25V 2V
ICM
SS OV OV tn o DD OV OV
o
V V V V v V V Vv
− + + + ≤ ≤ − −
⇒ − ≤ ≤
( )( )4 4 4 2 10 16o
o m o o oR g r r r≅ = ( )0 200 80 9.1421 28
M
R g r r M
= Ω
≅ = Ω6 6 6 8
4 6
3 6
21.286.4
0 8 10 6 4 10 5120V/V
o m o o
o o o
R g r r MR R R M
A G R −
≅ = Ω
∴ = = Ω
∴ × × ×
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0.8 10 6.4 10 5120V/Vv m oA G R∴ = = × × × =
9.2 The Folded-Cascode CMOS OP AMP
Example 9.23
12
0.8 10 25.52 2 5 10
mt m o P
L
Gf G R f MHzCπ π
−
−
×= = = =
× ×2 2 5 1025.5 5
5120
L
tp
Cf MHzf kHzA
π π
= = =
6
12
5120
200 10 40V μs5 10
vA
ISRC
−
−
×= = =
×5 10Finally, to determine the power dissipation we notethat the total current is
LC ×
500 A=0 5mA and the totalμthat the total current is 500 A 0.5mA, and the totalsupply voltage is 5V, thus
5 0 5 2 5mWP
μ
= × =
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5 0.5 2.5mWDP = × =
9.2 The Folded-Cascode CMOS OP AMP
Increasing the input common-mode range:Rail-to-rail input operation
An NMOS and a PMOS differential pair placed in parallel would provide an inputstage with a common-mode range thatexceeds the power supply voltage in bothdirections.
Rail-to-rail input operationEach of the current increments indicated isequal to Gm(Vid/2).
This assumes that both differential pairs
OmVidOmO RGAVRGV 2,2 == Figure 9.11 A folded-cascode op amp that employs twoparallel complementary input stages to achieve rail-to-rail
input common-mode operation. Note that the two “+”
t i l t d t th d th t “ ” t i l
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will be operating simultaneously. terminals are connected together and the two “–” terminalsare connected together.
9.2 The Folded-Cascode CMOS OP AMP
Increasing the output voltage range:The wide-swing current mirror
2t OVV V+ 2 OVVt OV OV
Figure 9.12 (a) Cascode current mirror with the voltages at all nodes indicated. Note that the minimum
voltage allowed at the output is V + V (b) A modification of the cascode mirror that results in the reduction
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voltage allowed at the output is Vt + VOV. (b) A modification of the cascode mirror that results in the reduction
of the minimum output voltage to VOV. This is the wide-swing current mirror.
9.3 The 741 OP-AMP Circuit
The IC design philosophyM tl t i tMostly transistorsRelatively few resistorsOnly one capacitorThis philosophy is dictated by the economics (silicon area, ease of fabrication, quality of realizable components) of the fabrication of active and passive components in IC form.
Two power supplies (+VCC and –VEE)Normally V V 15VNormally, VCC=VEE=15VBut the circuit also operates satisfactorily with ±5V.
With a relatively large circuit, the first step in the analysis is the identification of its recognizable parts and their functions.
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9.3 The 741 OP-AMP Circuit
Figure 9.13 The 741 op-amp circuit. Q11, Q12, and R5 generate a reference bias current, IREF. Q10, Q9, and Q8 bias
the input stage, which is composed of Q1 to Q7. The second gain stage is composed of Q16 and Q17 with Q13B acting
as active load. The class AB output stage is formed by Q14 and Q20 with biasing devices Q13A, Q18, and Q19, and an
i t b ff Q T i t Q Q Q d Q t t t th lifi i t t t h t i it d
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input buffer Q23. Transistors Q15, Q21, Q24, and Q22 serve to protect the amplifier against output short circuits and
are normally cut off.
9.3 The 741 OP-AMP Circuit
Bias CircuitQ Q R : I (reference bias current)Q11, Q12, R5: IREF (reference bias current)Q11, Q10, R4: Widlar current sourceQ8, Q9: Current mirror, Q12,Q13A, Q13B : Current mirrorQ18 Q19: 2VBE drops between Q14 and Q20Q18, Q19: 2VBE drops between Q14 and Q20
Short-Circuit Protection CircuitryR6, R7, Q15, Q21, Q24, R11: normally off
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R6, R7, Q15, Q21, Q24, R11: normally off
9.3 The 741 OP-AMP Circuit
The input stage (Differential stage)p g ( g )Q1~Q7 with biasing performed by Q8~Q10 Q1, Q2 : Emitter follower, Rin high Q3, Q4 : Common base amp, Level shifter, Q1,Q2 protection
(npn: Breakdown 7V, pnp: Breakdown 50V)Q5, Q6, Q7, R1, R2, R3 :
Load circuit of input stageCurrent mirror (High resistance)
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Current mirror (High resistance),Differential >> Single ended (Q6 Collector)
9.3 The 741 OP-AMP Circuit
The second stage (Single ended high gain stage)Intermediate stage: Q16, Q17, Q13B, R8, R9Q16 : Emitter follower(High Rin), Q17 : Common emitter ampQ16 : Emitter follower(High Rin), Q17 : Common emitter ampQ13B : Active load (High gain), CC: Frequency compensationDominant pole : 4Hz, unity gain bandwidth : 1MHz
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9.3 The 741 OP-AMP Circuit
The output stage (Buffering stage)Class AB output stage, Low Rout, Large load currentQ14, Q20 : Complementary pairQ14, Q20 : Complementary pairQ18, Q19 are fed by Q13A and bias Q14, Q20Q23 : Emitter follower (minimizing loading effect on second stage)
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9.3 The 741 OP-AMP Circuit
The output stage (buffering stage)Class AB output stage is utilized in 741 Op-Amp
Figure 9.14 (a) The emitter follower is a class A output stage. (b) Class B output stage. (c) The output of
a class B output stage fed with an input sinusoid. Observe the crossover distortion. (d) Class AB output stage.
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9.3 The 741 OP-AMP Circuit
Device parameters
1410 A, 200, 125 VS AI Vβ−= = =
1410 A, 50, 50 VS AI Vβ−= = =
For NPNFor PNP
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14 140.25 10 A, 0.75 10 ASA SBI I− −= × = ×For Multi-collector PNP
9.4 DC Analysis of the 741
Reference bias current
12 1111 12
5
( ) 0.73 ( 15 , 0.7 )CC EB BE EEREF CC EE BE EBV V V VI mA V V V V V V
R− − − −
= = = = = ≅5
Input-stage bias
Widlar Current Source
11 10 10 4
10 4 10 11 10ln ( ) 19
BE BE C
REFT C S S C
V V I RIV I R I I I AI
μ
− =
= = ⇒ =10CI
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Figure 9.15 The Widlar current source.
9.4 DC Analysis of the 741
From symmetryIf the npn β is high
21 CC II =III ≅If the npn β is high
Q3 and Q4 base current :
III BB ≅= 43
PP
IIββ
≅+1
Using the result in Eq.(6.21)Q8 and Q9 current mirror :
PC
IIβ/21
29 +=
Node X : if
Pβ/21+
uAIIIIIuAII
CCCC
CP
5.9192,1
4321
10
==≅==∴=≅>>β
Q1 through Q4,Q8 and Q9 : negative feedback loop
Figure 9.16 The dc analysis of the 741 input stage.
To stabilize 2/10CII ≅
↓↓
⇒↑⇒↑⇒↑ III CC)(/98
β
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↓⇒↓ IconstII CP )(/2 10β
9.4 DC Analysis of the 741
If neglect the base current of Q16,Q7
Q7 bias current
III CC ≅= 56
IRVI2
uAVIVV
RIRVIII BE
NEC
5175.9l25l
2
3
2677
++=≅
β
uAI
mA
mVI
VV
C
STBE
5.10
51710
ln25ln
7
146
=⇒
=== −
Input Bias and Offset Currents
Figure 9.17 The dc analysis of the 741 input stage, continued.
p1 2 9.5 / 200 47.5
2B B
BN
I I II nAβ
+= = = =
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1 2input offset current OS B BI I I= −
9.4 DC Analysis of the 741
Input offset voltageVOS : differential input voltage to reduce the output current to zero
Input common-mode rangeInput common mode rangeInput stage remains in the linear active modeThe upper end by saturation of Q1, Q2Th l d b t ti f Q Q
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The lower end by saturation of Q3, Q4
9.4 DC Analysis of the 741
Second-stage bias (Fig. 9.13)Second stage bias (Fig. 9.13)
13 17
17
0.75 (by Emitter Area Ratio)=550 A=
l 618
C B REF C
C
I I IIQ
μ=
1717 17 17 17 8 17
1716 16 16 17
ln 618 ,
16.2
CBE T B E BE
S
BC E B
IQ V V mV V I R VI
VQ I I I Aμ
⇒ = = = +
⇒ ≅ = + =
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16 16 16 179
16.2C E BQ I I I ARμ⇒ ≅ +
9.4 DC Analysis of the 741
If neglect the base current of Q14,Q20Output-stage bias
If VBE18 is 0.6V,
uAIII REFEC 18025.02323 =≅≅
60 uAk
IR 15406.0
10 ==
IIuAI CE 16515180 1818 ≅=−=
uAIQin
mVI
IVV
B
S
CTBE
8.0200/165,
588ln
1818
1818
==
≅=⇒
mVI
IVVQin
uAII
S
CTBE
EC
530ln,
8.15
191919
1919
==
=≅⇒
Figure 9.18 The 741 output stage without the IIV
IIVVAlso
VVVV
S
CT
S
CTBB
BEBEBB
lnln,
118.1530588
20
20
14
14
1918
+=
=+=+=
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short-circuit protection devices. uAIIII
CC
SS
15420142014
==⇒
9.5 Small-Signal Analysis of the 741 Input Stage
The Input Stage
dDifferential signal vig iFour emitter resistances connectedin series 4·re
Input resistance
kΩ 2.639.5uA25mV
IVr ,
4rvi Te
e
ie ====
Input resistance
MΩ1.2r)1(β4R eNid =⋅+⋅=
Figure 9.19 Small-signal analysis of the 741 input stage.
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9.5 Small-Signal Analysis of the 741 Input Stage
7 : neglectedbi 7 : neglectedbi
5c ei iα=
5 6 5 6, identical : c cQ Q i i=5 6 5 6, c cQ Q
output node : 2o ei iα=
Figure 9.20 The load circuit of the input stage fed by the two
complementary current signals generated by Q1 through Q4 in
Fig. 9.19. Circled numbers indicate the order of the analysis steps.
The transconductance of the input stage
)V/A265/1G1k632(i2iG eo ≅Ωα⋅α⋅
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)V/mA26.5/1G,1,k63.2r(r2ir4v
G 1meeee
e
i
o1m =≅αΩ==⋅⋅
=≡
9.5 Small-Signal Analysis of the 741 Input Stage
Output resistance(current source of Q44) || (output resistance of Q) || (output resistance of Q66))
50V V
Virtual ground 4
50 5.269.5
[1 ( // )] 10 5
Ao
V Vr MI A
R r g r r Mμ
= = = Ω
= + = Ωground 4 [1 ( // )] 10.5o o m eR r g r r Mπ+ Ω
0bi ≅
6 2[1 ( // )] 18.2b
o o mR r g R r Mπ= + = Ω
Figure 9.21 Simplified circuits for finding the two
components of the output resistance Ro1 of the first
stage
1 4 6 // 6.7o o oR R R M⇒ = = Ω
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stage.
9.5 Small-Signal Analysis of the 741 Input Stage
Small signal equivalent circuit of input stage
Figure 9.22 Small-signal equivalent circuit for the input stage of the 741 op amp.
2.1idR M= Ω
1
1
1/ 5.26 /6.7
m
o
G mA VR M
== Ω
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9.5 Small-Signal Analysis of the 741 Input Stage
Example 9.3RΔ
1 2
6
, where 0.02
current in Q I decreasing
RR R R R RRΔ
= = + Δ =
⇒ Δ
5 6
5 6
3
( )( )( )
BE BE
BE BE e
V IR V I I R RV V I R I R R Ir
I R
+ = + −Δ + Δ
− = Δ −Δ + Δ ≅ Δ
Δ Δ 3 5.5 10e
I RI R R r
−Δ Δ∴ = = ×+ Δ +
T d t hIΔ
3
To reduce to zero, we have to apply an input voltage
5.5 10 0 3
OS
IV
I IV mV−
Δ
Δ ×≅
1 1
0.3OSm m
V mVG G
= = ≅
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9.5 Small-Signal Analysis of the 741 Input Stage
The second stage
++++= RrRrR eei )])(1(||)[1( 81717916162 ββ
Input resistance by inspection
Ω≅ MRi 42Transconductance
Figure 9.24 The 741 second stage prepared for
2
13
- : short-circuit output current to input voltage( 0)
m
c B
Gi
i i G=
⇒Figure 9.24 The 741 second stage prepared forsmall-signal analysis.
17 2 2
17 9 1717 17 2
17 8 9 17 16
( // ),
( // )
o c m i
b ic b i
e i e
i i G vv R Ri v v
r R R R rα⇒ = =
= =+ +
Figure 9.25 Small-signal equivalent circuit
17 8 9 17 16
17 17 17 8
172
( )( 1)( )
6.5 /
e i e
i e
cm
R r RiG mA V
β= + +
∴ ≡ =
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g g q
model of the second stage.2
2m
iv
9.5 Small-Signal Analysis of the 741 Input Stage
The second stage
2- : output resistance of second stageoR
Output resistance
2 13 17
13B
( // )- Q base and emitter grouned
=90 9k
o o B oR R R
R r
=
= Ω
Figure 9.26 Definition of Ro17.
13 13
17 17 17 8 17
16 9 17
=90.9k- [1 ( // )] 787 ( // )
o B o B
o o m
e
R rR r g R r kr R r
π
π
= Ω= + = Ω
9.5 Small-Signal Analysis of the 741 Input Stage
The output stageOutput voltage limits- when Q13A is saturated
VVV
when Q is saturated
)VbelowV1(VVVv
CC
14BECEsatCCmaxo −−=
- when Q17 is saturated
)VaboveV51(VVVVv
EE
20EB23EBCEsatEEmino
−+++−=
)VaboveV5.1( EE
Figure 9.28 The 741 output stage.
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9.5 Small-Signal Analysis of the 741 Input Stage
The output stageO i it t t ltOpen-circuit output voltageof the second stage
2222 iomo vRGv −=
Figure 9 29 Model for the 741 output stage This model
Second stage voltage gain
2222 iomo
33 ii RGvAFigure 9.29 Model for the 741 output stage. This modelis based on the amplifier equivalent circuit presented in
Table 5.5 as “Equivalent Circuit C.”23
322
2
32
oin
inom
i
i
RRRRG
vvA
+−=≡
Input resistance
RfR Lin )(3 =
VVAMkRkRrQofemittertheinnceresistatotal
negligibleQQofRkrkRrRactiveQassume
bAo
AoLb
/515737474||:
,280,100,
201323
19181320232020
ΩΩ×≅∴Ω=⇒
−Ω≅Ω≅+=
β
βπ
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VVAMkRin /515,7.374 2233 −=Ω=Ω×≅∴ β
9.5 Small-Signal Analysis of the 741 Input Stage
The output stageOpen-circuit overall voltage gain of the output stage
1vGR o ≅=→∞= 1v
GRLR2o
3voL ≅=→∞=∞=
Output resistancep
20 14 20 14
20
( ,Q on/Q off or Q off/Q on): negative Q
o LR f Iv active
=⇒ 20
223 23 13
23
: negative Q
1.73
9.5 Small-Signal Analysis of the 741 Input Stage
The output stage
Output short-circuit protection
- Output terminal Short-circuited ⇒ Large current ⇒ Burnout of IC
- Short-Circuit Protection⇒ limit the current in the output TR
- In Fig 9.13
limit the maximum current that OP Amp
14 14 15 6 14
15 15 14
If > 20mA(Q ), > 540
Turn on Q , E BE E
C B
I V R I mV
I I
=
⇒ ↑ ⇒ ↓
limit the maximum current that OP Amp can source to about 20mA
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9.6 Gain, frequency response, and slew rate f th 741of the 741
Small-signal gain
Figure 9.31 Cascading the small-signal equivalent circuits of the individual stages for the evaluation of
the overall voltage gain.
2 2
2 2
o i o o
i i i o
v v v vv v v v=
1 1 2 2 2 3 ( // )( )
476.1 ( 526.5) 0.97 243,147 V/V
Lm o o m o vo
L o
RG R R G R GR R
= − −+
= − × − × =
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476.1 ( 526.5) 0.97 243,147 V/V 107.7 dB=
9.6 Gain, frequency response, and slew ratef th 741of the 741
Frequency responseUsing Miller’s theorem in second stage CC, the effective capacitance
2(1 ) 30 (1 515) 15480in CC C A p pF= + = + =A2 : the second-stage gain
This capacitance is quite large, we neglect all other C between Q16 and signal ground
The total R between this node and ground
Th d i t l
1 2( ) (6.7 4 ) 2.5t O iR R R M M M= = Ω Ω = Ω
The dominant pole1 4.1
2p in tf Hz
C Rπ= =
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in t
9.6 Gain, frequency response, and slew ratef th 741of the 741
Frequency response
The unity-gain bandwidth ft
The phase shift at ft is -90°
0 3 243147 4.1 1t dBf A f MHz= = × ≅
p t
The phase margin is 90°
This phase margin is sufficient toprovide stable operation for closed
Figure 9.32 Bode plot for the 741 gain, neglecting
nondominant poles.
loop amp with any value of βp
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9.6 Gain, frequency response, and slew ratef th 741of the 741
The high-gain second stage (Cc)
Figure 9.33 A simple model for the 741 based
The second stage gain is large (The output R of the input stage and the input
on modeling the second stage as an integrator.
The second stage gain is large (The output R of the input stage and the inputR of the second stage have been omitted)
1( )( )( )
o mV s GA sV C
≡ = 1( ) mGA jwj C
=
The magnitude of gain becomes unity at ω=ωt
( )i CV s sC Cj Cω
1mGω = 1tf MHzω= ≅ 1( 1/ 5.26 / 30 )CG mA V and C pF= =
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tCC
ω 12t
f MHzπ≅ 1( 1/ 5.26 / 30 )m CG mA V and C pF
9.6 Gain, frequency response, and slew ratef th 741of the 741
Slew rateThe large input voltage causes the input stage to be overdriven, and its small-signal model no longer applies
Figure 9.34 A unity-gain follower with a large step
Figure 9.35 Model for the 741 op amp when a large
positive differential signal is applied.g y g g p
input. Since the output voltage cannot change
instantaneously, a large differential voltage appears
between the op-amp input terminals.
2( )C
o cC C
i dt Iv t v tC C
= = =∫
1 3 2 4
0 , 10, ,
t V V VQ Q on and Q Q off
++ −> − =
⇒
C C
2 2(9.5 ) 0.63 /30C
ISR V sC p
μ μ= = =1,
mt
C
GC
ω =
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3 6 2c cI I I⇒ = =
9.6 Gain, frequency response, and slew ratef th 741of the 741
Relationship between ft and SR
re: Emitter resistance of each of Q1 through Q4112
4m eG
r=
1, 2T
e mV Ir GI V
= =1 2e m TI V
I SRh f2 4t C T T
thereforeC V V
ω = =
3 63 64 4 25 10 2 10 0.63 / ( 741)T tSR V V s forω π μ−= = × × × × =
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9.7 Data Converters – An Introduction
Digital processing of signals
Convert the signal from analog to digital form and then use digital ICs to perform digital signal processingICs to perform digital signal processing
The digital signal processor can perform a variety of arithmetic and logic operations that implement a filtering algorithm
Analog to digital converter (ADC)Analog to digital converter (ADC)Accept an analog sample and produce an N-bit digital word
Digital to analog converter (DAC)Accept an N-bit digital word and produce an analog sample
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9.7 Data Converters – An Introduction
Sampling of analog signalsSample-and-hold
Figure 9.36 The process of periodically sampling an analog signal. (a) Sample-and-hold (S/H) circuit.
The switch closes for a small part (t seconds) of every clock period (T). (b) Input signal waveform.
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The switch closes for a small part (t seconds) of every clock period (T). (b) Input signal waveform.
(c) Sampling signal (control signal for the switch). (d) Output signal (to be fed to A/D converter).
9.7 Data Converters – An Introduction
Signal quantizationConsider: 0~10VAssuming that we wish to convert this signal to digital form and thatthe required output is a 4 bit digital signalthe required output is a 4-bit digital signal
0V 0000 V 2102/3V 00016V 100110V 1111
VVresolution32
1510
==
10V 1111
Example: the case of a 6.2V analog level (between 18/3 and 20/3)18/3 (6V)18/3 (6V)
Quantization errorUse of more bits reduces quantization error
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9.7 Data Converters – An Introduction
The A/D and D/A converters as functional blocks
Figure 9.37 The A/D and D/A converters as circuit blocks.
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9.7 Data Converters – An Introduction
The A/D and D/A converters as functional blocks
Figure 9.38 The analog samples at the output of a D/A converter are usually fed to a sample-
and-hold circuit to obtain the staircase waveform shown. This waveform can then be filteredand hold circuit to obtain the staircase waveform shown. This waveform can then be filtered
to obtain the smooth waveform, shown in color. The time delay usually introduced by the filter
is not shown.
The analog samples at the output of a D/A converter are usually fed to a sample-and-hold circuit to obtain the staircase waveformThis waveform can then be smoothed by a low-pass filter, giving rise to the
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y p , g gsmooth curve in color in Fig.9.38
9.8 D/A Converter Circuits
Basic circuit using binary-weighted resistors
Figure 9.39 An N-bit D/A converter using a binary-weighted resistive ladder network.
bb b
bVbVbVi REFREFREF +⋅⋅⋅++=
1 21 22 2 2
NN
bb bN bit digital word D− = + + ⋅⋅⋅+
DR
V22b
2b
2b
RV2
bR2
bR2
bR
i
REFNN
221REF
N1N21o
=⎟⎠⎞
⎜⎝⎛ +⋅⋅⋅++=
+++= −
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DVRiv REFfoo −=−=⎠⎝
9.8 D/A Converter Circuits
Basic circuit using binary-weighted resistors
The accuracy of the DAC depends on- The accuracy of Vref- The precision of the binary-weighted resistors- The perfection of the switches
Disadvantages- For a large number of bits (N>4) the spread between the smallest and
largest R becomes quite large.hi i li iffi l i i i i i i l- This implies difficulties in maintaining accuracy in R values.
A more convenient scheme exists utilizing a resistive network called the R-2Rgladder
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9.8 D/A Converter Circuits
R-2R Ladders
VIVI
IIII
REFREF
NN
⎟⎞
⎜⎛ ⋅⋅⋅==
=⋅⋅⋅=== −
,,
242
21
1321
bR
VbR
VbR
Vi
RI
RI
NNREFREFREF
o +⋅⋅⋅++=
⎟⎠
⎜⎝
242
,4
,2
21
21
DR
VbbbR
V REFNNREF =⎟⎠⎞
⎜⎝⎛ +⋅⋅⋅++=
222 221
Figure 9.40 The basic circuit configuration of a DAC
utilizing an R-2R ladder network.DVRiv REFfoo −=−=
Because of the small spread in R values, this network is usually preferred to thebinary-weighted scheme discussed earlier, especially for N>4
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9.8 D/A Converter Circuits
A practical circuit implementation
( )2N
NN BE
IV V Rα
⎛ ⎞= + ⎜ ⎟⎝ ⎠
12 N
N NIV V Rα−
⎛ ⎞= +⎜ ⎟⎝ ⎠
1
14 2N N
N NBE BE
I IV R V Rα α−
−⎛ ⎞= + = +⎜ ⎟⎝ ⎠
1 12
N NBE BE N Nif V V I I
− −= ⇒ =
12 4 2NI I I I−
Figure 9.41 A practical circuit implementation of a DAC utilizing
11 2 32 4 2
NNI I I I∴ = = = ⋅⋅⋅ =
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an R-2R ladder network.
9.8 D/A Converter Circuits
Current switches Each of the single-pole double-throw switches in the DAC circuit of Fig.9.41 gcan be implemented by a circuit as that shown in Fig.9.42 for switch Sm
Im: the current flowing in the collector of the mth-bit transistor
Qmr: the reference transistor
If bm>VBIAS Qms turn on, Qmr turn off Im through QmsFigure 9.42 Circuit implementation of switch Sm
in the DAC of Fig. 9.41. In a BiCMOS technology,If bm< VBIAS Qms turn off, Qmr turn onIm through Qmr
in the DAC of Fig. 9.41. In a BiCMOS technology,
Qms and Qmr can be implemented using MOSFETs,
thus avoiding the inaccuracy caused by the base
current of BJTs.
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9.9 A/D Converter Circuits
The feedback-type converter
The comparator circuit provides an output that assumes one of two distinctvalues
Figure 9.43 A simple feedback-type A/D converter.
valuesAn up-down counter is simply a counter that can count either up or downdepending on the binary level applied at its up-down control terminal
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9.9 A/D Converter Circuits
The dual-slope A/D converter
Figure 9.44 The dual-slope A/D conversion method. Note that vA is assumed to be negative.
Close S2 (discharge C, v1=0) Open S2 and switch S1 to vA (I=vA/R flow away from the integrator )
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V1 rises linearly with a slope of I/C=vA/RC, as indicated in Fig. (b)
9.9 A/D Converter Circuits
The dual-slope A/D converterReference to Fig. 9.44(b)
peak AV v=
At the end of this phase, the counter ist t
1T RC=
reset to zeroIn phase II, v1 decreases linearly with aslope of (Vref/RC)When v1 reaches zero, the control logicstops the counterThus the content of the counter, n, atpeak refV V Av⎛ ⎞⎜ ⎟ the end of the conversion process is thedigital equivalent of vA
2
peak ref
T RC=
2 1A
ref
vT TV⎛ ⎞
= ⎜ ⎟⎜ ⎟⎝ ⎠
Avn n⎛ ⎞
= ⎜ ⎟⎜ ⎟
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refref
n nV
= ⎜ ⎟⎜ ⎟⎝ ⎠
9.9 A/D Converter Circuits
The parallel or flash converter
Figure 9.45 Parallel, simultaneous, or flash A/D conversion.
Very fastA rather complex circuit
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9.9 A/D Converter Circuits
The feedback-type converterSuitable for CMOS implementation
Figure 9.46 Charge-redistribution A/D converter suitable for CMOS implementation:
(a) sample phase
(a) sample phase: SB closed, v0=0, sA=vA, Q=-2CvA
(a) sample phase
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9.9 A/D Converter Circuits
The feedback-type converter
(b) hold phase: SB open, Si to GND, SA to Vref, vo=-vA
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9.9 A/D Converter Circuits
The feedback-type converter
(c) charge-redistribution phase(c) charge redistribution phase
S1 to Vref : vo=-vA+Vref/2,- If vA>Vref/2, voVref/2+Vref/4, vo