Chapter 9: 68HC11 Serial Communication Interface

H. Huang Transparency No.9-1

The 68HC11 Microcontroller

Chapter 9: 68HC11 Serial Communication Interface


Han-Way Huang

Minnesota State University, Mankato



Asynchronous Serial Data Communication

- Often used for data communication between a DTE and a DCE with or without a modem.- DTE stands for data terminal equipment and can be either a computer or a terminal. - DCE stands for data communication equipment. A modem is a DCE.- A basic data communication link is shown in Figure 9.1.

- there are three kinds of data communication links:

1. simplex link2. half-duplex link3. full-duplex link

DTE DTEDCE DCE

Computeror terminal

Computeror terminal

Modem Modem

Communication link

Figure 9.1 A data communication system



Types of communication links configuration

The RS232 Standard

- was the most widely used physical level interface for data communication- specifies 25 interchange circuits for DTE/DCE use- was established in 1960 by Electronics Industry Association (EIA)- was revised into RS232C in 1969- was revised into RS232D in 1987- was revised to RS232E in 1992- there are four aspects: electrical, functional, procedural, and mechanical

(a) Point-to-point Station Station

Master

Slave 1 Slave 2 Slave n......

(b) Multi-drop

Figure 9.2 Point-to-point and multi-drop communication links



The RS232D Electrical Specifications

- the interface is rated at a signal rate of < 20 kbps- the signal can transfer correctly within 15 meters- the maximum driver output voltage (with circuit open) is -25 V to +25 V- the minimum driver output voltage (loaded output) is -25 V to -5 V and +5 V

to +25 V- the minimum driver output resistance when power is off is 300 - the maximum driver output current (short circuit) is 500 mA- the maximum driver output slew rate is 30 V/s- the receiver input resistance is 3-7 K- the receiver input voltage range is -25 V to +25 V- the receiver output is high when input is open circuit- a voltage more negative than -3 V at the receiver input is interpreted as a logic 1- a voltage more positive than +3 V at the receiver input is interpreted as a logic 0



The EIA-232E Functional Specifications

Table 9.1 EIA-232-E signals

Pin No. Circuit Description

1 - Shield2 BA Transmitted data3 BB Received data4 CA/CJ Request to send/ready for receiving 1

5 CB Clear to send6 CC DCE ready7 AB Signal common8 CF Received line signal detector9 - (reserved for testing)10 - (reserved for testing)11 - unassigned 3

12 SCF/CI Secondary received line signal detection/data rate selector (DCE source) 2

13 SCB Secondary clear to send14 SBA Secondary transmitted data15 DB Transmitter signal element timing (DCE source)16 SBB Secondary received data17 DD Receiver signal element timing18 LL Local loopback19 SCA Secondary request to send20 CD DTE ready21 RL/CG Remote loopback/signal quality detector22 CE Ring indicator23 CH/CI Data signal rate selector (DTE/DCE source) 2

24 DA Transmitter signal element timing (DTE source)25 TM Test mode

1. When hardware flow control is required, circuit CA may take on the functionality of circuit CJ. This is one change from the former EIA-232.2. For designs using interchange circuit SCF, interchange circuits CH and CI are assigned to pin 23. If SCF is not used, CI is assigned to pin 12.3. Pin 11 is unassigned. It will not be assigned in future versions of EIA-232. However, in international standard ISO 2110, this pin is assigned to select transmit frequency.



EIA-232E Mechanical Specification

- Specifies a 25-bit connector- Specifies exact dimensions of each pin.

Signal Name

Protective groundTransmitted dataReceived dataRequest to sendClear to sendData set readySignal ground

Carrier detectReservedReserved

Secondary carrier detect

Secondary clear to send

Secondary transmitted dataTransmit clock

Secondary received dataReceiver clock

UnassignedSecondary request to send

Data terminal ready

Signal quality detectRing indicatorData rate select

Transmit clockUnassigned

Signal Name SignalDirection

Both

to DCE

to DTEto DCEto DTEto DTEBoth

to DTE

to DTEto DTE

Both

to DCEto DTE

SignalDirection

to DTEto DTE

to DCE

to DCE

to DTEto DTE

to DCE

Figure 9.3 EIA-232-E connector and pin assignment

123456789

10111213

141516171819202122232425

Unassigned



EIA-232E Procedural Specification

- define the sequence of events that occurs during data transmission- the procedure is easier to understand by examples

Case 1. Two DTEs connected via a point-to-point link using a modem.

EIA-232 signals involved:

- signal ground (GND)- transmitted data (Tx)- received data (Rx)- request to send (RTS)- clear to send (CTS)- data set ready (DSR)- data carrier detect (DCD)

TxRx

DCD

CTS

DSRGND

RTS

Tx

RxDCD

CTS

DSRGND

RTS

Computer(DTE)

Modem(DCE)

TxRx

DCDCTS

DSRGND

RTS

TxRxDCD

CTS

DSR

GND

RTS

Direct link

Computer(DTE)

Modem(DCE)

The following acronyms are used in Figure 9.4:Tx: transmit data CTS: clear to sendRx: receive data RTS: request to sendDCD: data carrier detect DSR: data set ready

Figure 9.4 Point-to-point asynchronous connection



Sequence of events occurred during data transmission over dedicated link

Local Remote

1. DCE asserts DSR

2. DTE asserts RTS

3. DCE asserts CTS

4. DTE starts to send data (to local DCE)

5. DCE sends out a carrier and then the modulated data 6. DCE asserts DCD

7. DTE waits for arrival of data

8. DCE sends out demodulated received data

9. DEC receives demodulated data

Tim

e



Case 2. Two DTEs exchange data through a public phone line

RS232 signals involved:

- signal ground (GND)- transmitted data (Tx)- received data (Rx)- request to send (RTS)- clear to send (CTS)- data set ready (DSR)- data carrier detect (DCD)- data terminal ready (DTR)- ring indicator (RING)

- The signal DTR is used by the DTE to indicate its intention to make a call or accept a call .

- The signal RING is used by the DCE to indicate that there is an incoming call.

TxRx

RINGDCDCTSRTSDSRDTRGND

TxRxRINGDCDCTSRTSDSRDTRGND

TxRx

RINGDCDCTSRTSDSRDTRGND

TxRxRINGDCDCTSRTSDSRDTRGND

Phone line

Computer(DTE)

Computer(DTE)

Modem(DEC)

Modem(DEC)

Figure 9.5 Asynchronous connection over public phone line



Sequence of events occur during data transmission over public phone line

Local Remote (receiving side)

time

Connection establishment phase

(transmission side)

1. DTE asserts DTR

2. DCE dials the phone number 3. DCE detects the ring

and asserts RING4. DTE asserts DTR to accept the call

5. DCE sends out a carrier and asserts DSR6. DCE asserts DSR

and DCD and also sends out a carrier for full duplex operation

7. DCE asserts DCD (full duplex operation)



Local Remote (receiving side)(transmission side)

Sequence of events occur during data transmission (continued)

time

Data transmissionphase

1. DTE asserts RTS

2. DCE asserts CTS

3. DTE sends out data to DCE

4. DCE modulates data and sends it out 5. DCE demodulates

data and forwards the data to DTE 6. DTE receives

data

Disconnectionphase

1. DTE drops RTS

2. DCE drops CTS and drops the carrier

3. DCE deasserts DCD & DSR

4. DTE deasserts DTR



Data format for asynchronous data communication

- data is transmitted character by character bit-serially- a character consists of

1. one start bit (0), 2. 7 to 8 data bits,

3. an optional parity bit, 4. one, or one and a half, or two stop bits (1)5. least significant bit is transmitted first6. most significant bit is transmitted last

Startbit

0 1 2 3 4 5 6 7 Stopbit 1

Stopbit 2

Figure 9.6 The format of a character



Example 9.1 The letter A is to be transmitted. What is the data output transmitted out fromthe computer? The data format for transmission is 8 data bits, no parity, and one stop bit.Solution:The ASCII code of letter A is $41 or %01000001. This code will be followed by a stopbit. The output from the DTE should be:

Example 9.2 How long does it take to transmit one character at the speed of 9600 baud? Eachcharacter is transmitted using a format with seven data bits, even parity, and two stop bits.Solution:- Each character consists 11 bits.- Each bit requires 104 s (= 1 sec ÷ 9600).- One character requires 11 × 104 s = 1.145 ms to transmit.

0 0 0 0 0 01 1 10

(a) output waveform on microcontroller interface

0 1 0 0 0 0 0 1 10

(b) output waveform on EIA-232-E interface

Figure 9.7 Data format for letter A



Data transmission errors

- framing error: a character is not properly framed by a stop bit- receiver overrun: one or more characters received but not read by the CPU- parity error: odd number of bits change value

Null Modem connection

Figure 9.8 Null Modem connection

Pin Circuit name DTE DTE

2220865432

24177

Ring indicatorData terminal readyData carrier detectData set readyClear to sendRequest to sendReceived dataTransmitted dataTransmitter timingReceiver timingSignal ground

CECDCFCCCBCABBBADADDAB

CECDCFCCCBCABBBADADDAB



The 68HC11 SCI Subsystem

- Signal pins: TxD (PD1) and RxD (PD0)

- Data formats

1. one start bit2. 8 or 9 data bits3. one stop bit

- Wake up feature

1. address mark wakeup: the character whose msb is a 1 is an address mark2. idle line wakeup: the RxD pin is idle (high) for at least one complete character time

Wakeup feature can reduce the data communication overhead in a multidrop environment.

- Start bit detection

1. the SCI uses a clock 16 times the bit rate to detect the arrival of a start bit and data bit2. the RxD pin must be high for at least three sampling clock cycles followed by a low

voltage3. the majority of bits 3, 5, and 7 being a low is considered as the arrival of a start bit



- Receive process of a character

1. the receiver detects the start bit2. the receiver shifts in 8 (or 9) data bits3. the receiver shifts in the stop bit4. when a correct stop bit is detected, the data bits will be loaded into the receive data

register5. the receiver sets the RDRF flag in the SCSR register and may optionally generate

an interrupt to the CPU

- SCI receive errors

1. framing error (FE)2. receiver overrun (OR)3. noise error (NE)

- The transmitting process of a character

1. CPU writes the character into the transmit data register after the transmitter is enabled2. the transmitter adds the start bit and a stop bit to the data character presented by the CPU3. the transmitter shifts out the bit stream4. the transmitter sets the TDRE status flag of the SCSR register after a character is

shifted out and may optionally generate an interrupt to the CPU



SCI registers

Serial Communication Data Register (SCDR)

Receive data register (RDR) and transmit data register (TDR) are referred to as SCDR.

Serial Communication Status Register (SCSR)

TDRE: set to 1 when transmit data register is emptyTC: set to 1 when transmission is complete (the whole message have been sent out)RDRF: set to 1 when receive data register is fullIDLE: set to 1 when idle line condition is detectedOR: set to 1 when receiver is overrunNF: set to 1 when communication line is noisyFE: set to 1 when framing error occurs

TDRE TC RDRF IDLE OR NF FE 0

7 6 5 4 3 2 1 0

value afterreset 0 0 0 0 0 01 1

SCSRat $102E



Serial Communication Control Register 1 (SCCR1)

R8: receive data bit 8T8: transmit data bit 8M: data format bit (0 selects 8 data bits, 1 selects 9 data bits)WAKE: wake up method select (0 selects idle line, 1 selects address mark

wake up method)

7 6 5 4 3 2 1 0

u u 0 0 0 0 0 0

R8 T8 0 0 0 0M WAKEvalue after

reset

SCCR1at $102C



Serial Communication Control Register 2 (SCCR2)

TIE: transmit interrupt enableTCIE: transmit complete interrupt enableRIE: receive interrupt enable (including receive data register full and receiver overrun)ILIE: idle line interrupt enableTE: transmit enableRE: receive enableRWU: receiver wake up (puts the receiver in sleep and enables wake up mechanism)SBK: send break

A break is defined as the transmission or reception of a low for at least one completecharacter frame time (from the viewpoint of a DTE).

An idle line is defined as a continuous logic high on the RxD line for at least a complete character frame time (from the viewpoint of a DTE).

7 6 5 4 3 2 1 0

00000000

TIE TCIE RIE ILIE TE RE RWU SBKSCCR2at $102DValue after

reset



Baud Register (BAUD)

TCLR: clear baud rate counter (used in factory testing only)RCKB: SCI baud rate check (used in factory testing only)

The baud rate is derived by dividing the E clock signal by two factors specified in the BAUD register.

SCP0--SCP1prescaler

control ÷ N

SCR2--SCR0SCI select

rate control÷ M

SCIreceive

clock (RT)

÷ 16SCI

transmitclock

E clock

Figure 9.10 SCI rate generator division (Redrawn with permission of Motorola)

7 6 5 4 3 2 1 0

u u0 0 00 0

TCLR 0 SCP1 SCR2 SCR1 SCR0SCP0 RCKBvalue after

reset

BAUDat $102B

u

SCP1 SCP0Divide processor

clock by

0011

0101

134

13

Table 9.2 Baud rate prescale factor

SCR1 SCR0Divide processor

clock by

00110011

01010101

1248

163264

128

Table 9.3 SCI baud rate select

SCR2

00001111



Example 9.3 Give a set of baud rate prescale and baud rate select factors to set the baud rate to 9600 with a 2-MHz E clock.Solution:

- the frequency of the clock that is used to determine the bit value is 16 × 9600 = 153,000.

- 13 × 153000 = 1996800 2 MHz.- set the prescale factor to 13 (set SCP1 & SCP0 to 11)- set the baud rate select factor to 1 (set SCR2-SCR0 to 000)- write the value $30 to the BAUD register



SCI Interfacing

- the SCI uses 0 V and 5 V to represent 0 and 1- the RS232 signal Tx cannot be driven by the SCI TxD signal without translation- the RS232 signal Rx cannot drive the SCI RxD signal without translation- voltage level translation is required for the SCI signals to drive and be driven

by the RS232 signals- Companies such as MAXIM and Motorola provide RS232 driver and receiver

chips that perform the required voltage translation- MAX232 from MAXIM is a RS232 driver chip that operates off a single 5V

power supply



MAX232 signals

+5 V

+5 V

400 K

400 K RS232outputs

RS232inputs

TTL/CMOSinputs

TTL/CMOSinputs

TTL/CMOSoutputs

TTL/CMOSoutputs

Figure 9.11 Pin assignments and connections of the MAX232

10

11

12

9

15

8

13

7

14

R2 IN

R1 IN

5K

5K

T1 IN

T2 IN

R1 OUT

R2 OUT

T1 OUT

T2 OUT

1.0 F

1.0 F

1

3

4

5

1.0 F

+5 V

16

+10 VV+

V--10 V

1.0 F

2

6

V CC

GND



Interfacing the 68HC11 SCI to the RS232 using the MAX232 chip and implements the NULL modem connection so that this connection can talk to a PC directly.

TxD

RxD

T1 IN

R1 OUT

T2 IN

R2 OUT

T2 OUT

R2 IN

T1 OUT

R1 IN

T X D

R X D3

2

CTS

DSR

DCD

DTR

5

6

8

20

1

7

GND

SIGGND

Null-ModemConnection

68HC11

MAX232

Figure 9.12 Diagram of the SCI's EIA-232 side circuit connection

RS-232connector



Example 9.4 Write a subroutine that initialize the 68HC11 SCI subsystem to operate withthe following parameters:

- 9600 baud- 1 start bit, 8 data bits, and 1 stop bit- no interrupt for receive and transmit- enable receive and transmit- idle line wakeup- do not send break

Solution:

- to choose 9600 baudwrite $30 into BAUD

- for the remainingparameters, write $00and $0C into SCCR1and SCCR2

regbas equ $1000baud equ $2Bsccr1 equ $2Csccr2 equ $2D

on_sci pshxpshaldx #regbasldaa #$30staa baud,Xldaa #0staa sccr1,Xldaa #0Cstaa sccr2,Xpulapulxrts



Example 9.5 Write a subroutine to send break to the communication port controlled by theSCI subsystem. The duration of the transmitted break is approximately 200,000 E clock cycles.Solution:

- A break can be sent by setting the bit 0 of SCCR2 to 1. As long as this bit is 1, the SCI willkeep sending out break characters.

regbas EQU $1000SCCR2 EQU $2Dsendbrk PSHX

LDX #regbasBSET SCCR2,X $01 ; set send break bit

* the following 3 instructions create a delay of about 100 msLDY #28751

txwait DEYBNE txwait

BCLR SCCR2,X $01 ; clear the SBK bit of SCCR2PULXRTS



C Function to Send Break for 100 ms

void send_break ( ){

char i;SCCR2 |= 0x01; /* set the bit that triggers send break */TFLG1 = 0x40; /* clear OC2 F flag */TOC2 = TCNT + 20000; /* start an OC2 operation with 10 ms delay */for (i = 0; i < 10; i ++) { /* wait for 100 ms */

while (!(TFLG1 & 0x40));TFLG1 = 0x40;TOC2 += 20000;

}SCCR2 &= 0xFE; /* stop send break */

}



Example 9.6 Write a subroutine to output a character from the SCI subsystem using the polling method. The character to be output is in accumulator A.Solution: The subroutine will wait until the TDRE bit is set to 1 and then send out the character.regbas EQU $1000SCSR EQU $23 ; offset of SCSR from regbasSCDR EQU $2F ; offset of SCDR from regbasTDRE EQU $80 ; mask to select the TDRE bit of SCSRSCIputch PSHX

LDX #regbasBRCLR SCSR,X TDRE * ; wait until transmit data register is emptyANDA #$7F ; clear bit 7STAA SCDR,X ; send the characterPULXRTS

In C language,

#define TDRE 0x80void sci_putch (char xch){

while (!(SCSR & TDRE));SCDR = xch & 0x7F;

}



Example 9.7 Write a subroutine to input a character from the SCI subsystem using the polling method. The character will be returned in accumulator A.Solution:regbas EQU $1000SCSR EQU $23 ; offset of SCSR from regbasSCDR EQU $2F ; offset of SCDR from regbasRDRF EQU $20 ; mask to select the RDRF bit of SCSR

SCIgetch PSHXLDX #regbasBRCLR SCSR,X RDRF * ; wait until RDRF bit is 1LDAA SCDR,X ; read the characterPULXRTS

In C language,

#define RDRF 0x20char sci_getch ( ){

while (!(SCSR & RDRF)); /* wait until the RDRF flag is set */return SCDR;

}



Serial Communication Interface Chips

- A general-purpose microprocessor needs an external serial interface chip to communicate with other computer.

- The 68HC11 needs external serial communication chips if it needs to talk to two or more DTEs.

- The Motorola 6850 ACIA, Intel 8251, Zilog Z8530, and Rockwell R6551 are among the popular serial communication chips

- Serial communication chips are also called universal asynchronous receiver and transmitter (UART)

- The Motorola 6850 is used in the EVB to implement the terminal port



The Motorola 6850 ACIA

- was designed to work with Motorola 8-bit microprocessors- can also work with the 68000 family microprocessors and also the 68HC11- has two 8-bit data registers, one each for receive and transmit- has a programmable control register and a read-only status register- the register select input in conjunction with the R/W input to select one of the

four registers

TxCLKEnable

R/WCS0CS1CS2

Reg Sel

IRQ

D0D1D2D3D4D5D6D7

TxData

CTS

DCD

RTS

RxData

VCC

VSS

414138

109

11

7

2221201918171615

12

1

2

5

23

24

6

6850

Reg Sel R/W Register

1 0 Tx Data Register 1 1 Rx Data Register 0 0 Control Register 0 1 Status Register

Table 8.4 MC6850 Register Selection

RxCLK3



Control register

RxINTEnable

Transmitcontrol

Formatselect

Counterdivide

00011011

0010

RTS TxINT

disabledenableddisableddisabled

000001010011100101110111

7 data; even; 2 stop7 data; odd; 2 stop7 data; even; 1 stop7 data; odd; 1 stop8 data; 2 stop8 data; 1 stop8 data; even; 1 stop8 data; odd; 1 stop

00011011

÷ 1÷ 16÷ 64

master reset

7 6 5 4 3 2 1 0

Figure 9.14 MC6850 control register



Status Register

IRQ: interrupt request flagPE: parity errorOVRN: overrun flagFE: frame error flagCTS: clear to send flag that reflects the current level of the CTS input from a modemDCD: data carrier detect flag. This bit goes high when the DCD input from the modem

goes high (indicates no carrier condition)TDRE: transmit data register emptyRDRF: receive data register full

IRQ PE OVRN FE CTS DCD TDRE RDRF

7 6 5 4 3 2 1 0

Figure 9.15 The MC6850 status register



ACIA Transmit Operation Sequence

- the CPU reads the ACIA as a result of an interrupt or polling sequence- the CPU writes a character into the TDR if the TDRE bit of the status register is 1- the ACIA transfers the character to the transmit shift register to serialize the character- the transmitter adds start bit, stop bit(s) and optionally parity bit to the serialized character

before sending it to the TxData pin

ACIA Receive Operation Sequence

- the RxCLK clock which is either 1 or 16 or 64 times the bit rate is used to detect the arrivalof a start bit

- for the divide-by-16 or divide-by-64 counter divide factor, the start bit is detected by 8 or32 consecutive low samples from the RxData pin

- the ACIA receiver detects the start bit- the ACIA shifts in the character and discards the stop bit(s)- the ACIA records parity, receiver overrun, and framing errors in the status register

ACIA Interrupts

- one transmit interrupt source: transmit data register empty- three receive interrupt sources: receive data register full, receiver overrun, and

data carrier detect goes high



Interfacing ACIA to the 68HC11

- the 68HC11 should be configured to operate in expanded mode- address space should be assigned to the ACIA- an example of circuit connection is shown in Figure 9.17



5 V

3.3 K E3 E2 E1

B7/A15

B6/A14

B5/A13

A2

A1

A0

6840_CS

SRAM_CSPIA_CS

ROM_CS

CS2

3.3 K

5 V

IRQ

CS0CS1E(nable)R/W

.

.

.

reg sel

A11A12

ER/W

AS

AD7-AD0

D7-D0

MC6850

68HC11

Figure 9.17 MC6850 microprocessor side connections

LE

D7-D0

O0

O7OE

74F373

74F138O1

O2O3O4O7

IRQ



Example 9.9 Implement the null modem connection to the ACIA so that the 68HC11 cantalk to a PC via a straight-through RS232 cable and connector. This implementation shouldallow the user to select from the following baud rates: 300, 600, 1200, 2400, 4800, and 9600.

Solution:

- A crystal oscillator will be needed to generate an accurate and stable clock signal. A 2.4576 MHz crystal oscillator is used in this example.

- A Schmidt-Trigger inverter circuit will be used to convert the sinusoidal output of theoscillator to a square wave. The 74HC14 is used.

- A ripple counter is needed to provide a choice of baud rates. A 74HC4040 is used. Byfeeding the output of the 74HC14 to the 74HC4040, the frequencies of Q1-Q7 are1.2288 MHz, 0.6144 MHz, 0.3072 MHz, 0.1536 MHz, 0.0768 MHz, 0.0384 MHz, and0.0192 MHz.

- Choosing 64 as the divide factor for the receive clock, baud rates of 9600, 4800, 2400,1200, 600, and 300 are obtained.



A1

Y1

A2

Y2

A3

Y3

GND

V CC

A6

Y6

A5

Y5

A4

Y4

1

2

3

4

5

6

7 8

9

10

11

12

13

14

74HC14

A1

A2

A3

A4

A5

A6

Y1

Y2

Y3

Y4

Y5

Y6

(b) Logic diagram

(a) Pin assignments

Figure 9.18 74HC14 pin assignments and logic diagram

GND

V CC1

2

3

4

5

6

7 10

11

12

13

14

15

16

74HC4040

Figure 9.19 74HC4040 pin assignment

Q11

Q10

Q8

Q3

Q9

Q2 Clock

Reset

Q7

Q6

Q5

Q4

8 9 Q1

Q12



- Use a MAX232 to perform voltage level translation and implement the Null modemconnection as shown in Figure 9.20.

2.4576 MHz

HC14 HC14

0.1 F24 pF

2.2 K 2.2 K

Q7Q6Q5Q4Q3Q2

300600

1200240048009600

CLK

reset

GND

TxCLK RxCLK

TxD

RxD

MAX232

T1 IN

R1 OUT

T1 OUT

R1 IN

T2 IN

R2 OUT R2 IN

T2 OUT

TxD

RxD

CTSDSRDCD

1

3

2

56820

7

GNDSIG-GND

Null modemconnection

EIA-232connector

EIA232pin number

MC6850

Figure 9.20 Diagram of EIA232 side circuit connection

74HC404010

11

DCD

CTS

V SS



Example 9.10 Write an instruction sequence to configure the ACIA in Figure 9.20 to operatewith the following parameters:

- disable receive and transmit interrupts- counter divide factor is 64- data format is 8 data bits, 1 stop bit, and no parity

Solution:

- To disable receive interrupts, clear the bit 7 of the ACIA control register.- To disable transmit interrupt, set bits 6 and 5 of the ACIA control register to 00 or 11.- For the chosen data format, set bits 4-2 of the control register to 101.- Set bits 1-0 of the control register to 10 to select the specified divide factor.- The address space assigned to the ACIA is $9800-$9FFF.

acia_ini EQU $16LDAA #acia_iniSTAA $9800



A Terminal I/O Package for ACIA

ONACIA initializes the ACIA control registerGETCH returns a character in accumulator A from the ACIA receive data registerPUTCH writes the contents of accumulator A into the ACIA transmit data registerGETSTR inputs a string that is terminated by a carriage return (CR). The string is to

be stored in the buffer pointed to by Y.PUTSTR outputs a Null-terminated string pointed to by YNEWLINE outputs a CR/LF character pair to the terminalCHPRSNT clears the Z bit in CCR to 0 if a character is present in the ACIA receive data

register; otherwise sets the Z flag to 1.PUTHEX prints in 2 hex digits the 8-bit contents of AECHOFF turns off keyboard input echoing (to the screen)ECHO turns on keyboard input echoing (to the screen)LFON expands a CR into CR/LF pair and expands a LF into LF/CR pairLFOFF turns off newline expansion



Constant definitions for the ACIA I/O package

ACIA equ $9800 ; base address of the ACIACR equ $0D ; ASCII code of carriage returnLF equ $0A ; ASCII code of line feedTDRE equ $02 ; mask to select the transmit data register empty flagRDRF equ $01 ; mask to select the receive data register full flagcontrol equ $0 ; offset of the ACIA control register from its base addressstatus equ $0 ; offset of the ACIA status register from its base addressxmit equ $01 ; offset of the ACIA transmit data register from its base addressrcv equ $01 ; offset of the ACIA receive data register from its base addressmasterst equ $03 ; value to reset ACIA control registerctl_ini equ $16 ; value to initialize the ACIA control register

ONACIA pshxpshaldx #ACIAldaa #masterst ; reset the ACIAstaa control,X ; “ldaa #ctl_ini ; set up ACIA parametersstaa control,X ; “pulapulxrts



In C language, we need to add the following declaration to the hc11.h file so that we can usesymbols to access ACIA registers:

#define ACIA_CTRL *(unsigned char volatile *)(0x9800)#define ACIA_STAT *(unsigned char volatile *)(0x9800)#define ACIA_XMIT *(unsigned char volatile *)(0x9801)#define ACIA_RCV *(unsigned char volatile *)(0x9801)

ACIA initialization in C language

void on_acia ( ){

ACIA_CTRL = 0x03; /* master reset ACIA */ACIA_CTRL = 0x16; /* configure ACIA parameters */

}



Flowchart of GetchStart

read ACIAstatus register

Is there is a framing,overrun, or parity

error?

ReinitializeACIA

Is receive dataregister full?

yes

no

no

yes

Read the receivedata register

mask out bit 7

Stop

Is echo flag set?Echo the character

to the screenyes

no

Figure 9.21 Flowchart of the GETCH routine



GETCH PSHXPSHBLDX #ACIA

* The following instruction checks framing, parity, and overrun errors

retry BRCLR status,X $70 noerr

JSR ONACIA ; reset ACIABRA retry

* The next instruction checks if receive data register is full

noerr BRCLR status,X RDRF retrygetit LDAA rcv,X ; read the character

ANDA #$7F ; mask out bit 7LDAB echo ; is echo flag on?BEQ quit ; “JSR PUTCH ; echo the character

quit PULBPULXRTS



C Language Version of Getch

char getchar ( ){

char xch;while (ACIA_STAT & 0x70) {

on_acia ( );}while (!(ACIA_STAT & 0x01)); /* wait until receive data register is full */xch = ACIA_RCV & 0x7F; /* mask out parity bit */if (ECHO_ON) putchar (xch);/* echo the character to the screen */return xch;

}



Flowchart of PUTCH routine

Start

Is transmit dataregister empty?

Output the character

Is auto line-feedexpansion flag = 1?

Does accumulatorA contain CR?

Does accumulatorA contain LF?

Place LF character in A

Place CR character in A

yes

no

Is transmitregister empty?

yes

yes

yes

no

no

no

Output the characterin accumulator A

Stop

no

yes

Figure 9.22 Logic flow of the subroutine PUTCH



PUTCH BSR outchTST autolf ; check auto line feed flagBEQ quit ; prepare to return if notCMPA #CR ; does A contains a CR?BNE chklf ; go and check LFLDAA #LF ; also output a LFBSR outch ; “BRA quit

chklf CMPA #LF ; does A contains a LF?BNE quit ; prepare to return if notLDAA #CR ; also output a CRBSR outch

quit RTS

outch LDX #ACIABRCLRstatus,X TDRE * ; wait until xmit emptySTAA xmit,X ; output the characterRTS



C Function that Outputs A Character

char auto_lf; void outchar (xch)#define CR 0x0D; {#define LF 0x0A; while (!(ACIA_STAT &0x02));void outchar (char xch); ACIA_XMIT = xch;void putchar (char xch); }{

outchar (xch);if (auto_lf) {

switch (xch) {case CR:

outchar (LF);break;

case LF:outchar (CR);break;

default: break;}

}}



GETSTR PSHAgsloop JSR GETCH ; get a character

CMPA #CR ; is it a carriage return?BEQ gfinis ; if yes, then it is the end of the stringSTAA 0,Y ; save the characterINY ; move the pointerBRA gsloop

gfinis LDAA #00 ; add a Null to the end of the stringSTAA 0,Y ; “PULARTS

PUTSTR PSHApsloop LDAA 0,Y

BEQ pfinis ; is this the end of the string?JSR PUTCH ; if not, output the characterINY ; move to the next characterBRA psloop

pfinis PULARTS



GETSTR Function in C

void getstr (char *ptr){

char xch;while ((xch = getchar ( )) != ‘\n’)

*ptr++ = xch;*ptr = ‘\0’;

}

PUTSTR Function in C

void putstr (char *ptr){

while (*ptr) {putchar (*ptr);ptr ++;

}}



NEWLINE PSHALDAA #$01 ; set the auto linefeed expansion flagSTAA autolf ; “LDAA #CR ; output a carriage returnJSR PUTCH ; output a CR which will be expanded into CR/LF pairPULACLR autolf ;clear the auto line feed expansion flagRTS

In C language,

void newline ( ){

auto_lf = 1; /* set auto-linefeed flag */putchar (CR);auto_lf = 0;

}



CHPRSNT PSHAPAHXLDX #ACIALDAA status,XBITA #RDRF ; test the RDRF flag to update the Z flag of CCRPULXPULARTS

In C language,

int chprsnt ( ){

if (ACIA_STAT & 0x01)return 1;

else return 0;}



PUTHEX PSHXPSHBPSHATAB ; make a copy of A in BLSRB ; shift the upper hex digit LSRB ; to the lower half of BLSRB ; “LSRB ; “LDX #hexdig ; place the address of the hex digit table in XABX ; point X to the ASCII code of the upper hex digit in ALDAA 0,X ; get the ASCII codeJSR PUTCH ; output the upper hex digitPULB ; put A in B againPSHB ; restore the stackANDB #$0F ; mask out the upper digitLDX #hexdig ; place the address of the hex table digit in XABX ; point X to the ASCII code of the lower hex digit in ALDAA 0,X ; get the ASCII code of the lower hex digitJSR PUTCH ; output the hex digitPULAPULBPULXRTS

hexdig FCC “0123456789ABCDEF” ; hex digits ASCII code table



PUTHEX Function in C Language

char hex_tab [16] = {‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’, ‘8’, ‘9’, ‘A’, ‘B’, ‘C’, ‘D’, ‘E’, ‘F’};void puthex (xch){

char xx;xx = xch & 0xF0; /* mask out the lower 4 bits */xx = xx >> 4;putchar (hex_tab[xx]);xx = xch & 0x0F; /* mask out the upper 4 bits */putchar (hex_tab[xx]);

}



ECHOFF CLR echo ; turn off input echoingRTS

ECHON LDAA #1STAA echo ; turn on input echoingRTS

LFON LDAA #1STAA autolf ; turn on auto line feed expansionRTS

LFOFF CLR autolf ; turn off auto line feed expansionRTS

echo RMB 1 ; input echo flagautolf RMB 1 ; line feed expansion flag

END

Documents

Chapter 9: 68HC11 Serial Communication Interface