Chapter 8: Combinational Logic Modulesocw.snu.ac.kr/sites/default/files/NOTE/6631.pdfChapter 8: Combinational Logic Modules Digital System Designs and Practices Using Verilog HDL and

Chapter 8: Combinational Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 8-1

Chapter 8: Combinational Logic

Modules

Prof. Soo-Ik Chae



Objectives

After completing this chapter, you will be able to:

Understand the features of decoders

Understand the features of encoders

Understand the features of priority encoders

Understand the features of multiplexers

Understand the features of demultiplexers

Describe how to design comparators and magnitude

comparators

Describe how to design a parameterized module



Basic Combinational Logic Modules

Commonly used combinational logic modules:

Decoder

Encoder

Multiplexer

Demultiplexer

Comparator

Adder (CLA)

Subtracter (subtractor)

Multiplier

PLA

Parity Generator

-



Options for Modeling Combinational Logic

Options for modeling combinational logic:

Verilog HDL primitives

Continuous assignment

Behavioral statement

Function

Task without delay or event control

Combinational UDP

Interconnected combinational logic modules



Three Descriptions of Combination Logic

Logic Description

Circuit Schematic

Truth Table

Switching Equations

Verilog Description

Structural Model

User-Defined Primitives

Continuous Assignments



Decoder Block Diagrams

An n m decoder has n input lines and m output lines. Each

output line Yi corresponds to the ith minterm of input (line)

variables.

Total decoding: when m = 2n.

Partial decoding: when m < 2n.

Y0

Y1

Inp

ut

Ou

tpu

t

Enable control

Ym-1

Ym-2

E

x0

x1

xn-1

xn-2

n-to-m

decoder

Y0

Y1

n-to-m

decoderInp

ut

Ou

tpu

t

Enable control

Ym-1

Ym-2

E

x0

x1

xn-1

xn-2



A 2-to-4 Decoder Example

(a) Logic symbol

(b) Function table (c) Logic circuit

x1

x0

E

Y0

Y1

Y2

Y3

Y0x

1

Y2

Y3

E

Y1

x0

2-t

o-4

dec

od

er

0

x1

x0

0

10

1 0

Y0

Y1

Y2

Y3

E

1 1111

0111

1011

1101

1110

0

0

0

0

f f

1 1

f : don’t care



A 2-to-4 Decoder Example

// a 2-to-4 decoder with active low output

module decoder_2to4_low(x,enable,y);

input [1:0] x;

input enable;

output reg [3:0] y;

// the body of the 2-to-4 decoder

always @(x or enable)

if (!enable) y = 4'b1111; else

case (x)

2'b00 : y = 4'b1110;

2'b01 : y = 4'b1101;

2'b10 : y = 4'b1011;

2'b11 : y = 4'b0111;

default : y = 4'b1111;

endcase

endmodule

y28

y25

y26

y27

un1_y28

un1_y25

un1_y26

un1_y27 y[3:0]

0

1

[0]

[1]

[0]

[1]

[0]

[1]

[1]

[0]

1111

[3:0]y[3:0]

[3:0]

enable

x[1:0][1:0]



A 2-to-4 Decoder with Enable Control

// a 2-to-4 decoder with active-high output

module decoder_2to4_high(x,enable,y);

input [1:0] x;

input enable;

output reg [3:0] y;

// the body of the 2-to-4 decoder


if (!enable) y = 4'b0000; else

case (x)

2'b00 : y = 4'b0001;

2'b01 : y = 4'b0010;

2'b10 : y = 4'b0100;

2'b11 : y = 4'b1000;

default : y = 4'b0000;

endcase

endmodule

y28

y25

y26

y27 y[3:0]

0

1

[0]

[1]

[0]

[1]

[0]

[1]

[1]

[0]

0000

[3:0]y[3:0]

[3:0]

enable

x[1:0][1:0]



A Parameterized Decoder Module

decode

y_3[3:0] y[3:0]

0

1[3:0]

EQ[3:0][1:0]

D[1:0]

0000

[3:0]

[3:0]y[3:0]

[3:0]

enable

x[1:0][1:0]

// an m-to-n decoder with active-high output

module decoder_m2n_high(x,enable,y);

parameter m = 3; // define the number of input lines

parameter n = 8; // define the number of output lines

input [m-1:0] x;

input enable;

output reg [n-1:0] y;

// The body of the m-to-n decoder


if (!enable) y = {n{1'b0}};

else y = {{n-1{1'b0}},1'b1}} << x;

endmodule



Encoder Block Diagrams

An encoder has m = 2n (or fewer) input lines and n output

lines. The output lines generate the binary code

corresponding to the input value.

(b) Inverted output(a) Noninverted output

Y0

Y1

Inp

ut

Ou

tpu

t

Enable control

Yn-1

Yn-2

E

I0

I1

Im-1

Im-2

m-to-n

encoder

Y0

Y1

m-to-n

encoderInp

ut O

utp

ut

Enable control

Yn-1

Yn-2

E

I0

I1

Im-1

Im-2



A 4-to-2 Encoder Example

Q: What is the problem of this encoder?

(a) Function table (b) Logic circuit

I0

I2

I3

I1

Y1

Y0

I1

I0

0

I2

I3

Y1

Y0

0 10 0 0

0 1

1 0

1 1

00 01

10 00

01 00

There are many undefined input cases!



A 4-to-2 Encoder Example

// a 4-to-2 encoder using if ... else structure

module encoder_4to2_ifelse(in, y);

input [3:0] in;

output reg [1:0] y;

// the body of the 4-to-2 enecoder

always @(in) begin

if (in == 4'b0001) y = 0; else

if (in == 4'b0010) y = 1; else

if (in == 4'b0100) y = 2; else

if (in == 4'b1000) y = 3; else

y = 2'bx;

end

endmodule

y22

y23

y24

y25

y[1:0]

e

d

e

d

e

d

e

d

[0]

[1]

[2]

[3]

[1]

[0]

[2]

[3]

[2]

[0]

[1]

[3]

[3]

[0]

[1]

[2]

00

01[1:0]

10

11

y[1:0][1:0]

in[3:0][3:0]



Another 4-to-2 Encoder Example

// a 4-to-2 encoder using case structure

module encoder_4to2_case(in, y);

input [3:0] in;

output reg [1:0] y;

// the body of the 4-to-2 enecoder

always @(in)

case (in)

4'b0001 : y = 0;

4'b0010 : y = 1;

4'b0100 : y = 2;

4'b1000 : y = 3;

default : y = 2'bx;

endcase

endmodule

y22

y23

y24

y25

y[1:0]

e

d

e

d

e

d

e

d

[0]

[1]

[2]

[3]

[1]

[0]

[2]

[3]

[2]

[0]

[1]

[3]

[3]

[0]

[1]

[2]

00

01[1:0]

10

11

y[1:0][1:0]

in[3:0][3:0]



A 4-to-2 Priority Encoder

(a) Block diagram (b) Function table

I0

A0

I2

I3

I1

A1

4-to-2

priority encoderI0

1

1 f

1 f f

1 0 0

f 0 1

f 1 0

f 1 1

I1

I2

I3

A1

A0

OutputInput

0

0

0

0

0

0



A 4-to-2 Priority Encoder Example

// a 4-to-2 priority encoder using if ... else structure

module priority_encoder_4to2_ifelse (in, valid_in, y);

input [3:0] in;

output reg [1:0] y;

output valid_in;

// the body of the 4-to-2 priority encoder

assign valid_in = |in;

always @(in) begin

if (in[3]) y = 3; else // MSB: higher priority

if (in[2]) y = 2; else



y = 2'bx;

end

endmodule un1_in_1

y23

valid_in

un1_in_3

y24

y25

y_1[0]

e

d

e

d

e

d

e

d

[2]

[3]

[2]

[3]

[0]

[1]

[2]

[3]

[1]

[1]

[0]

[3]

1

0

1

0

y[1:0]

valid_in

in[3:0][3:0]



Another 4-to-2 Priority Encoder Example

// a 4-to-2 priority encoder using case structure

module priority_encoder_4to2_case(in, valid_in, y);

input [3:0] in;

output reg [1:0] y;

output valid_in;

// the body of the 4-to-2 priority encoder

assign valid_in = |in;

always @(in) casex (in)

4'b1xxx: y = 3;

4'b01xx: y = 2;

4'b001x: y = 1;

4'b0001: y = 0;

default: y = 2'bx;

endcase

endmodule

y23[0]

y24[0]

valid_in

y25

y[1:0]

e

d

e

d

e

d

e

d

[2]

[3]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[3]

11

10[1:0]

01

00

y[1:0][1:0]

valid_in

in[3:0][3:0]



A Parameterized Priority Encoder Example

// an m-to-n priority encoder

module priencoder_m2n(x, valid_in, y);

parameter m = 8; // define the number of inputs

parameter n = 3; // define the number of outputs

input [m-1:0] x;

output valid_in; // indicates the data input x is valid.


integer i;

// the body of the m-to-n priority encoder

assign valid_in = |x;

always @(*) begin: check_for_1

for (i = m - 1 ; i > 0 ; i = i - 1)

if (x[i] == 1) begin y = i; disable check_for_1; end

else y = 0; // Why need else …?

end

endmodule

check_for_1_l1.i20

check_for_1_l1.un1_x

un1_x_1

valid_in

check_for_1_l2.i18

check_for_1_l2.i21

y_1[0]

e

d

e

d

e

d

e

d

[3]

[2]

[3]

[2]

[0]

[1]

[2]

[3]

[1]

[1]

0

[3]

1

0

1

y[1:0]

valid_in

x[3:0][3:0]

Q: Explain the philosophy behind

this program. Why is it so simple?



A Better Parameterized Priority Encoder Example

// an m-to-n priority encoder

module priencoder_m2n_while(x, valid_in, y);

parameter m = 4; // define the number of inputs

parameter n = 2; // define the number of outputs

input [m-1:0] x;

output valid_in; // indicates the data input x is valid.


integer i;

// the body of the m-to-n priority encoder

assign valid_in = |x;

always @(*) begin

i = m - 1 ;

while(x[i] == 0 && i >= 0 ) i = i - 1;

y = i;

end

endmodule

un1_x_1

un1_x_2

valid_in

un1_x_3

un1_x_4

i_12[1:0]

e

d

e

d

e

d

e

d i[1:0]

0

1

[2]

[1]

[2]

[1]

[0]

[1]

[2]

[3]

[0]

[0]

[2]

10

01[1:0]

00

11

[3]

[1:0]

[1:0]

11y[1:0]

[1:0]

valid_in

x[3:0][3:0]



Multiplexer Block Diagrams

An m-to-1 ( m = 2n ) multiplexer has m input lines,1 output

line, and n selection lines. The input line Ii selected by the

binary combination of n source selection lines is directed to

the output line, Y.

(a) Without enable control (b) With enable control

InputOutput

Source selection

I0

I1

Y

Sn-1

S0S

1

2n-to-1

MUX

I -12n

I -22n

Output

Source selection

E

Input

Enable

control

I0

I1

Y

Sn-1

S0S

1

2n-to-1

MUX

I -12n

I -22n



A 4-to-1 Multiplexer Example

Gate-based 4-to-1 multiplexers

(a) Logic symbol (b) Function table (c) Logic circuit

I0

I1

YI2

I3

S1

S0

Y

I0

I1

4-t

o-1

MU

X

I2

I3

S1

S0

Y

0

1

I0

I1

S1

S0

0

0

01

1 1

I2

I3



An n-bit 4-to-1 Multiplexer Example

// an N-bit 4-to-1 multiplexer using conditional operator.

module mux_nbit_4to1(select, in3, in2, in1, in0, y);

parameter N = 4; // define the width of 4-to-1 multiplexer

input [1:0] select;

input [N-1:0] in3, in2, in1, in0;

output [N-1:0] y;

// the body of the N-bit 4-to-1 multiplexer

assign y = select[1] ?

(select[0] ? in3 : in2) :

(select[0] ? in1 : in0) ;

endmodule

un1_select_2

un1_select_3

un1_select_4

un1_select_5

y[3:0]

e

d

e

d

e

d

e

d

[0]

[1]

[1]

[0]

[0]

[1]

[0]

[1]

[3:0]

[3:0][3:0]

[3:0]

[3:0]

y[3:0][3:0]

in0[3:0][3:0]

in1[3:0][3:0]

in2[3:0][3:0]

in3[3:0][3:0]

select[1:0][1:0]



The Second n-bit 4-to- 1 Multiplexer Example

// an N-bit 4-to-1 multiplexer with enable control.

module mux_nbit_4to1_en (select, enable, in3, in2, in1, in0, y);


input [1:0] select;

input enable;


output reg [N-1:0] y;


always @(select or enable or in0 or in1 or in2 or in3)

if (!enable) y = {N{1’b0}};

else y = select[1] ?

(select[0] ? in3 : in2) :

(select[0] ? in1 : in0) ;

endmodule



The Third n-bit 4-to- 1 Multiplexer Example

// an N-bit 4-to-1 multiplexer using case structure.

module mux_nbit_4to1_case(select, in3, in2, in1, in0, y);


input [1:0] select;


output reg [N-1:0] y;


always @(*)

case (select)

2’b11: y = in3 ;

2’b10: y = in2 ;

2’b01: y = in1 ;

2’b00: y = in0 ;

endcase

endmodule

un1_select_2

un1_select_3

un1_select_4

un1_select_5

y[7:0]

e

d

e

d

e

d

e

d

[0]

[1]

[1]

[0]

[0]

[1]

[0]

[1]

[7:0]

[7:0][7:0]

[7:0]

[7:0]

y[7:0][7:0]

in0[7:0][7:0]

in1[7:0][7:0]

in2[7:0][7:0]

in3[7:0][7:0]

select[1:0][1:0]



A Parameterized Multiplexer Example

_l3.un1_select

_l2.un1_select

_l1.un1_select

_l0.un1_select

y

e

d

e

d

e

d

e

d

[0]

[1]

[1]

[0]

[0]

[1]

[0]

[1]

[3]

[2]

[1]

[0]

y

in[3:0][3:0]

select[1:0][1:0]

// an example of parameterized M-to-1 multiplexer.

module mux_m_to_1(select, in, y);

parameter M = 4; // define the size of M-to-1 multiplexer

parameter K = 2; // define the number of selection lines

input [K-1:0] select;

input [M-1:0] in;

output reg y;

// the body of the M-to-1 multiplexer

integer i;

always @(*)

for (i = 0; i < M; i = i + 1)

if (select == i) y = in[i];

endmodule



DeMultiplexer Block Diagrams

A 1-to-m ( m = 2n ) demultiplexer has 1 input line, m output

lines, and n destination selection lines. The input line D is

directed to the output line Yi selected by the binary

combination of n destination selection lines.

(a) Without enable control (b) With enable control

Y0

Y1

DInputOutput

Destination selection

Sn-1 S

0S

1

1-to-2n

DeMUX

Y -22n

Y -12n

EEnable

control

Y0

Y1

DInput Output

Destination selection

Sn-1 S

0S

1

1-to-2n

DeMUX

Y -22n

Y -12n



A 1-to-4 DeMultiplexer Example

Gate-based 1-to-4 demultiplexers

(a) Logic symbol (b) Function table (c) Logic circuit

DY

0

S1

S0

E

Y1

Y2

Y3

E

D

Y0

Y1

1-t

o-4

DeM

UX

Y2

Y3

S0

S1

0

S1

S0

0

10

1 0

Y0

Y1

Y2

Y3

E

1 0000

D000

0D00

00D0

000D

0

0

0

0

f f

1 1



An n-bit 1-to-4 DeMultiplexer Example

// an N-bit 1-to-4 demultiplexer using if ... else structure

module demux_1to4_ifelse (select, in, y3, y2, y1, y0);

parameter N = 4; // define the width of the demultiplexer

input [1:0] select;

input [N-1:0] in;

output reg [N-1:0] y3, y2, y1, y0;

// the body of the N-bit 1-to-4 demultiplexer

always @(select or in) begin

if (select == 3) y3 = in; else y3 = {N{1'b0}};




end

endmodule

y37

y27

y17

y07

y3[3:0]

0

1

y2[3:0]

0

1

y1[3:0]

0

1

y0[3:0]

0

1

[0]

[1]

[1]

[0]

[0]

[1]

[0]

[1]

0000

[3:0]

[3:0]

0000

[3:0]

[3:0]

0000

[3:0]

[3:0]

0000

[3:0]

[3:0]y0[3:0]

[3:0]

y1[3:0][3:0]

y2[3:0][3:0]

y3[3:0][3:0]

in[3:0][3:0]

select[1:0][1:0]



The Second n-bit 1-to-4 DeMultiplexer Example

// an N-bit 1-to-4 demultiplexer with enable control

module demux_1to4_ifelse_en(select, enable, in, y3, y2, y1, y0);

parameter N = 4; // Define the width of the demultiplexer

input [1:0] select;

input enable;

input [N-1:0] in;

output reg [N-1:0] y3, y2, y1, y0;

// the body of the N-bit 1-to-4 demultiplexer

always @(select or in or enable) begin

if (enable)begin





end else begin

y3 = {N{1'b0}}; y2 = {N{1'b0}}; y1 = {N{1'b0}}; y0 = {N{1'b0}};

end

end

endmodule



A Parameterized DeMultiplexer Example

_l3.y86

_l0.y18

_l1.y42

_l2.y66

y_1[3]

0

1

y_1[0]

0

1

y_1[1]

0

1

y_1[2]

0

1

[0]

[1]

[0]

[1]

[0]

[1]

[1]

[0]

0

[3]

0

[0]

0

[1]

0

[2]

y[3:0][3:0]

in

select[1:0][1:0]// an example of 1-to-M demultiplexer module

module demux_1_to_m(select, in, y);

parameter M = 4; // define the size of 1-to-m demultiplexer

parameter K= 2; // define the number of selection lines

input [K-1:0] select;

input in;

output reg [M-1:0] y;

integer i;

// the body of the 1-to-M demultiplexer

always @(*)

for (i = 0; i < M; i = i + 1) begin

if (select == i) y[i] = in; else y[i] = 1'b0; end

endmodule



Comparators

A magnitude comparator is a device that determines the

relative magnitude of two numbers being applied to it.

Two types of magnitude comparator circuits:

Comparator

Cascadable comparator

A0

A1

A3

A2

B0

B1B

3B

2

IA>B

IA=B

IA<B

OA>B

OA=B

OA<B

4-bit comparator

A 4-bit cascadable comparator block diagram



Comparators

Cascading two 4-bit comparators to form an 8-bit comparator.

What will happen if you set the input value (010) at the

rightmost end to other values?

A0

A1

A3

A2

B0

B1B

3B

2

IA>B

IA=B

IA<B

OA>B

OA=B

OA<B

4-bit comparator A

A0

A1

A3

A2

B0

B1B

3B

2

IA>B

IA=B

IA<B

OA>B

OA=B

OA<B

0

1

0

B0

B1

B3

B2

A0

A1

A3

A2

B4

B5

B7

B6

A4

A5

A7

A6

4-bit comparator B



A Simple Comparator Example

// an N-bit comparator module example

module comparator_simple(a, b, cgt, clt, ceq);

parameter N = 4; // define the size of comparator

// I/O port declarations

input [N-1:0] a, b;

output cgt, clt, ceq;

// the body of the N-bit comparator

assign cgt = (a > b);

assign clt = (a < b);

assign ceq = (a == b);

endmodule

ceq

=

cgt

<

clt

<

[3:0]

[3:0]

[3:0]

[3:0]

[3:0]

[3:0]

ceq

clt

cgt

b[3:0] [3:0]

a[3:0][3:0]



A Cascadable Comparator Example

module comparator_cascadable (Iagtb, Iaeqb, Ialtb, a, b, Oagtb, Oaeqb, Oaltb);

parameter N = 4; // define the size of comparator

// I/O port declarations

input Iagtb, Iaeqb, Ialtb;

input [N-1:0] a, b;

output Oagtb, Oaeqb, Oaltb;

// dataflow modeling using relation operators

assign Oaeqb = (a == b) && (Iaeqb == 1); // equality

assign Oagtb = (a > b) || ((a == b)&& (Iagtb == 1)); // greater than

assign Oaltb = (a < b) || ((a == b)&& (Ialtb == 1)); // less than

endmodule

un1_Oaeqb

=

un1_Oagtb

<

un1_Oaltb

<

Oaeqb

un2_Oagtb

un2_Oaltb

Oagtb

Oaltb

[3:0]

[3:0]

[3:0]

[3:0]

[3:0]

[3:0]

Ialtb

Iaeqb

Iagtb

b[3:0][3:0]

a[3:0][3:0]

Oaltb

Oaeqb

Oagtb

Documents

Chapter 8: Combinational Logic Modulesocw.snu.ac.kr/sites/default/files/NOTE/6631.pdfChapter 8: Combinational Logic Modules Digital System Designs and Practices Using Verilog HDL and