Chapter 8 - ADC

8/19/2019 Chapter 8 - ADC

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Chapter 8Chapter 8

Analog-to-Digital Converter (ADC)Analog-to-Digital Converter (ADC)

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Why Analog-to-Digital Conversion?Why Analog-to-Digital Conversion?

• In the physical world, everything isIn the physical world, everything is

analog (continuous).analog (continuous).

• We need an analog-to-digital converterWe need an analog-to-digital converter

to translate analog signals to digitalto translate analog signals to digitalnu!ers so that the icrocontroller cannu!ers so that the icrocontroller can

read and process the.read and process the.

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n-resolution ADCn-resolution ADC

• ""#$%-#$%- & ' - '& ' - '

• ""#$%#$% & "& "DDDD - *- *nn-+-+

• I ADC result & I ADC result &

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r in ters o "r in ters o "#$%-#$%-/ "/ "#$%)#$%)00


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$1aples$1aples

• e.g., "e.g., "#$%-#$%- & ', "& ', "#$%)#$%) & 2"& 2",, +'-!it resolution+'-!it resolutionADC. 3uppose the ADC results are asADC. 3uppose the ADC results are asollows. What are the correspondingollows. What are the corresponding

voltages?voltages?a.a.*'*'

""*'*' & *'124(*& *'124(*+'+'-+) & '.'566"-+) & '.'566"

!.!.755755

""755755 & 755124(*& 755124(*+'+'-+)& *.7"-+)& *.7"

c.c.858858

""858858 & 858124(*& 858124(*+'+'-+)&7.8"-+)&7.8"

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9IC+8 ADC :odule9IC+8 ADC :odule

• 9IC+8%72*' has + analog inputs9IC+8%72*' has + analog inputs

channels.channels. (nly one channel is used at(nly one channel is used at

any given tie)any given tie)

• ;enerates +'-!it !inary results;enerates +'-!it !inary results

• ""#$%-#$%- / "/ "#$%)#$%) are ad


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=loc Diagra o 9IC+8 ADC=loc Diagra o 9IC+8 ADC

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3%# controlling the unctions o ADC3%# controlling the unctions o ADC

• A4D Control #egister ' (ADC>')A4D Control #egister ' (ADC>')

• A4D Control #egister + (ADC>+)A4D Control #egister + (ADC>+)

• A4D Control #egister * (ADC>*)A4D Control #egister * (ADC>*)

• A4D #esult igh #egister (AD#$3)A4D #esult igh #egister (AD#$3)

• A4D #esult @ow #egister (AD#$3@)A4D #esult @ow #egister (AD#$3@)

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ADC>'ADC>'

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ADC>'ADC>'

• C30C3'0 Analog Channel 3elect =itsC30C3'0 Analog Channel 3elect =its –

9IC+8%72*' has only + Analog-to-Digital unit9IC+8%72*' has only + Analog-to-Digital unit – Can only select + input ro A>'0A>+* to !eCan only select + input ro A>'0A>+* to !e

sapled and convertedsapled and converted

• ;4D>$0;4D>$0 –

3etting this !it starts A4D conversion3etting this !it starts A4D conversion – Cleared when A4D conversion is doneCleared when A4D conversion is done

• AD>0AD>0 – 9ower up (+)43hut o (') the ADC odule9ower up (+)43hut o (') the ADC odule

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ADC>+ADC>+

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ADC>+ADC>+

"oltage #eerence Coniguration !its"oltage #eerence Coniguration !its•"C%;+0"C%;+0 ""#$%-#$%- sourcesource

+ & "+ & "#$%-#$%- (A>*)(A>*)

' & "' & "3333

•"C%;'0"C%;'0 ""#$%#$% sourcesource

+ & "+ & "#$%#$% (A>)(A>)

' & "' & "DDDD

A4D 9ort Coniguration !itsA4D 9ort Coniguration !its

9C%;0' B he input analog signal ust !e9C%;0' B he input analog signal ust !econigured as an analog input.conigured as an analog input.

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ADC>+0 A4D 9ort Coniguration !itsADC>+0 A4D 9ort Coniguration !its

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ADC>+0ADC>+0 A4D 9ort Coniguration !itsA4D 9ort Coniguration !its

• Do the ollowing two lines sound ailiar?Do the ollowing two lines sound ailiar? movlw 0x0F movlw 0x0F

movwf ADCON1 movwf ADCON1

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ADC>*ADC>*

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ADC>*ADC>*

• AD%:0 A4D #esult %orat 3elect !itAD%:0 A4D #esult %orat 3elect !it

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A4D Conversion ie0 A4D Conversion ie0 ADAD

• ADAD & tie reuired to coplete +-!it A4D& tie reuired to coplete +-!it A4Dconversionconversion

• ie reuired or one ull +'-!it A4Die reuired or one ull +'-!it A4D

conversion is ++ to +* conversion is ++ to +* ADAD B 3uccessive B 3uccessiveappro1iationappro1iation

• %ro the 9IC+8%72*' speciication, %ro the 9IC+8%72*' speciication, ADAD

ust !e !etween '.6 B *2ust !e !etween '.6 B *2 EEs.s.• ADAD can !e speciied ro *can !e speciied ro *oscosc to F7to F7oscosc

!y selecting the!y selecting the A/D Conversion Clock A/D Conversion ClockSelect BitsSelect Bits ( ( ADC3'0* in ADC>*ADC3'0* in ADC>* ). ).

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ow should ow should ADAD !e set?!e set?

• e.g., I a 7:G cloc is installed, e.g., I a 7:G cloc is installed, oscosc &&

'.*2'.*2EEs.s.

• he iniu he iniu ADAD that can !e set is 7that can !e set is 7oscosc..

•

ADAD can !e chosen ro 7can !e chosen ro 7oscosc (+(+EEs) tos) toF7F7oscosc (F7(F7EEs).s).

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3uccessive Appro1iation3uccessive Appro1iation

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3iple $1aple o 3uccessive Appro1iation3iple $1aple o 3uccessive Appro1iation

• * !it representation* !it representation 7 @evels7 @evels

• ' @evel' @evel ' " and @evel' " and @evel " "

• $1aple +0 Input "oltage *."$1aple +0 Input "oltage *."

– +st iteration0 3A# & +'+st iteration0 3A# & +' *. " * "? Hes*. " * "? Hes – *nd iteration0 3A# & ++*nd iteration0 3A# & ++ *. "? >o*. "? >o

3A#'J & '3A#'J & ' %inal 3A# & +'%inal 3A# & +'

• $1aple *0 Input "oltage +.6 "$1aple *0 Input "oltage +.6 " – +st iteration0 3A# & +'+st iteration0 3A# & +' +.6 * "? >o+.6 * "? >o

3A#+J & ' (i.e., 3A# & '')3A#+J & ' (i.e., 3A# & '')

– *nd iteration0 3A# & '+*nd iteration0 3A# & '+ +.6 + "? Hes+.6 + "? Hes%inal 3A# & '+.%inal 3A# & '+.

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3aple-and-hold circuit3aple-and-hold circuit

• he analog input voltage will charge uphe analog input voltage will charge upCC?@D?@D to a steady state !eore ADCto a steady state !eore ADC

!egins.!egins.

•

he tie reuired to reach steady statehe tie reuired to reach steady statedepends on #depends on #ss, #, #IC,IC, ##ssss and Cand C?@D.?@D.

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A4D Acuisition ie (ACK)A4D Acuisition ie (ACK)

• he iniu acuisition tie (he iniu acuisition tie (ACKACK) or) or9IC+8%72*' is +.79IC+8%72*' is +.7EEs.s.

• ADC odule will insert an acuisitionADC odule will insert an acuisition

tie !etween the ;4D>$ !it is settie !etween the ;4D>$ !it is setand when the conversion starts.and when the conversion starts.

• 3uppose 3uppose ADAD & +& +EEs. s. ACKACK & * & * ADAD

• ACKACK is set !y setting ACK'0* ois set !y setting ACK'0* oADC>*.ADC>*.

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A4D Conversion 9rocessA4D Conversion 9rocess

+.+. 3et ;4D>$ !it3et ;4D>$ !it

*.*. Wait Wait ACKACK to charge up Cto charge up C@D@D.. CC@D@D is disconnected and ADC !eginsis disconnected and ADC !egins

7.7. ++-+* ++-+* ADAD is reuired or a +'-!it ADCis reuired or a +'-!it ADC

2.2. When inished0When inished0 – AD#$30AD#$3@ are loadedAD#$30AD#$3@ are loaded

– ;4D>$ !it is cleared;4D>$ !it is cleared – ADI% !it is setADI% !it is set

– CC@D@D is reconnected to the analog inputis reconnected to the analog input

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$1aple Lse o the ADC$1aple Lse o the ADC

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:ain0 ovlw !M''''+++'Movw ADC>+ovlw !M'''''''+Movw ADC>'ovlw !M'''+'+''Movw ADC>*

clr #I3D

:ain@oop0 !s ADC>', ;adcNwait0 !tsc ADC>', ;

!ra adcNwait

ov AD#$3, 9#D

!ra :ain@oop

O3et #A' Analog 9ort, others Digital I4

O3elect ADC Channel ', $na!le ADC

O AD%: @et


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Hou should !e a!le to ... Hou should !e a!le to ...

•

Descri!e the roles o the ollowing 2Descri!e the roles o the ollowing 2registers0registers0 ADC>', ADC>+, ADC>*,ADC>', ADC>+, ADC>*,AD#$3 and AD#$3@ in the A4DAD#$3 and AD#$3@ in the A4Dconversion. hese registers speciy theconversion. hese registers speciy the

ollowing options0ollowing options0 – Which channel to convert?Which channel to convert?

– Which channel should !e set to accept analogWhich channel should !e set to accept analoginput?input?

– ow to store the conversion result?ow to store the conversion result? – What is "What is "re)re) and "and "re-re-??

– What is the conversion tie (What is the conversion tie (ADAD)?)?

– What is the acuisition tie (What is the acuisition tie (ACKACK)?)?24


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Hou should !e a!le to ... Hou should !e a!le to ...

• $1plain the process o sapling analog$1plain the process o sapling analogvoltage !eore A4D conversion.voltage !eore A4D conversion.

• $1plain why an acuisition tie is$1plain why an acuisition tie is

needed !eore A4D conversion.needed !eore A4D conversion.

• Descri!e the successive appro1iationDescri!e the successive appro1iation

algorith.algorith.

• Descri!e the whole A4D ConversionDescri!e the whole A4D Conversion

process.process.

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Chapter 8 - ADC