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Princess Sumaya Univ.Computer Engineering Dept.
Chapter 6:Chapter 6:
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.RegistersRegisters
Group of D Flip-Flops
Synchronized (Single Clock)
Store Data
D Q
R
Reset
D Q
R
D Q
R
D Q
RCLK
I0
I1
I2
I3
A0
A1
A2
A3
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.RegistersRegisters
D Q
R
Reset
D Q
R
D Q
R
D Q
RCLK
I0
I1
I2
I3
A0
A1
A2
A3
CLK
I3
I2
I1
I0
A3
A2
A1
A0
NoteNote: New data has to go in with every clock
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Registers with Parallel LoadRegisters with Parallel Load
Control LoadingLoading the Register with New Data
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0LD
LD Q(t+1)0 Q(t)1 D
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Registers with Parallel LoadRegisters with Parallel Load
Should we block the “Clock” to keep the “Data”?
D Q
CLK
I0 A0
D QI1 A1
D QI2 A2
D QI3 A3
Load
Delays the
Clock
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0LD
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Registers with Parallel LoadRegisters with Parallel Load
Circulate the “old data”
D Q
CLK
I0A0
D QI1A1
D QI2A2
D QI3A3
Load
MUXI0
I1
YS
MUXI0
I1
YS
MUXI0
I1
YS
MUXI0
I1
YS
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Shift RegistersShift Registers
4-Bit Shift Register
SerialInput Serial
Output
D Q D Q D Q D Q
CLK
SI SO
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Shift RegistersShift Registers
D Q D Q D Q D Q
CLK
SI SO
Q3
SI
Q2
Q1
Q0
CLK
Q3 Q2 Q1 Q0
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Serial TransferSerial Transfer
Shift Register ASI Shift Register BSO SI
ClockShift
Control
ShiftControl
CLK CLK
Clock
CLK
1010 / 28 / 28
Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Serial AdditionSerial Addition
FA
Shift Register A xyz
SC
Q D
CLR
CLK
ShiftControl
Clear
Shift Register B
SI
1111 / 28 / 28
Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Universal Shift RegisterUniversal Shift Register
Parallel-in Parallel-out
Serial-in Serial-out
Serial-in Parallel-out
Parallel-in Serial-out
D QD QD QD Q
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Universal Shift RegisterUniversal Shift Register
D
Q
D
Q
D
Q
D
Q
MUXI3 I2 I1 I0
YS1
S0
Q3 Q2 Q1 Q0
D1
S1
S0
CLKCLR
D0D2D3
SI for SR
SI for SL
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Universal Shift RegisterUniversal Shift Register
Q3 Q2 Q1 Q0
D3 D2 D1 D0
S1S0 USR
CLR
SRin SLin
Mode ControlMode Control Register Register OperationOperationS1 S0
0 0 No change0 1 Shift right1 0 Shift left1 1 Parallel load
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Ripple CountersRipple Counters
Ripple ↔ Asynchronous
TQ
CLR
TQ
CLR
TQ
CLR
TQ
CLR
Q3 Q2 Q1 Q0
CLK
CLR
1111
CLK
Q0
Q1
Q2
Q3
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Ripple CountersRipple Counters
DQ
Q
DQ
Q
DQ
Q
DQ
Q
Q3 Q2 Q1 Q0
CLK
CLK
Q0
Q1
Q2
Q30 1 2 3 4 5 6 7 8 9
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.BCD Ripple CounterBCD Ripple Counter
0000 0001 0010 0011 0100
1001 1000 0111 0110 0101
JQ
Q KCLK
1
1
JQ
Q K 1
JQ
Q K
1
1
JQ
Q K 1
Q3 Q2 Q1 Q0
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Decades CounterDecades Counter
BCDCounter
Q3 Q2 Q1 Q0
BCDCounter
Q3 Q2 Q1 Q0
BCDCounter
Q3 Q2 Q1 Q0
Count
1’s Digit1’s Digit10’s Digit10’s Digit100’s Digit100’s Digit
(CLK)
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Synchronous Binary CounterSynchronous Binary Counter
JQ
Q KCLK
EnableQ3 Q2 Q1 Q0
JQ
Q K
JQ
Q K
JQ
Q KTo
Next Stage
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Up-Down Binary CounterUp-Down Binary Counter
TQ
Q
Up
TQ
Q
TQ
Q
TQ
Q
Q3 Q2 Q1 Q0
Down
CLK
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.BCD CounterBCD Counter
0000 0001 0010 0011 0100
1001 1000 0111 0110 0101
Q3 Q2 Q1 Q0
E
0 0 0 0 0
0 0 0 0 0
1 1 1 1
1 1 1 1
11
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.BCD CounterBCD Counter
0000 / 0 0001 / 0 0010 / 0 0011 / 0 0100 / 0
1001 / 1 1000 / 0 0111 / 0 0110 / 0 0101 / 0
Q3 Q2 Q1 Q0
y E
0 0 0 0 0
0 0 0 0 0
1 1 1 1
1 1 1 1
11
2222 / 28 / 28
Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Binary Counter with Parallel LoadBinary Counter with Parallel Load
Q3
Q2
Q1
Q0
LD
I3
I2
I1
I0
Count
CLR LD Count Q(t+1)
0 x x 0
1 0 0 Q(t)
1 0 1 Q(t)+1
1 1 x I
CLR
Usually Asynchronous Clear
2323 / 28 / 28
Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.BCD Counter ExampleBCD Counter Example
Q3
Q2
Q1
Q0
LD
I3
I2
I1
I0
Count
CLR
0
0
0
0
A3
A2
A1
A0
1 CLK
Count
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Ring CounterRing Counter
10000001 0010 0100
2-bit counter
2-to-4 Decoder
T3 T2 T1 T0CLK
T0
T1
T2
T3
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Johnson CounterJohnson Counter
01110000 0001 0011
11111000 1100 1110
DQ
Q
CLK
DQ
Q
DQ
Q
DQ
Q
Q3 Q2 Q1 Q0
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.HomeworkHomework
Mano● Chapter 6
♦ 6-2
♦ 6-3
♦ 6-4
♦ 6-13
♦ 6-14
♦ 6-16
♦ 6-18
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.HomeworkHomework
6-2 Include a synchronous clear input to the “Register with Parallel Load”. The modified register will have a parallel load capability and a synchronous clear capability. The register is cleared synchronously when the clock goes through a positive transition and the clear input is equal to 1.
6-3 What is the difference between serial and parallel transfer? Explain how to convert serial data to parallel and parallel data to serial. What type of register is needed?
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.HomeworkHomework
6-4 The content of a 4-bit register is initially 1101. The register is shifted six times to the right with the serial input being 101101. What is the content of the register after each shift?
6-13 Show that a BCD ripple counter can be constructed using a 4-bit binary ripple counter with asynchronous clear and a NAND gate that detects the occurrence of count 1010.
6-14 How many flip-flop will be complemented in a 10-bit binary ripple counter to reach the next count after the following count:(a) 1001100111(b) 0011111111(c) 1111111111
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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.HomeworkHomework
6-16 The BCD ripple counter has four flip-flops and 16 states, of which only 10 are used. Analyze the circuit and determine the next state for each of the other six unused states. What will happen if a noise signal sends the circuit to one of the unused states?
6-18 What operation is performed in the up-down counter when both the up and down inputs are enabled? Modify the circuit so that when both inputs are equal to 1, the counter does not change state, but remains in the same count.
