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206 | P a g e
CHAPTER – 6
FABRICATION AND
CHARACTERIZATION OF
Al/n-CdS SCHOTTKY DIODES
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6.1 Introduction
Semiconductor devices are the basic components of integrated circuits and are
responsible for the startling rapid growth of the electronics industry in the past 50
years worldwide. Nowadays everyone is interested in high power and high
temperature devices. Because there is a continuing need for faster and more complex
systems for the information age, existing semiconductor devices are being constantly
studied for improvement, and new ones are being invented. Whether it is for higher
speed, lower power, higher density, higher Efficiency, or new functionality, the
number and types of semiconductor devices have been growing steadily in this
fascinating field. There now exists approximately 100 semiconductor devices,
depending on the definition of device [1].
Metal – Semiconductor (MS) contacts are an essential part of virtually all
semiconductor electronic and optoelectronic devices. One of the most important
properties of a MS interface is its Schottky barrier height (SBH).Ever since the second
half of the 20th century, many textbooks and articles were published with efforts to
unravel the Metal – Semiconductor mystery. The studies of semiconductor thin films
and crystals and their junctions such as metal-semiconductor junctions (Schottky
Barriers) and heterojunctions have received much attention due to their applications in
various electronic and optoelectronic devices including solar cells. Schottky diodes
are discrete devices with special functions in high power electronics and other
integrated circuitry; they are basic building blocks for many transistors such as
MOSFETs etc. Due to their high frequency behavior, Schottky barrier diodes (as
opposed to pn-junction diodes) are being extensively used in different applications
such as high frequency switches, gas sensors, mixers, microwave circuits and UV
detectors. Schottky barrier diodes are one of the simplest electronic devices in the
semiconductor industry. The main advantage of these diodes is their high current
density and low forward voltage drop. Primarily the current flow in these diodes is
due to the majority carriers having an inherently fast response. The current-voltage
characteristics of Schottky diodes are similar to ordinary p-n junction diodes.
Moreover, metal-semiconductor (MS) contacts are the most common form of
junctions in integrated circuits. Therefore, research efforts regarding the interaction of
semiconductor surfaces with deposited metals are very important for understanding
many developmental aspects of the microelectronic devices. The great majority of
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metal-semiconductor junctions are used for ohmic contact. Ohmic contact has a very
low resistance to make the electrons and holes move freely in and out of the devices.
The other type of metal-semiconductor contact has a rectification capability, with a
large current in forward bias and a very low leakage current in reverse bias and is
called Schottky diode. Metal-semiconductor structures are important research tools in
the characterization of semiconducting materials and fabrication of such type of
structures plays an important role in the realization of some useful devices [2]. The
physical properties of the interfaces between metal and semiconductors depend on
surface preparation conditions [3, 4].
Many models have been developed to understand the origin and behavior of
potential barrier at the interface of M-S contacts by various workers. But significant
efforts are still being made on ways and means to arrive at a more realistic
interpretation of characterizing parameters of real Schottky diodes [5-8]. Depending
upon relative positions of the Fermi level of the forming metal and the semiconductor
used, the requirement of equilibrium gives two types of contacts, rectifying (Schottky)
contact and ohmic contact. An ohmic contact is like a typical resistor thus providing a
means to connect the semiconductor directly to the outside world with some loss due
to the resistance. Ohmic contacts are considered to have symmetrical and linear I-V
characteristics while rectifying contacts possesses non-reciprocal and non-linear I-V
characteristics. Metal-Semiconductor Schottky diodes are majority carrier devices and
hence they posses small charge storage time leading to fast electrical responses. The
total absence of minority carrier storage time made the Schottky contact an ideal
device for surge protection, switching application, microwave detector, mixer etc. [9,
10]. The Schottky contacts have now occupied major place among the devices used in
modern electronic systems.
6.2 Metals-Semiconductor Contact
Metal-Semiconductor contacts are of great importance because they are
always present in every semiconductor device in any of its two forms i.e. ohmic or
rectifying. Thus, Metal-Semiconductor contacts have become an important member of
the device families of the modern electronic systems. When a metal makes an intimate
contact with a semiconductor and a thermal equilibrium is established, a metal-
semiconductor junction is formed. Metal-semiconductor junctions are of great
importance since they are present in every semiconductor device. They can behave
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either as an ohmic contact or as a rectifying contact called Schottky barrier depending
on the characteristics of the interface. A large number of metal/II-VI semiconductors
have been studied by many researchers due to several interest properties of II-VI
group and different devices applications. Although great efforts have gone into
providing a systematic study of this seemingly simple system over the years, a
complete determination of the detailed mechanisms responsible for Schottky barrier
formation and charge transport across it have still proven quite elusive [11-16].
6.2.1 Ohmic Contact
The term "ohmic" refers in principle to a metal-semiconductor contact, which
is non-injecting and has a linear current-voltage characteristic in both directions of
current flow. In practice, the contact is usually acceptable if it can supply the required
current density with a voltage drop which is very small compared to that across the
active region of the device; even though its behaviour may not be strictly linear.
Metal-semiconductor contacts are said to be ohmic when the charge induced in the
semiconductor in aligning the Fermi levels is provided by the majority carriers. For
example in the case of metal - n type semiconductor junction, the Fermi levels are
aligned at equilibrium by transferring electrons from the metal to the semiconductor.
This transferring of electrons raises the electron energy levels in the n type
semiconductor relative to the metal at equilibrium. With Φm < Φs, the barrier to the
electron flow between the metal and the semiconductor is very small and easily
overcome by a small voltage. Thus, the junction effectively acts as a linear resistor.
Conversely for a p type semiconductor, Φm > Φs results in easy hole flow across the
junction. Energy band diagram of such a junction is illustrated in the figure 6.1 and 6.2.
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Figure 6.1: Ohmic contact between a metal and an n-type semiconductor with Φm<
Φs (a) band diagrams before joining (b) equilibrium band diagram for the junction.
Figure 6.2: An Ohmic contact between a metal and p-type semiconductor with Φm>
Φs (a) band diagrams before joining (b)equilibrium band diagram for the junction.
6.2.2 Schottky Barrier Contacts
When there is a barrier at the metal-semiconductor junction affecting the flow
of carriers, allowing an easier flow in one direction and hard flow in the opposite
direction, the barrier is called Schottky Barrier. The metal–semiconductor contact was
one of the first practical semiconductor devices showing rectifying characteristic
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when the metal work function (Φm) (n- type semiconductor) is greater than the
semiconductor work function (Φs), as shown in the figure 6.3 (a). If metal and
semiconductor materials are in contact and under thermal equilibrium (no current
flow) the Fermi levels of both must be at the same energy level and constant
throughout this system figure 6.3(a) ,(b) and (c).
Figure 6.3: Formation of Schottky barrier from metal and semiconductor (n-type); (a)
Energy band diagram of isolated metal and n-type semiconductor; (b) separated by a
narrow gap;(c) perfect contact.
In actual practice, the ideal condition for metal-semiconductor intimate contact
is never reached because there is usually a thin insulating layer of oxide called
interfacial layer on the surface of the semiconductor. The barrier presented by this
layer is thin enough such that electrons can easily tunnel through it.
Based on the theory of Schottky and Mott [17, 18], the barrier height b is
defined as the potential difference between the Fermi energy of the metal and the
band edge where the majority carriers reside. From figure 6.3 one finds that for a n-
type semiconductor the barrier height is obtained as , Φm
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Φbn=(Φm – χs) 6.1
Where is Φm the work function of the metal and is the electron affinity. For p-type
material, the barrier height is given by the difference between the valence band edge
and the Fermi energy in the metal:
Φ
χ Φ 6.2
A metal-semiconductor junction will therefore form a barrier for electrons and
holes if the Fermi energy of the metal as drawn on the flat band diagram is
somewhere between the conduction and valence band edge. In addition, we define the
built-in potential, Φi as the difference between the Fermi energy of the metal and that
of the semiconductor.
Φ χ
6.3
χ
Φ 6.4
This theory of Schottky and Mott is rather simplistic in the sense that it
assumes ideal conditions. The experimental barrier heights often differ from that
calculated using equation 6.1 or 6.2. This is due to the non- ideality imposed by the
metal-semiconductor interface. The ideal metal-semiconductor theory assumes that
both materials are infinitely pure and there is no interaction between the two
materials. It is also assumed that there is no interfacial layer between the contacting
metal and semiconductor surface. One of the first explanations for the departure of
experimental observations from this theory was given in terms of localized surface
states or dangling bonds. This is because at the surface of a solid the atoms have
neighbors on one side only. This causes a distortion of the electron cloud belonging to
the surface atoms, so that the centers of the positive and negative charges do not
coincide. This means that, in practice, surface dipole layers do form. It is observed
that Φb does not depend on Φm which is in contradiction to equation 6.1. Thus, the
assumption of constancy of the surface dipole cannot be justified. The surface states
are continuously distributed in energy within the forbidden gap and are characterized
by a neutral level, Φ0, such that if the surface states are occupied up to Φ0 and empty
above Φ0, the surface is electrically neutral. In general, the Fermi level does not
coincide with the neutral level. In this case, there will be a net charge in the surface
states. If, in addition, there is a thin oxide layer between the metal and the
semiconductor the charge in the surface states together with its image charge on the
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surface of the metal will form a dipole layer which will alter the potential difference
between the semiconductor and the metal. Thus, the modification to the Schottky-
Mott theory can be expressed as follows [19].
Φ Φ χ Φ 6.5
Where, Eg is band gap of the semiconductor in eV and Φ0 is position of neutral level
(measured from the top of the valence band),
6.6
Where, εi is the permittivity of oxide layer, δ is thickness of oxide layer and Ds is
density of surface states.
Hence, if there are no surface states, Ds = 0; 'γ = 1 and equation 6.5 becomes
identical to equation 6.1, which is the original Schottky-Mott approximation. But if
the density of states is very high, 'γ becomes very small and Φb approaches the value
Eg−Φ0.This is because a very small deviation of the Fermi level from the neutral level
can produce a large dipole moment, which stabilizes the barrier height by a negative
feedback effect [20]. When this occurs, the Fermi level is said to be "pinned" relative
to the band edges by the surface states.
6.3 Charge Transport Mechanisms across Schottky Barrier
The current across the Schottky junction is mainly due to majority carriers.
Once a Schottky barrier has formed there are four main transport mechanisms for an
electron to overcome the potential barrier. For an n-type semiconductor in forward
bias, figure 6.4 shows the transport mechanisms for an electron to overcome the
Schottky barrier. These mechanisms are:
a) Emission of Electrons from The Semicocnductor over The Top of The Barrier
into The Metal;
According to this mechanism, for transport of majority carriers over the
Schottky barrier, they must be transported from interior neutral region of the
semiconductor to the interface. The usual process for this is the drift and
diffusion through the space charge region. Therefore the emission of such
carriers over the barrier may be either limited by their transport up to the
interface or by their capability of crossing the barrier after arrival at the
interface.
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b) Quantum-Mechanical Tunneling through The Barrier;
Tunneling from the neutral regions of the semiconductor will have a
significant probability in the forward biased case only when doping
concentration is so high as to make the barrier very thin.
c) Recombination in The Space-Charge Region;
This occurs through the localized centers within the space charge region.
However, most effective recombination centers are the one lying near the
centre of the semiconductor band gap.
d) Recombination in The Neutral Region (‘Hole Injection’);
In case where Schottky barrier height is more than the semiconductor band
gap, the nature of the semiconductor near the interface may be inverted and as
a result minority carrier injection into the neutral region of the semiconductor
may assume significance.
Figure: 6.4: Charge transport processes in a forward-biased Schottky diode.
6.4 Schottky Diode Current
The current transport through the device by emission over the barrier is
essentially a two-step process: first, the electrons have to be transported through the
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depletion region, and this is determined by the usual mechanisms of diffusion and
drift [21, 22]; secondly, they must undergo emission over the barrier into the metal
[23], and this is controlled by the number of electrons that impinge on unit area of the
metal per second. Quantum - mechanical tunneling through the barrier takes into
account the wave-nature of the electrons, allowing them to penetrate through thin
barriers [24, 25]. In a given junction, a combination of all three mechanisms could
exist. However, typically one finds that only one mechanism limits the current,
making it the dominant charge transport mechanism.
6.4.1 Thermionic Emission (Rectification)
The thermionic emission theory assumes that the current is controlled only by
the transfer of carriers across the top of the barrier; provided they move towards the
barrier and the drift and diffusion that occur as a result of collisions within the space
charge region are considered unimportant. The actual shape of the barrier is hereby
ignored. For an n-type semiconductor under forward bias assuming qΦb>>kT, the
electrons emitted over the barrier from semiconductor into the metal will be in
equilibrium with the electron population in the semiconductor and thus will have a
Maxwellian energy distribution. The resultant current ‘ITE’ due to thermionic emission
for an applied bias ‘V’ (measured +ve with respect to the n-type semiconductor) is
given by S. M. Sze [16],
Φ
6.7
Where, A is cross-sectional area of the metal - semiconductor interface, A* is
Richardson constant for metal - semiconductor interface
6.8
6.9
Here me* and mh* are effective masses of the electrons holes, T is temperature
in Kelvin, k is Boltzmann constant, h is Plank’s constant, q is electronic charge, V is
effective bias across the interface and is the Schottky barrier height. If the barrier
height is assumed to vary linearly with bias, one writes,
6.10
Where is the barrier height at zero bias and is positive. γ (= ∂Φb /∂V)
Substituting (6.10) in equation (6.7), equation (6.7) becomes,
6.11
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Where,
6.12
ITE0 is termed as thermionic emission saturation current,
6.13
Now, introducing a parameter n such that l/n = 1 - γ, equation 6.11 can be
written as,
6.14
Thus, the current is zero if no voltage is applied as in thermal equilibrium any
motion of carriers is balanced by a motion of carriers in the opposite direction. The
parameter n, in equation 6.14 gives a measure of the quality of the junction called
ideality factor. For an ideal Schottky junction, when n = 1 (or γ = 0), equation 6.14
reduces to the case of pure thermionic emission-diffusion. This mode of current
transport is commonly referred to as the "thermionic emission" current [26, 27]. In
practice, however, larger values for n are obtained due to the presence of non-ideal
effects or other contributing components to the total current through the junction.
Normally, the neutral region of the semiconductor, between the depletion
region and back ohmic contact, offers resistance (Rs) and so a significant voltage drop
(= IRs) occurs across it at large forward currents. This amounts to a reduction of the
voltage across the barrier region from that actually applied to the terminals of the
diode. This is accounted for by replacing V by V – IRs in equation 6.14. The current
equation then becomes,
6.15
6.4.2 Quantum Mechanical Tunneling
It may be possible for the electrons having energies below the barrier height to
penetrate the barrier by quantum mechanical tunneling under certain conditions. One
type is known as field emission and the other, thermionic field emission.
6.4.3 Field Emission and Thermionic Field Emission
As the concentration of the dopant is increased in the semiconductor, another
mechanism for current flow across a metal – semiconductor interface becomes
important. With decrease in depletion layer width with increasing doping, probability
of quantum mechanical tunneling of electrons through the barrier increases. At very
high doping, the barrier can be thin enough to permit appreciable field emission at the
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bottom of the barrier. At moderately high doping, the barrier is somewhat wider.
Hence, those electrons with sufficient thermal energy can tunnel near the top
of the barrier to produce an appreciable current. This latter process is known as
thermionic field emission. Field emission is independent of temperature, while
thermionic field emission is temperature dependent. The transmission probability P
for an electron of energy E to successfully tunnel through a triangular shaped
potential energy barrier with diffusion potential Vd is given by [16].
6.16
Where,
6.17
6.17a
E00 is the tunneling parameter having the dimensions of energy, which is
inherently related to material properties of the semiconductor and is very useful in
determining the range of doping and temperature for which field emission, thermionic
field emission or thermionic emission is valid [26].
Assuming uniform doping concentration ND, complete depletion of the space
charge region and ignoring image force lowering, analytical expression for the I-V
characteristics by Padovani and Stratton can be summarized as follows.
1. At very high doping or at low temperatures, where E00 >> kT
6.18
Where,
IFE – The resultant current due to field emission for an applied bias V and
I0FE – The field emission saturation current
2. At moderate temperatures and doping levels where E00 ≈ kT, we obtain
6.19
Where,
ITFE –The resultant current due to thermionic field emission for an applied bias V
I0TFE – The thermionic field emission saturation current
Here
6.20
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3. At temperatures or low doping where E00 << kT, the carriers are thermionically
emitted over the barrier and the current can be expressed as
6.21
Where,
ITE – The resultant current due to thermionic emission for an applied bias V
I0TE – The thermionic emission saturation current
In brief, taking the expressions for the three dominant mechanisms, the current
is determined by [28],
For TE 6.22
For TFE 6.23
For FE 6.24
Thus,
For
dominates and the contact is rectifying; 6.25
For
, FE dominates and the contact is ohmic; 6.26
For
TFE dominates and a mixed mode prevails for the conduction. 6.27
Hence, FE and TFE are caused due to quantum mechanical tunneling of
electrons through the barrier. Note that both TE and TFE are temperature dependent
while FE is not.
6.5 Other Current Transport Mechanisms
In addition to thermionic emission and quantum mechanical tunneling, there
are a number of other effects and current transport mechanisms, which also contribute
to the electrical properties of the metal semiconductor interface albeit to a much lesser
extent. These include generation - recombination effects, leakage and barrier
inhomogeneity etc.
6.5.1 Generation-Recombination Effects
Generation - recombination effects within the depletion region give rise to a
parallel component to the thermionic emission current transport mechanism. This is
particularly significant at moderately low temperatures. The current contribution,
‘IGR’, due to this mechanism can be represented by [27],
6.28
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Where,
6.29
6.30
6.31
Where, IGRO is generation-recombination saturation current, w is thickness of the
depletion region, is the carrier effective lifetime within the depletion region, ni is the
intrinsic carrier concentration, Nc is the effective conduction band density of states
and Nv is the effective valence band density of states .
6.5.2 Barrier Lowering Due to Image Force Effects
The electric field in the semiconductor may be considered to be identical to
that of the carrier itself and another carrier with opposite charge at equal distance but
on the opposite side of the interface (figure 6.5). Consider an electron, in vacuum, at a
distance x from a metal surface. A positive charge will be induced on the metal at a
distance -x from its surface. This charge is called the image charge and will give rise
to an attractive force between the two, known as the image force. This force has
associated with it an image potential energy which corresponds to the potential energy
of an electron at a distance x from the metal. When an external field, Eext, is applied
this electric field causes the image-force-induced lowering of the potential energy for
charge carrier emission [16]. Thus, at high fields, the Schottky barrier is considerably
lowered. The difference between the actual surface charges and the image charge is
that the fields in the metal are distinctly different. The image charge concept is
justified on the basis that the electric field lines are perpendicular to the surface of a
perfect conductor, so that, in the case of a flat interface, the mirror image of the field
lines provides continuous field lines across the interface. The amount of reduction due
to the induced image force ΔΦ imf is given by [3, 29],
Δ
6.32
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Figure: 6.5: (a) Field lines and surface charges due to an electron in close proximity
to a perfect conductor (b) the field lines and image charge of an electron.
6.5.3 Leakage Current
The leakage current IL is another parallel component of the total current. It is
caused by surface leakage and can usually be significantly reduced by various designs
and fabrication techniques e.g. guard ring structure etc. In practice, it is the
component, which appears to by-pass the metal/semiconductor interface altogether
and is often thought of as a large leakage resistor, RL, in parallel to it. Thus the
leakage current can be expressed as:
6.33
6.5.4 Barrier Height Inhomogeneity
It has been reported that the increase in ideality factors (n > 1) of abrupt
Schottky contacts without interfacial layers between the metal and a moderately
doped semiconductor may be due to the spatial / lateral inhomogeneity at the metal –
semiconductor interface (figure 6.6). This inhomogeneity can be explained by using
an analytical potential fluctuation model based on spatially inhomogeneous barrier
height at the interface [13, 30].Suppose that the distribution of the barrier height is
Gaussian in character [P(b)] with a standard deviation σs. So the Schottky barrier
b depend on the location within the interface plane with this barrier distribution
P(b), around the mean Schottky barrier b
. The Gaussian barrier distribution can be
expressed as:
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6.34
This expression is normalized from ∞− to ∞+, as
6.35
Thus, the term
of equation 6.34 is the normalization constant of the
Gaussian barrier height distribution.
Now, the current across a homogeneous Schottky barrier at a forward bias V,
when V>3kT/q, based on the thermionic emission theory is given by (E. H.
Rhoderick, 1988):
* 2 0exp expsb
q V IRqI AA T
kT nkT
6.36
According to Werner and Guttler the net current I through an inhomogeneous
Schottky contact is controlled by the effective / apparent barrier height ap and the
corresponding ideality factor is nap. For most non homogeneous Schottky diodes, the
current – voltage characteristics can still be well described with the help of the
thermionic emission theory, except that 0b and n should be replaced by ap and nap
in equation 6.35.
Figure 6.6: The band diagram of an inhomogeneous Schottky contact
(Ref : Werner 1991)
Considering equations 6.35 and 6.36 to describe the inhomogeneities of abrupt
Schottky junctions, the total current I can be expressed as,
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22* exp exp 1 exp
2
sb
ap
qq qV qVI(V)= A T
kT kT n kTA
kT
6.37
With
* 2
0 expapq
I AA TkT
6.38
The apparent barrier height ap and ideality factor (nap) at zero bias are given
by [13,31,32]
2
0
0( 0)
2ap b
qT
kT
6.39
and
kT
q
nap 21
1 3
2
6.40
The temperature dependence of σs is usually small and thus can be neglected.
However, σs and b
are assumed to be linearly bias dependant on Gaussian
parameters such that
20bbV 6.41
And
0 3s V 6.42
where 2 and 3 are the voltage coefficients that may depend on temperature and
they quantify the voltage deformation on the barrier height distribution [31, 33].
Thus, the standard deviationS , and hence the parameter
0 can be considered as a
measure of the barrier inhomogeneity.
6.6 Fabrication of Al/n-CdS Crystals Schottky Diodes
6.6.1 Selection of Material
As per our literature survey, the devices like Schottky barrier diodes of Al
based on CdS thin films has been studied by a very few researchers. But such devices
based on crystals CdS have not been studied. As a result of that, Al based on CdS
crystals have been selected for this study. As based on the importance of CdS that
have already been pointed out in chapter 1 .an extra incentive to do research on this
device that is include;
1. Very limited numbers of current-voltage investigations were made on CdS
based Schottky barrier systems over wide temperature ranges.
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2. Very limited numbers of capacitance-voltage investigations were made on
CdS based Schottky barrier systems over wide temperature ranges and
different frequency.
3. Most of the earlier reported work is based on Schottky barrier devices
fabricated by deposition of metal thin films on CdS thin films[34,35], and till
today there is no report on Al thin film Schottky diode based on CdS crystals .
Hence that was incentive to do research on this device, we have decided to study
crystals CdS based Schottky barrier devices and to study their conduction mechanism.
A metal chosen was Al.
Aluminum is the most plentiful metal in the earth crust and never occurs in the
free form. It is obtained by electrolysis from bauxite (Al2O2). Al is silvery, light
weight, non-magnetic, non-sparking, malleable metal with atomic number 13. It has
cubic face centered structure with atomic radius of 1.82Å and atomic volume of
10cm3/mole. The electron work function of Al is 4.28eV and the melting point is
933.4K. Its electric and thermal conductivities are 0.377 × 106 Ω.cm and 2.37 W/cm K
respectively. Its density is 2.702 g/cc at 300K and the coefficient of linear thermal
expansion is 2.39 ×10-7
cm/cm/ºC (0 ºC) [36].
6.6.2 Metal Deposition Using Thermal Evaporation Technique
Initially crystals of CdS with flat surfaces, chosen with the help of optical
microscope, were washed in acetone to remove contaminations and to make the
surface clean; and later they were dried in the oven at 60 0C. The cleaned crystals
were mounted on the substrate holder inside the vacuum chamber. Aluminum metal
thin films were deposited using thermal evaporation technique. For this purpose,
vacuum coating unit model: 12A4D (Make: Hind High Vacuum Co. Ltd. Bangalore)
was used. The schematic diagram and photograph of the deposition system is shown
in figure 6.7(a-b).
The complete deposition process of Al thin films by thermal evaporation
technique can be divided into three major stages as mentioned bellow.
i. Transformation of solid material, to be deposited, into gaseous form.
ii. Transport of the created material, to the substrate, from the evaporation
source, in the form of vapor stream and
iii. Deposition of the material on the substrate and growth of the film or crystal .
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In reference to these steps, the requirement of the thermal evaporation
technique can be discussed.
In the first stage, the transformation of the material takes place from solid to
gaseous state. For example, if this is to be accomplished by resistive heating, then it is
always essential that the material of the evaporation source (i.e. boat) should
withstand very high temperatures (which are always greater than the melting/boiling
point of the material to be evaporated). In addition, the power supply used for such
resistive heating should be capable of delivering enough current to the boat so that it
reaches these high temperatures conveniently.
In the second stage, the transport of the gaseous form of the material from the
evaporation source to the substrate takes place. This process can be better
accomplished only if the mean free path of the evaporated gas molecules is greater
than the distance between the evaporation source and the substrate. If this condition is
not fulfilled, then the vapor molecules will be diverted from their normal path due to
collisions with the ambient gas molecules or among themselves. Therefore, it is
always essential that the pressure in the chamber should be reduced substantially.
(The normal desired pressure is always less than 10-5
torr.)
In the third stage, the nucleation and condensation of the vapor molecules on
the substrates takes place to form a continuous film. This process can be optimized if
the rate of incidence of the vapor molecules at the substrate is kept less than the rate
of nucleation. Besides, it is always essential that the rate of impingement of the
ambient gas molecules should be very small compared to that of the evaporated
molecules in order to minimize the incorporation of impurities in the thin film.
The system comprises of conventional diffusion pump backed by a direct
drive rotary pump of pumping speed 300 lit/sec. The diffusion pump is of diffstack
type with liquid nitrogen trap, water cooled chevron and has a pumping speed of
500 lit/sec. The ultimate vacuum achievable by the system is ~ 10-7
torr, which is
measured at various stages by Pirani and Bayard-Alpert gauges. The main gadgetries
in the work chamber consist of thermal evaporation sources and flash evaporator
assembly with high tension (HT) ion cleaning facility. It also consists of rotary
substrate holder for obtaining uniform thickness over large substrate area. Operating
roughing, backing and baffle valves and pouring liquid nitrogen in the trap in a proper
sequence is required for attaining ultimate vacuum in minimum time. The vacuum
chamber after loading the substrates to be coated may be allowed to follow ion-
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cleaning process. For this, the required level of vacuum is about 10-2
to 10-3
torr. It is
desirable to heat the system up to around 250°C for about half an hour to remove the
impurities adsorbed on to the walls of the chamber and then flushed by an inert gas
before going to high vacuum, for which a high purity argon gas cylinder can be
connected to the main chamber and the flow can be controlled by a needle valve.
This is because of the fact that contamination free and chemically non-interacting
processes are necessary to be pursued particularly in case of semiconductor devices,
the vacuum system after achieving the ultimate vacuum is normally isolated from the
pumping system and then the thin film deposition process may be initiated. The
vacuum level can be monitored by Pirani gauge and ultimate pressure is measured
with the help of Bayard Alpert ionization gauge for better accuracy.
In order to get evaporated metals on a confined area on the CdS crystals;
crystals were masked with specially designed thin mica sheet mask having circular
holes of area of 0.196 cm2. After reaching a vacuum level of the order of 10
-6 torr,
pure aluminum metal was evaporated to achieve thickness of 5 kÅ from a Whelical
boat onto the grown CdS crystals surface. The rate of evaporation was kept very slow
i.e.2 Å/Sec in order to make the deposition uniform over the whole area. Thus, Al/n-
CdS Schottky barrier diodes of area 0.196 cm2 were fabricated. In addition, this
definitely gives good adhesion and other desirable properties in the Schottky diode
fabrication by relatively slower growth mechanisms. Since silver gives good ohmic
contact to n-CdS, the ohmic contacts were drawn again by bonding Ag alloy wires
(LakeShore sample wires PN 671-260) using Ag paste (Eltec-1228C) onto the surface
of CdS crystal. Front Schottky contacts with evaporated aluminum regions were taken
by bonding low strain thin Ag alloy wires (LakeShore sample wires PN 671-260)
using Ag paste (Eltec-1228C).
226 | P a g e
Figure 6.7 :( a) Photograph and (b) Schematic of vacuum coating unit
(Model: 12A4D).
227 | P a g e
External contacts from Ag were taken through copper wires using conducting
silver paste (Eltech-1228 C). Schottky barrier diodes based on CdS crystal of different
thickness, thickness 0.314 and 0.421 mm were prepared in order to study the charge
transport mechanism in these diodes. The structure diagram of fabricated Al/n-CdS
crystal Schottky diodes of area 0.196 cm2 are shown in figure 6.8.
Figure 6.8: The structure diagram of fabricated Al/n-CdS crystal Schottky diode of
area 0.196 cm2.
6.6.3 Current-Voltage-Temperature(I-V-T) Measurements
There are various methods for the determination of Schottky barrier
parameters. They are Current – voltage (I-V) analysis, Capacitor – voltage (C-V)
analysis, Photoelectron spectroscopy method, Activation energy method etc. [16, 19, 37].
I-V analysis method is the basic and simplest of all methods since it involves direct
measurement of current voltage and provides first hand information about the nature
of the developed barriers across the interface. In the present investigation the I-V data
were acquired using Keithley – Semiconductor Characterization System SCS-4200.
6.6.3.1 Keithly 4200 Semiconductor Characterization System
Keithley 4200 can be used for I-V measurement in wide current range for the
fabricated Schottky barrier diodes. In the present investigation the I-V-T and C-V-T
data were acquired using Keithley Semiconductor Characterization System SCS-4200
along with HP-4284A LCR meter. The Model 4200-SCS provides a total system
228 | P a g e
solution for DC characterization of semiconductor devices, test structures and
materials. This advanced parameter analyzer provides intuitive and sophisticated
capabilities for semiconductor device characterization. The Model 4200-SCS
combines unprecedented measurement speed and accuracy with an embedded
Windows NT-based PC and Keithley Interactive Test Environment (KITE) to provide
a powerful single-box solution. KITE allows users to gain familiarity quickly with
tasks such as managing tests and results and generating reports. Sophisticated and
simple test sequencing and external instrument drives simplify performing automated
device and wafer testing. The Keithley Model 4200 Semiconductor Characterization
System (SCS) [38] can be programmed to characterize I-V and C-V of semiconductor
devices and test structures, using up to eight Source- Measure Units (SMUs). A
variety of supported external components enhance the capabilities. The exceptional
low current performance of the Model 4200-SCS makes it the perfect solution for
research studies of single electron transistors (SETs), molecular electronic devices
and other Nano electronic devices that requires I-V characterization. Figure 6.9 shows
the complete block diagram of Keithley Model 4200 Semiconductor Characterization
System (SCS). The variation of current and voltage with temperature were
accomplished by single zone small furnace along with temperature controller (Omron
E5CZ). Keithley 4200 – Semiconductor Characterization System (SCS) is a versatile
instrument, in which the start, stop and step for current or voltage values of the
SMU’s are assigned initially. The switching of the terminals is to be connected to the
device can be done using switch matrix unit coupled to the respective SMU’s.
When these variables were set ready, temperature was also set constant at the
desired level using temperature controller and the data obtained were stored as
spreadsheet in the computer memory. The experiment was repeated at different
temperatures from room tempertuer upto 493K in steps of 10K. The results can be
observed either in the table form or in the graphical form and may be edited as
needed. It also allows saving comma-separated values in text files that can be easily
imported into most analysis and spreadsheet programs such as excel or origin.
Provisions are also there to save the test configuration being done. In the present
investigation, adopting I-V-T and C-V-T as the measurement technique, various
Schottky barrier parameters were calculated by standard methods as discussed in the
next section.
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Figure 6.9: Block diagram of Keithley Semiconductor Characterization System
Model 4200-SCS.
6.7 Results and Discussions
In the present investigation, adopting I-V as the measurement technique,
various Schottky barrier parameters were calculated by three different methods. They
are [3, 39-41]:
i. LnI versus V plot.
ii. Norde method.
iii. Cheung method.
6.7.1 I-V-T Analysis Using Different Methods
6.7.1.1 Line versus V Plot
The plot of LnI vs. V yield a straight line for V > (3kT/q) and this may cover
two to three decades of change in current at low forward bias voltages. The intercept
on y-axis of this straight line gives the value of saturation current ‘I0’. From this ‘ɸb0’
can be calculated using the equation,
6.43
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Also from the slope of the LnI vs. V plot, the ideality factor ‘η’ can be
calculated as,
6.44
The more realistic representation of barrier potential is done if the bands are
flat across the interface. Under this condition the barrier potential as designated by flat
band barrier height and is given by [42],
6.45
Here ‘ND’ is the carrier concentration of CdS crystal obtained from Hall Effect
measurement as described in chapter 5. ‘NC’ is the effective density of states in the
conduction band, which is given by [3],
6.46
Where, ‘me*, is the effective mass of CdS and is given by 0.21m0 [43]. Here ‘m0 , is
the rest mass of electron (9.1x10-31
kg), ‘k’ is Boltzmann’s constant (1.3808 x 10-23
J/K or 8.6175 x 10-5eV), ‘T’ is the temperature in K and ‘h’ is Plank’s constant.
The total current passing through a Schottky barrier device may be because of
one or a combination of several conduction mechanisms as discussed in the beginning
of this chapter. The general understanding of dominant charge transport mechanism
can be done by the comparison of the magnitude of energy characteristics E00 with
that of kT/q. The value of E00 can be calculated from the equation 6.17a. Since ND is a
temperature dependent parameter the value of E00 calculated for different temperature
regions. The variation of E00 for different values of ND is plotted in figure 6.10. The
result shows that in these temperature ranges
and TE conduction
mechanism has been identified as the dominant charge transport mechanism.
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Figure 6.10: Variation of E00 as a function of change in ND observed at different
temperatures.
These diodes were analyzed in the temperature range 303 K - 493 K and 293 -
433K for the two diodes denoted by ‘a’ and ‘b’ respectively. The two prepared
devices were subjected to I-V measurements at room temperature. Figures 6.11 show
the I-V characteristics of room temperature rectifying nature, indicating proper
formation of the junction. The rectification ratios were of around 31.6 and 3.5 at
1 volt, which measured at room temperature for diode ‘a’ and diode ‘b’ respectively.
It can be seen from here that the prepared diode ‘a’ have a good rectification
characteristic and diode ‘b’ have a poor rectification characteristic. Figure 6.12 (a)
and (b) represents the I-V plots of fabricated diodes at various high temperatures.
Figure 6.13 (a) and (b) represents the forward and reverse bias LnI – V characteristics
(known as Gamma plot) for prepared Schottky diodes at different temperatures.
The forward current–voltage characteristics as shown in (figure 6.14) can be
classified into two regions according to the applied voltages. In region above 0.6 V,
the forward current deviates from linearity due to the effect of a series resistance and
interfacial layer on the Al/n-CdS structure. In region below 0.6 V, the temperature
dependence of the forward currents was analyzed by using a simple Schottky model.
232 | P a g e
In this model, the carrier transport occurs across the barrier by thermionic
emission, the drift and diffusion of carriers within the depletion region are less
important. Using the intercept on y-axis of straight line curve (below 0.6 V) obtained
from these plots figure 6.14(a) and (b) at low forward bias voltages we have obtained
the value of saturation current (I0). From the obtained values of I0 and using equation
6.43 we have calculated values of zero bias barrier height ( bo). We have also
evaluated values of ideality factor (η) and flatband barrier height (bf) using these
plots as well as equations 6.44 and 6.45.
The results obtained in this analysis are shown in table 6.1 and 6.2. The
temperature dependent characteristics for ideality factor and barrier height are shown
in figure 6.15(a) and (b) for these diodes. It has been observed from these figures
that the ideality factor decreases while zero bias barrier height and flat band barrier
height increases with increasing temperature in case of both the diodes. The diode
ideality factors of both diodes have been found to be greater than unity are generally
attributed to the presence of a bias dependent Schottky barrier height.
There may be variety of causes [13, 31, 34, 44-52], which lead n to exceed
unity. Some of the main causes are:
i. The presence of Interfacial oxide layer or any thin insulating layer between the
metal and the semiconductor may be responsible for a higher ideality factor and
image force affect the barrier and therefore the effective current with applied
voltage,
ii. Inhomogeneity of thickness and composition of the layer, non-uniformity of the
interfacial charges or Surface defects produce electronic energy levels in the band
gaps of CdS semiconductor. These levels can pin the Fermi energy at metal-
semiconductor interface and caused the formation of Schottky-barrier junction
iii. Recombination of electrons and holes due to surface states, defects etc gives rise
to component of current with n greater than unity in addition to thermoionic
emission current. At higher bias, there may be increase in n because of drift and
diffusion in the barrier region.
iv. The high series resistance causes the actual voltage drop across the barrier region
to be less than the voltage applied to the terminals of the diode.
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Figure 6.11: Room temperature I-V curves of the two prepared Al/n-CdS Schottky
diodes ‘a’ and ‘b’ respectively.
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Figure 6.12: I-V plots of fabricated Al/n-CdS Schottky diodes ‘a’ and ‘b’ as measured
at different high temperatures.
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Figure 6.13: Temperature dependent forward and reverse bias Ln I-V (Gamma Plot)
characteristics for prepared Al/n-CdS Schottky diodes ‘a’ and ‘b’ respectively.
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Figure 6.14: Temperature dependent forward bias Ln I-V characteristics at various
temperatures for prepared Al/n-CdS Schottky diodes ‘a’ and ‘b’ respectively.
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Figure 6.15: Plot of ideality factor, zero bias barrier height and flat band barrier
height as a function of temperature for Al/n-CdS Schottky diodes ‘a’ and ‘b’
respectively.
238 | P a g e
The current transport at the metal / semiconductor interface is a temperature
activated process and at a microscopic scale Schottky barriers are assumed as an
assembly of patterns of different barrier height regions at the interface. Thus, at lower
temperatures conduction through smaller barrier patches dominates and that accounts
for the larger ideality factor. As the temperature increases, more and more electrons
are likely to have sufficient energy to surmount even larger barriers. As a result, the
dominant barrier height will increase with the temperature and bias voltage. Thus,
both BH and ‘η’ are strongly dependent on temperature. Moreover, it has been
observed from simulation studies on mixed-phase Schottky contact that, below a
critical size, low BH region is pinched off and high barrier remains effective [53].
Schmitsdorf et al [54] used Tung’s theoretical approach and they found a linear
correlation between the experimental zero-bias BH and ideality factors n. Figure 6.16
(a) and (b) shows the plot one can see that the ideality factor has a homogeneous BH
of 1.29 and 1.25 by extrapolating of both diodes ‘a’ and ‘b’ respectively. The other
barrier height values are deviating from this value due to local inhomogeneities[44,
46,47].
One can understand the temperature dependency of flat band barrier height
(bf ) by the relation given as [16],
6.47
Where α is the temperature coefficient of the barrier height. The value of α can be
determined using the plot of bf vs. T as shown in figure 6.17 (a) and (b). The slope of
plot gives value of α and intercept on y-axis represent the value of bf at T=0 K.
From the data it can be seen that the flat-band barrier height is invariably larger than
the zero-bias barrier height at low temperatures. This is possibly due to extremely
high values of the ideality factor, which increases with decreasing temperature.
The fit of the above equation to the data as shown in figure 6.17 (a) and (b)
gives the value of temperature coefficient of the barrier height ‘α’ which found to be
8.7 x 10-4
and 7 x 10-4
eV.K-1
f and the value of bf = 1.58 and 1.49 eV for both the
diodes ‘a’ and ‘b’ Al/n CdS crystal diodes at T=0 K respectively.
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Figure 6.16: The variation in zero-bias barrier height versus ideality factor for Al/n-
CdS Schottky diodes ‘a’ and ‘b’ respectively.
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Figure 6.17: The temperature dependence of flat band barrier height for Al/n-CdS
Schottky diodes ‘a’ and ‘b’ respectively.
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We can rewrite the equation 6.13 as the following form,
6.48
Now, using the value of I0, a plot of Ln (I0/AT2) → 1000/T (Richardson plot)
as shown in figure 6.18(a) and (b), gives straight line and intercept of this straight line
on y axis gives value of Richardson constant (A*) according to equation 6.48. The
value of A* is near to reported values for bulk CdS. Some deviation may be due to
inhomogenities present at the interface of the diode. It is seen that both the plots for
fabricated diodes are found almost linear. The little deviation observed in Richardson
plots may be due to large ideality factor and high series resistance. This indicates the
deviation of I-V characteristics from thermionic emission. The deviation in
Richardson plots may be also due to the spatial inhomogeneous barrier heights and
potential fluctuations at the interface that consist of low and high barrier areas [33,39,
44, 55-59]. Here the values of Richardson constants for Al/n CdS crystal diodes ‘a’
and ‘b’ are found to be 20.7 Acm-2
K-2
and 27.9 Acm-2
K-2
respectively. The values of
Richardson constants are nearly close to reported value of 20 Acm-2
K-2
[60] for CdS.
As it was explained by Horwath [61], the value of Richardson constant obtained from
the temperature dependence of I-V characteristics may be affected by the lateral
inhomogeneity of the barrier.
The series resistance Rs here includes the contact resistance and the thermionic
emission is assumed to be the most predominant mechanism. The effect of Rs is
significant in the non-linear region of the forward voltage biasing and results in
reducing the linear range of the forward IV curves. Indeed, the determination of Φb
and n becomes inaccurate [34].
The slope of (dV/dI)I vs. I plot figure 6.19(a) and (b) obtained from forward
bias I – V characteristics of the prepared Schottky diodes at various temperature will
give us the value of series resistance. As a result of these, the variation in series
resistance with temperature is plotted in figure 6.20(a) and (b). The obtained high
series resistance of the Al/n-CdS device may be attributed to the high resistance of the
starting CdS and some defects through the preparation or to the interfacial layer
created between the metal and CdS and it is found to decrease with increasing
temperature[34,62]. The results obtained in this analysis are shown in table 6.1 and 6.2.
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Figure 6.18: Richardson plots for Al/n-CdS Schottky diodes ‘a’ and ‘b’ respectively.
243 | P a g e
Figure 6.19: (dV/dI)I vs. I plot obtained from forward bias I – V characteristics at
various temperature for Al/n-CdS Schottky diodes ‘a’ and ‘b’ respectively.
244 | P a g e
Figure 6.20: The variation of series resistance at different temperatures for Al/n-CdS
Schottky diodes ‘a’ and ‘b’ respectively.
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6.7.1.2 Norde Method
The series resistance is a very important parameter of Schottky diode. The
resistance of the Schottky contact is the sum total resistance value of the series
resistance RS and parallel resistance of barrier region in the direction of current flow.
Because of series high resistance, it is difficult to evaluate the accurate barrier height
from the both standard LnI vs. V method. Norde [40] proposed an alternative method
to determine values of barrier height of Schottky diode even for high series resistance.
In this method Norde function F(V) defined as,
6.50
which is used to plot against forward bias voltage (figure 6.21(a) and (b)). This plot
normally shows slops of +1/2 and -1/2 on both the side of minimum value of function
F(V) called F(V)minimum.
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Figure 6.21: Norde function versus forward bias voltage at different temperatures for
Al/n-CdS Schottky diodes ‘a’ and ‘b’ respectively.
The effective Schottky barrier height is given by,
6.51
Here, F(V)min is the minimum value of F(V), Vmin is the corresponding voltage,
and ‘I0’ is the corresponding current at V=Vmin, respectively, ‘A’ is the effective area
of Schottky diode and ‘A*’ is the Richardson constant 20 A.cm
-2K
-2 for CdS .
6.7.1.3 Cheung Method
The Schottky diode parameters such as the barrier height ‘ɸb’ and the ideality
factor ‘η’ and series resistance ‘Rs’ were also obtained using a method developed by
Cheung and Cheung [63]. Cheung’s functions can be written as follows,
6.52
6.53
Cheung function (equation 6.53) is also writing as
6.54
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where, ‘b0’ is the zero bias barrier height extracted from the lower – voltage part of
forward I–V characteristics, ‘A’ is the effective area of Schottky diode and A* is the
Richardson constant for CdS. Using equation 6.52 and from the plot of dV/d(ln(I)) vs.
I, one can obtain the value of ideality factor (η) as the y – axis intercept (figure 22).
Similarly, using equation 6.54 and from the plot of H(I) vs. I one can obtain the value
of barrier height (b) as the y – axis intercept and the series resistance ‘Rs’ are equal
to the slope of the same equation(figure 23).
The values of ideality factor, barrier height and series resistance were obtained
and results obtained are shown in table 6.1 and 6.2. As discussed earlier, the deviation
in Richardson plot and value of A*, the high value of ideality factor at low
temperature can be considered as an indication of non-ideal nature which may be
attributed to:
i. Inhomogeneous nature of the fabricated diode[13, 44, 46, 64,65]
ii. Multiplicity of operative transport mechanisms [6,39, 40,66] or
iii. Combination of above both
In view of all the point discussed above, we can say that the observed results
need to be re-examined more closely, and the first step towards this is to assess the
barrier height inhomogenities using Gaussian distribution as describes in the
following section. The value of ideality factor greater than unity is associated with
Fermi-level pinning at the interface [67-71] or relatively large voltage drops in
interface region. Interfacial oxide layer may also be the possible cause for a higher
ideality factor [72]. Surface defects produce electronic energy levels in the band gaps
of CdS semiconductor. These levels can pin the Fermi energy at metal-semiconductor
interfaces and cause Schottky-barrier formation [72,73].
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Figure 6.22: dV/d(LnI) vs. I plot obtained from forward bias I – V characteristics at
different temperature for Al/n-CdS Schottky diodes ‘a’ and ‘b’ respectively.
249 | P a g e
Figure 6.23: H ( I ) vs. I plot obtained from forward bias I – V characteristics at
different temperature for Al/n-CdS Schottky diodes ‘a’ and ‘b’ respectively.
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Table 6.1: A comparative table of various Schottky barrier parameters extracted for
the prepared Schottky diode ‘a’.
Temp.
(K)
In I → V Method Chung Method ,
H(I) vs. I
Norde Method,
F(V) vs. V
Series Resistance
( k Ω)
I0
(A)
b0
(eV)
bf
(eV)
η b0
(eV)
η b0
(eV)
IdV/dI
vs. I
H (I)
vs. I
303 5.3E-11 0.96 1.50 5.30 0.82 5.40 0.97 3680 3570
313 1.8E-10 0.95 1.48 4.31 0.91 4.70 1.0 2420 2320
323 2.3E-10 0.98 1.39 3.72 0.92 3.93 0.97 2020 1980
333 1.8E-10 1.02 1.27 2.59 0.95 3.13 0.92 1820 1570
343 6.7E-11 1.08 1.29 2.06 0.96 1.90 0.96 1520 1440
353 3.2E-10 1.07 1.21 1.95 0.99 1.83 0.97 1090 1030
363 1.2E-09 1.06 1.13 1.90 1.04 1.81 1.07 273 272
373 8.9E-10 1.09 1.19 1.80 1.06 1.78 1.08 195 194
383 2.4E-09 1.10 1.15 1.75 1.07 1.73 1.09 135 134
393 2.1E-09 1.13 1.15 1.38 1.11 1.42 1.10 107 103
403 4.6E-09 1.14 1.14 1.35 1.13 1.35 1.12 80.8 79
413 3.2E-09 1.17 1.20 1.31 1.14 1.21 1.13 60.9 59
423 1.7E-09 1.23 1.27 1.23 1.15 1.23 1.14 46.8 45
433 4.8E-09 1.23 1.24 1.17 1.19 1.07 1.16 35.2 34
443 9.5E-09 1.23 1.24 1.15 1.20 1.05 1.17 25.2 25
453 4.9E-08 1.19 1.21 1.12 1.23 1.02 1.18 19.1 18.8
463 1.5E-08 1.27 1.31 1.09 1.26 0.95 1.19 14.9 14.6
473 1.6E-08 1.29 1.32 1.07 1.29 0.96 1.21 11.8 11.4
483 2.6E-08 1.31 1.32 1.04 1.30 0.91 1.22 9.7 9.3
493 5.4E-08 1.30 1.31 1.02 1.31 0.92 1.23 8 7.6
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Table 6.2: A comparative table of various Schottky barrier parameters extracted for
the prepared Schottky diode ‘b’.
Temp.
(K)
In I → V Method Chung Method ,
H(I) vs. I
Norde Method,
F(V) vs. V
Series
Resistance
( k Ω)
I0
(A)
b0
(eV)
bf
(eV)
η b0
(eV)
η b0
(eV)
IdV/dI
vs. I
H (I)
vs. I
293 3.6E-10 0.87 1.33 4.95 0.84 4.67 0.84 18500 17600
303 3.7E-10 0.91 1.28 4.15 0.88 4.40 0.86 15000 14100
313 5.3E-10 0.93 1.27 3.97 0.87 4.21 0.90 12200 11900
323 5.7E-10 0.96 1.23 3.37 0.93 3.36 0.99 10600 10200
333 8.2E-10 0.98 1.22 3.06 0.97 3.18 0.95 5250 4910
353 8.4E-10 1.04 1.26 2.64 1.10 2.80 1.01 5440 4970
363 1.3E-09 1.06 1.21 2.17 1.11 2.10 1.04 3110 2490
373 1.2E-09 1.09 1.20 1.45 1.10 2.01 1.05 2970 2520
383 1.3E-09 1.12 1.18 1.19 1.14 1.90 1.10 2170 2050
393 1.4E-09 1.15 1.17 1.08 1.13 1.71 1.12 1510 1240
403 2.3E-09 1.16 1.21 1.16 1.12 1.62 1.14 1610 1400
413 3.0E-09 1.18 1.20 1.07 1.14 1.56 1.15 1310 1190
423 4.1E-09 1.20 1.20 1.00 1.17 1.26 1.16 763 691
433 6.1E-09 1.21 1.22 1.03 1.20 1.16 1.18 677 569
6.7.2 Schottky Barrier Height (SBH) Inhomogeneities
The interfaces of the semiconductor junction are important part of
semiconductor devices. One of the most interesting properties of a semiconductor
junction interface is its barrier height (Φb), which is a measure of the mismatch of the
energy levels for the majority carriers across the interface. Temperature dependent
ideality factor (η) and barrier height (Φb) and deviation of the Richardson constant
(A*) suggest an inhomogeneous barrier.
Inhomogeneities are imperfections at the interface between two materials. These are
borne from the surface not being atomically flat due to grain boundaries, multiple
phases, facets, defects, etc. Other sources of inhomogeneity include nonuniformity
252 | P a g e
within the doping profile and residual materials left over from processing creating
interfacial states between the surfaces.
Various factors may be responsible for these large variations observed in
ideality factor and barrier height. The ideality factor is simply a manifestation of the
barrier uniformity and it increases for an inhomogeneous barrier [45]. An apparent
increase in ideality factor and decrease in BH at low temperature are possibly caused
by some other effects such as inhomogeneities of thickness and composition of the
layer, nonuniformity of the interfacial charges or the presence of any thin insulating
layer between the metal and the semiconductor or contamination at MS interface
[13, 31, 44-50].Moreover, there are numerous structural defects, grain boundaries,
dislocations at MS interface and these may contribute to SBH inhomogeneity.
The above discussed unusual contact behavior can be explained by using an
analytical potential fluctuation model based on spatially inhomogeneous barrier
heights at interface [53-58]. As discussed earlier in the theory of barrier height
inhomogeneity, the apparent barrier height and ideality factor at zero bias are given by
equations 6.39 and 6.40. However, the distribution may differ for each bias voltage;
hence a more general form of equation 6.38 can be expressed as,
Φ Φ
σ
6.55
which holds for all biases including zero bias. Thus, equation 6.39 is a special
case of equation 6.55 when the applied bias V is zero. Since equation 6.39 gives Φap
and ηap which should in turn obey equations 6.39 and 6.40. Thus, the plot (6.24 (a)
and (b)) of Φap vs. q/2kT should be a straight line giving the Gaussian parameters
′mean 0′ and σ0 from the intercept and slope respectively. Since σo is not small in
comparison with the mean value of Φbo , we conclude that the interface is significantly
inhomogeneous. Also, the temperature dependence of the ideality factor can be
understood on the basis of equation 6.40 which indicates that the plot (6.25(a) and (b))
of ((1/ηap) -1) vs. q/2kT should give a straight line giving voltage coefficients ρ2 and
ρ3 from y-axis intercept and a slope respectively. Obtain results for the Al/n-CdS
diodes are shown in table 6.3.
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Figure 6.24: Apparent barrier height vs. q/2kT plots for Al/CdS Schottky diodes.
254 | P a g e
Figure 6.25: Apparent ideality factor vs. q/2kT plots for Al/CdS Schottky diodes.
Now, the Richardson plot is modified by combining equations 6.38 and 6.39
as,
6.56
The Ln(I0/T2) – (q
2σ0
2/2k
2T
2) vs 1000/T known as modified Richardson plot,
thus should be a straight line.From the intercept of this graph, the modified
255 | P a g e
Richardson constant, ‘A**
’ was calculated. The modified Richardson plot for diodes
are shown in figure 6.26 (a) and (b) and the accurate value of Richardson constant
shown in table 6.3.
Figure 6.26: Richardson plot and its modification for Al/n-CdS Schottky diodes
according to Gaussian distribution of the barrier heights.
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Table 6.3: A comparative table of various Schottky barrier parameters extracted for
the prepared Al/n-CdS crystals Schottky diodes.
Schottky
Diode
Ф(T=0)
(eV)
σ0
(V)
ρ2
(V)
ρ3
(V)
A*
Acm-2K-2
A**
Acm-2K-2
% of
Inhomogeneities
Diode ‘a’ 1.87 0.22 0.88 0.07 20.75 20.55 11.76
Diode ‘b’ 1.95 0.23 1.2 0.088 27.89 27.58 11.79
6.7.2 Capacitance-Voltage-Temperature(C-V-T) Measurement
Capacitance–Voltage C-V measurements of prepared Al/n-CdS crystal
structure were studied. The values of barrier height and the doping concentrations
were obtained from the reverse bias capacitance–voltage CV measurements at room
temperatures for 1kHz, 3kHz and 5kHz.
Figure 6.27 shows the C-V measurements on the Schottky barrier diode of
thickness 0.314mm was performed to determine the carrier concentrations of the
crystal and to measure the barrier heights of the SBDs. The C-2
versus V of room
temperature studies shows that insignificant increase of barrier height and donor
concentrations with increasing frequency (figure 6.28) .
On the other hand, it is seen from the results of 1 KHz the values of barrier
height for the diode are found to decrease with increasing temperature (figure 6.29).
The Schottky barrier heights extracted from the C-V measurements were typically
higher than those obtained from the I-V measurements. This has been attributed to the
presence of the interfacial oxide layer. This oxide layer decreases the total
capacitance and thus increases the built-in voltage, resulting in a higher value of the
barrier height.
According to Werner and Guttler [13], spatial inhomogeneities at the metal–
semiconductor interface of abrupt Schottky contact can also cause such differences in
the barrier height determined from IV and CV measurements. Another possibility may
be the transport mechanism in these diodes which is not purely due to thermionic
emission. For this structure, the barrier height obtained from IV measurement is
voltage or electric field sensitive, whereas the barrier height obtained from CV is not
[34].The obtained result represented in table 6.4 and 6.5.
On the other hand, the values of barrier height and the doping concentrations
were obtained under different high temperatures in the range 303K–363K at 1 kHz.
257 | P a g e
Measurement of capacitance under reverse bias can be used to gather information
about the barrier parameters. For an ideal Schottky barrier with a n-type non-
degenerate semiconductor with uniform doping concentration, the capacitance under
reverse bias per unit area can be expressed in terms of the diffusion potential (Vbi) and
donor density (Nd), if the effect of the holes can be neglected, by the relation [3],
ε ε
6.57
where, εs is the permittivity of semiconductor, Nd is the donor density, Vbi is the
diffusion voltage at zero bias and V is the applied reverse bias. This relation shows
that a graph of C-2
as a function of V should be a straight line with a slope of
2/(A2qε0εsNd) and a negative intercept on the V axis equal to –Vi=– Vbi +kT/q, from
which Vbi can be calculated. Nd can be known from the slope of the line if the
permittivity of the semiconductor is known. Considering value of intercept we can
write equation 6.57 as :
ε ε
6.58
The C-2
vs. V plots for Al/n-CdS Schottky barrier diode was drawn as shown in
figure 6.28. The doping concentration Nd was calculated from the slope of these plots
under reverse bias condition using relation (6.57).
Nd=2/ (A2.qεsε0×slope) 6.59
Here, Vi is the negative intercept on the reverse voltage axis and εs is the
permittivity of CdS, εo permittivity of free space. If the built in potential Vbi is
independent of V (i.e. if there is no appreciable interfacial layer) a plot of C-2
against
V should give a straight line with an intercept – Vi on the horizontal axis equal to –
(ɸbo- ξ -kT/q). The barrier height is then given by
6.60
where ξ is the energy difference between Fermi level and the bottom of the
conduction band. The value of ξ is known from the relation [16],
6.61
Where Nc is the effective density of states in the conduction band and Nd is donor
concentration.
From equation 6.60 we can obtain an equation for barrier height b0 as,
6.62
258 | P a g e
Figure 6.27: The C–V characteristics in both reverse and forward biasing under
various measuring frequencies for Al/n-CdS crystal diode.
Figure 6.28: C-2
versus V plots at room temperature under various measuring
frequencies (1kHz, 3kHz and 5kHz) for Al/n-CdS crystal diode.
259 | P a g e
Figure 6.29: C-2
versus V plots at different temperatures for Al/n-CdS crystal diode
at 1KHz.
Table 6.4: Room temperature SBD parameters extracted from C-2
-V plot for Al/n-
CdS diode at 1kHz, 3kHz and 5kHz.
Frequency Intercept ,(Vi)
(Volt)
Slope Donor concentration
(m-3)
Barrier height
(eV)
1KHz -3.1 1.31 x1019 5.25x1013
2.30
3KHz - 4.0 1.06x1019
6.51x1013
3.21
5KHz - 4.1 5.56x1018 1.24x1014 3.32
260 | P a g e
Table 6.5: Extracted SBD parameters (barrier height and carrier concentration) from
the C-2
-V plot for Al/n-CdS diode at 1KHz.
Temperature
Intercept ,Vi
(Volt)
Slope
Effective
density of
states (m-3
)
Donor
concentration
(m-3
)
Barrier
height
(eV)
303 K -3.1 1.32E+19 2.64E+26 5.25E+13 2.31
313 K -2.73 2.14E+19 2.77E+26 3.23E+13 1.90
323 K -2.35 2.18E+19 2.90E+26 3.18E+13 1.56
333 K -2.1 2.18E+19 3.04E+26 3.17E+13 1.21
343 K -1.91 2.25E+19 3.18E+26 3.08E+13 0.99
353 K -1.85 2.39E+19 3.32E+26 2.89E+13 0.90
363 K -1.85 2.41E+19 3.46E+26 2.87E+13 0.88
373k -1.6 2.47E+19 3.60E+26 2.81E+13 0.60
383k -1.6 2.48E+19 3.75E+26 2.79E+13 0.57
393k -1.45 2.51E+19 3.89E+26 2.75E+13 0.41
6.7.4 Current –Voltage(I-V) Measurement under Illumination
For studying photovoltaic effect arrangements were made to expose the diode
‘a’ to the light of desired intensity and wave lengths at room temperature (303K). The
I-V curves (6.30) show a lower current in the dark. A small open circuit voltage of
about 0.4 Volt at a light intensity of 120 mW/cm2 for polychromatic light as well as
monochromatic light. Hence, because of the presence of photovoltaic properties, Al/n-
CdS Schottky diodes could be used as a photodiode. If the photovoltaic parameters
could be made even better, the diode could be a good candidate for solar cell
technology. The variation of the structure resistance with applied bias has been
investigated at different wavelength of incident illumination and the result have been
in figure 6.31.
Generally, Al/n-CdS Schottky contacts are considered as majority carrier
devices and minority carrier injection is disregarded. Though injection of minority
carriers (holes for n-type CdS) is usually ignored, one should have to consider the
phenomenon especially at high forward bias condition where minority carrier
injection and charge storage become significant. In other words, both electrons and
holes transportation takes place simultaneously. To do so, barrier height for minority
261 | P a g e
carriers should be low compared to that of majority carriers. Indeed, the barrier height
for minorities will decrease as the barrier height for majority carriers increases.
Consequently, minority carrier injection occurs inevitably and produces an
inversion layer at the interface where the minority carrier amount exceeds the
majority carrier amount. Those charges would not contribute to the survey techniques
unless certain conditions were fulfilled. One of these occurs in the dark condition:
those stored minorities (holes) will diffuse into the neutral region of n-CdS
semiconductor under forward bias. In the meantime, additional electrons should enter
the neutral region of Schottky diode to preserve the charge neutrality, leading to an
increase in bulk conductivity .This phenomenon is known as conductivity modulation.
On the other hand, once IV measurement is performed under light, additional
electrons would be supplied over the one created due to illumination. Thus, the
reverse bias current exceeds the forward bias current values under light condition [1,
16, 34, 50, 74].
To measure the diode ideality factor n and reverse saturation current Jo of the
junctions under illumination, Jsc and Voc of the junctions were measured from the J-V
curves under three different wave lengths of illumination .The photovoltaic cell
follows the relation (6.63) [75],
6.63
Therefore, when ln Jsc versus Voc is plotted, it will be a straight line as per relation
6.64
When, ln Jsc is plotted against Voc developed under different intensity of illumination,
a straight line will be obtained as per relation (6.64). Therefore, the intercept and
slope of this linear plot will give the reverse saturation current density J0 and diode
ideality factor n, of the Al/n-CdS junction under illumination respectively.
Figure 6.32 (a - d) shows ln Jsc versus Voc plot of a typical diode. From the
slope and intercept of the plots for each wavelength, the diode ideality factor n and
reverse saturation current density Jo under illumination were calculated and have been
given in the table 6.6. The diode ideality factors n are observed to decrease under
illumination. The saturation current density Jo is found to increase under illumination.
The diode ideality factor under illumination of Al/n-CdS junction has been
found to decrease upon illumination while the saturation current density has been
observed to increase under illumination. This is due to the generation of more carriers
262 | P a g e
under illumination. Similar type of changes was observed by other workers with other
Schottky barrier junctions [76-78].
Figure 6.30: lnI–V characteristic of Al/n-CdS Schottky diodes measured at room
temperature in dark and light conditions.
Figure 6.31: The plot of the structure resistance versus applied bias voltage for Al/n-
CdS crystal under dark and illumination conditions.
263 | P a g e
264 | P a g e
Figure 6.32 (a - d): ln Jsc versus Voc plot of AL/n-CdS crystal Schottky diode.
I-V measurements showed a good response under the effect of illumination in
the range 10– 120 mW/cm2. Photovoltaic measurement indicated that Al/n-CdS
265 | P a g e
Schottky diode had response to light, proposing them as a good candidate as a
photodiode. Speculation was attempted to resolve this issue. [34,79].
Table 6.6: Ideality factor and saturation current density under illumination for Al/n-
CdS Schottky diode.
Illumination Ideality factor ,η Saturation current, I0(A)
Polychromatic light 0.23 1.11× 10-7
Yellow 0.359 2.55× 10-7
Green 0.56 2.50× 10-7
Red 0.359 7.77×10- 7
Summary
In this chapter, the fabrication and study of electrical properties of Al/n-CdS
Schottky diode by Current-Voltage-Temperature (I-V-T) and Capacitance-Voltage-
Temperature (C-V-T) characteristics are reported. The temperature dependence of
I-V characteristics of Al/n-CdS junction have been studied for two different diodes
denoted by ‘a’ and ‘b’ within the temperature range 303 K - 493 K and 293 - 433K
respectively. The value of zero bias barrier height has been calculated using three
different methods i.e. LnI versus V plot method, Norde method and Cheung method.
The diode ideality factors at room temperature of both diodes ‘a’ and ‘b’ have
been found to be 5.30 and 4.95 which were found to be reduced to the unity with
increment the temperature respectively (see Table 6.1 and Table 6.2).The series
resistance obtained is found to be in MΩ which may be attributed to the high
resistance of the starting CdS. The various Schottky barrier parameters like
Richardson constant and its modification, voltage coefficients ‘ρ2’ and ‘ρ3’ and % of
inhomogeneities were extracted using different mathematical equations and plots. The
values of barrier height and the doping concentrations were obtained from the
reverse bias capacitance–voltage CV measurements in room temperatures at 1kHz,
3kHz and 5kHz.On the other hand, the values of barrier height and the doping
concentrations were obtained under different high temperatures in the range 303–363
K at 1 kHz. Finally, the studying photovoltaic effect of Schottky diode was done. The
I-V curves show a lower current in the dark. A small open circuit voltage of about 0.4
Volt at a light intensity of 120 mW/cm2 for polychromatic light as well as
monochromatic light. Hence, because of the presence of photovoltaic properties, Al/n-
CdS Schottky diodes could be used as a photodiode. If the photovoltaic parameters
266 | P a g e
could be made even better, the diode could be a good candidate for solar cell
technology.
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