Chapter 6

Interrupts and Resets

Basics of Interrupts (1 of 4)

• What is an interrupt?– A special event that requires the CPU to stop normal program execution

and perform some service related to the event. – Examples of interrupts include I/O completion, timer time-out, illegal

opcodes, arithmetic overflow, divide-by-0, etc.• Functions of Interrupts

– Coordinating I/O activities and preventing CPU from being tied up– Providing a graceful way to exit from errors– Reminding the CPU to perform routine tasks

• Interrupt maskability– Interrupts that can be ignored by the CPU are called maskable

interrupts. – A maskable interrupt must be enabled before it can interrupt the CPU. – An interrupt is enabled by setting an enable flag.– Interrupts that can’t be ignored by the CPU are called nonmaskable

interrupts.

Basics of Interrupts (2 of 4)

• Interrupt priority– Allow multiple pending interrupt requests– Resolve the order of service for multiple pending interrupts

• Interrupt service– CPU executes a program called the interrupt service routine.– A complete interrupt service cycle includes

• Saving the program counter value in the stack• Saving the CPU status (including the CPU status register and some other

registers) in the stack• Identifying the cause of interrupt• Resolving the starting address of the corresponding interrupt service routine• Executing the interrupt service routine• Restoring the CPU status and the program counter from the stack• Restarting the interrupted program

Basics of Interrupts (3 of 4)

• Interrupt vector– Starting address of the interrupt service routine

• Interrupt vector table– A table where all interrupt vectors are stored

• Methods of determining interrupt vectors– Predefined locations (Microchip PIC18, 8051 variants)– Fetching the vector from a predefined memory location (HCS12)– Executing an interrupt acknowledge cycle to fetch a vector number in

order to locate the interrupt vector (68000 and x86 families)• Steps of interrupt programming

– Step 1. Initializing the interrupt vector table– Step 2. Writing the interrupt service routine– Step 3. Enabling the interrupt

Basics of Interrupts (4 of 4)

• The overhead of interrupts– Saving and restoring of CPU status and other

registers. (HCS12 needs to save all CPU registers).– Execution time of instructions of the interrupt service

routine.– The execution of the RTI instruction that will restore

all the CPU registers.

Reset

• The initial values of some CPU registers, flip-flops, and the control registers in I/O interface chips must be established in order for the computer to function properly.

• The reset mechanism establishes these initial conditions for the computer system.

• There are at least two types of resets: power-on reset and manual reset. – The power-on reset establishes the initial values of registers and

I/O control registers.– The manual reset without power-down allows the computer to

get out of most error conditions if hardware doesn’t fail.• A reset is nonmaskable.

PSEL5 PSEL4 PSEL3 PSEL2 PSEL1PSEL7 PSEL6 07 6 5 4 3 2 1 0

Figure 6.1 Highest priority I interrupt register

$001F

HCS12 Exceptions (1 of 2)• Maskable interrupts: including IRQ pin and all peripheral function

interrupts• Nonmaskable interrupts: including XIRQ pin, SWI interrupt, and

unimplemented opcode trap• Resets: including the power-on reset, reset pin manual reset, the

COP reset (computer operate properly), and clock monitor reset• Maskable Interrupts

– Different HCS12 members implement different number and types of peripheral functions, and hence may have different number of maskable interrupts.

– One of the maskable interrupts can be raised to the highest priority among the maskable interrupt group and receive quicker service. This is achieved by programming the HPRIO register.

HCS12 Exceptions (2 of 2)

• The priority and vector addresses of all HCS12 exceptions are listed in Table 6.1.

• To raise a maskable interrupt source to the highest priority, write the low byte of the vector address of this interrupt to the HPRIO register.

• In Table 6.1, exceptions that have higher vector addresses are at higher priorities.

• Not all the exceptions are available in all HCS12 members. • IRQ Pin Interrupt

– The only external maskable interrupt for the HCS12.– IRQ interrupt can be edge-triggered or level-triggered. – IRQ interrupt has a local enable mask in the IRQCR register.– The IRQ interrupt is configured by programming the IRQCR register.– The contents of the IRQCR register are shown in Figure 6.2.

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Figure 6.2 Interrupt control register (IRQCR)

IRQE -- IRQ edge sensitive only bit IRQE can be written once in normal mode. In special modes, it can be written any time, but the first write is ignored. 1 = IRQ pin responds only to falling edge 0 = IRQ pin responds to low level.IRQEN -- IRQ enable bit IRQEN bit can be written any time in all modes. The IRQ pin has an internal pullup. 1 = IRQ pin interrupt enabled 0 = IRQ pin interrupt disabled

• Pros– Multiple interrupt sources can be tied to this pin.

• Cons– Need to make sure that the IRQ signal has become

inactive before the IRQ service routine is complete if there is only one interrupt request pending.

Making IRQ Level-sensitive

• Pros:– No need to control the duration of the IRQ pulse.

• Cons:– Not suitable for noisy environment because every

falling edge caused by noise will be recognized as an interrupt.

Making IRQ Edge-sensitive

When Does the MCU Recognize Interrupt Requests?

• The MCU recognizes the interrupt request when it completes the execution of the current instruction unless the current instruction is a fuzzy logic instruction. For fuzzy logic instructions, the HCS12 recognizes the interrupt immediately.

.

Figure 6.3 Stack order on entry to interrupts

return address

[Y]

[X]

[B]

[A]

[CCR] SP

SP+1

SP+2SP+3

SP+5

SP+7

• The stack order on entry of an interrupt– The HCS12 saves all CPU registers on an interrupt.– The order of saving CPU registers is shown below.

• The RTI instruction– RTI is used to terminate interrupt service routines.– RTI will restore CPU registers from the stack.– The HCS12 will continue to execute the interrupted program unless

there is another pending interrupt.

Nonmaskable Interrupts• XIRQ pin interrupt

– XIRQ interrupt is disabled during a system reset and upon entering the service routine of another XIRQ interrupt.

– After minimal system initialization, software can clear the X bit of the CCR register to enable the (using the andcc #$BF instruction) XIRQ interrupt. Software cannot reset the X bit once it has been set.

– When a nonmaskable interrupt is recognized, both the X and I bits are set after CPU registers are saved.

– The execution of an RTI instruction at the end of the XIRQ service routine will restore the X and I bits to the pre-interrupt request state.

• Unimplemented opcode trap– There are 202 unimplemented opcodes on page 2 (16-bit opcode).– These unimplemented opcodes share the same vector $FFF8:$FFF9.

• Software interrupt instruction (SWI)– Execution of the SWI instruction causes an interrupt without an interrupt request

signal.– The SWI instruction is commonly used in the debug monitor to implement

breakpoints and to transfer control from a user program to the debug monitor. – A breakpoint in a user program is a memory location where we want program

execution to be stopped and information about instruction execution (in the form of register contents) to be displayed.

Interrupts in D-Bug12 EVB Mode

• On-chip flash memory locations are not available for user to store interrupt vectors.

• D-Bug12 monitor provides SRAM-based interrupt vector table.

• The SRAM-based table (in Table 6.3) starts at $3E00 and has 64 entries.

• The interrupt SCI0 has been used by the monitor and is not available to the user.

• Mnemonic names are defined for users to store their interrupt vectors in the table. Both the hcs12.inc and the vectors12.h (for C language) have the definitions for these entries.

Table 6.3 Mnemonic names for D-Bug12 RAM Interrupt vector addresses

Interrupt source Interrupt sauceRAM vector

addressRAM vector

address

UserRsrv0x80UserRsrv0x82UserRsrv0x84UserRsrv0x86UserRsrv0x88UserRsrv0x8aUserPWMShDnUserPortPUserMSCAN4TxUserMSCAN4RxUserMSCAN4ErrsUserMSCAN4WakeUserMSCAN3TxUserMSCAN3RxUserMSCAN3ErrsUserMSCAN3WakeUserMSCAN2TxUserMSCAN2RxUserMSCAN2ErrsUserMSCAN2WakeUserMSCAN1TxUserMSCAN1RxUserMSCAN1ErrsUserMSCAN1WakeUserMSCAN0TxUserMSCAN0RxUserMSCAN0ErrsUserMSCAN0WakeUserFlashUserEEPROMUserSPI2UserSPI1

$3E00$3E02$3E04$3E06$3E08$3E0A$3E0C$3E0E$3E10$3E12$3E14$3E16$3E18$3E1A$3E1C$3E1E$3E20$3E22$3E24$3E26$3E28$3E2A$3E2C$3E2E$3E30$3E32$3E34$3E36$3E38$3E3A$3E3C$3E3E

$3E40$3E42$3E44$3E46$3E48$3E4A$3E4C$3E4E$3E50$3E52$3E54$3E56$3E58$3E5A$3E5C$3E5E$3E60$3E62$3E64$3E66$3E68$3E6A$3E6C$3E6E$3E70$3E72$3E74$3E76$3E78$3E7A$3E7C$3E7E

UserIICUserDLCUserSCMEUserCRGUserPAccBOvUserModDwnCtrUserPortHUserPortJUserAtoD1UserAtoD0UserSCI1UserSCI0UserSPI0UserPAccEdgeUserPAccOvfUserTimerOvfUserTimerCh7UserTimerCh6UserTimerCh5UserTimerCh4UserTimerCh3UserTimerCh2UserTimerCh1UserTimerCh0UserRTIUserIRQUserXIRQUserSWIUserTrapN/ AN/ AN/ A

Setting Up the Interrupt Vector (1 of 2)

• The label (or name) of the IRQ interrupt service routine is IRQISR.• In assembly language

movw #IRQISR,UserIRQ ; store the vector at the designated address

• In C language– Add the following statement at the beginning of the program:

#define INTERRUPT __attribute__((interrupt))– Include the header file vectors12.h using the statement:

#include “c:\egnu091\include\vectors12.h”– Declare the prototype of the service routine as follows:

#define INTERRUPT IRQISR(void);– Store the name of the IRQ service routine at the designated address:

UserIRQ = (unsigned short)&IRQISR;

Setting Up the Interrupt Vector (2 of 2)

• Example 6.1 – The IRQ pin of the HCS12DP256 is connected to a 1-Hz digital

waveform and port B is connected to eight LEDs. Write a program to configure port B for output and enable the IRQ interrupt and also write the service routine for the IRQ interrupt.

– The service routine for the IRQ interrupt simply increments a counter and outputs it to port B.

• Solution– The assembly and C language versions of the program are in

the following two pages.

#include "c:\miniide\hcs12.inc"org $1000

count ds.b 1 ; reserve one byte for countorg $1500lds #$1500 ; set up the stack pointermovw #IRQISR,UserIRQ ; set up interrupt vector in SRAMclr countmovb #$FF,DDRB ; configure port B for outputbset DDRJ,$02 ; configure PJ1 pin for output (required in Dragon12)bclr PTJ,$02 ; enable LEDs to light (required in Dragon12)movb count,PTB ; display the count value on LEDsmovb #$C0,IRQCR ; enable IRQ pin interrupt, select edge-triggeringcli ; "

forever nopbra forever ; wait for IRQ pin interrupt

; ****************************************************************************; This is the IRQ service routine.; ****************************************************************************IRQISR inc count ; increment count

movb count,PTB ; and display count on LEDsrtiend

#include "c:\egnu091\include\hcs12.h"#include "c:\egnu091\include\vectors12.h"#define INTERRUPT __attribute__((interrupt))void INTERRUPT IRQISR(void);unsigned char cnt;

int main(void){ UserIRQ = (unsigned short)&IRQISR; DDRB = 0xFF; cnt = 0; DDRJ |= BIT1; /* configure PJ1 pin for output */ PTJ &= ~BIT1; /* enable LEDs to light */ IRQCR = 0xC0; /* enable IRQ interrupt on falling edge */ asm("cli"); /* enable interrupt globally */ while(1); /* wait for interrupt forever */ return 0;}void INTERRUPT IRQISR(void){ cnt++; PTB = cnt;}

Clock and Reset Generation Block (CRG) (1 of 2)

• CRG generates the clock signals required by the HCS12 instruction execution and all peripheral operations.

• The clock signal has the form of square waveform.• Crystal oscillators are often used to generate clock signals.• The crystal oscillator output is sinusoidal wave and must be squared up

before it can be used.• The HCS12 has an internal circuit to do this square up operation.• The CRG block also has a PLL circuit that can multiply the frequency of the

incoming clock signal.• The block diagram is shown in Figure 6.4.• The CRG can also accept oscillator output (square waveform) directly. • The XCLKS signal must be tied low (for MC9S12DP256B) in order to use

external clock signal.

VREG

Clock and ResetControl

Resetgenerator

Clock qualitychecker

COP RTI

Registers

SystemReset

Bus clock

Core clock

Oscillatorclock

Power onreset

RESET

CM failClock

monitor

OSC

PLL

OSCCLK

PLLCLK

XCLKS

EXTAL

XTAL

XFCVDDPLLVSSPLL

CRG

Figure 6.4 Block diagram of CRG

Clock and Reset Generation Block (CRG) (2 of 2)

Choice of Clock Source (1 of 2)

• The user can choose between using the external crystal or oscillator to produce the clock signal.

• The external crystal is connected between the EXTAL and XTAL pins and needs an on-chip oscillator circuitry to square it up.

• The external clock source provided by the oscillator is connected to the EXTAL pin and has a 2.5V peak-to-peak magnitude for D family.

• The XCLKS signal must be grounded to select the external clock signal.• The output from the OSC module in Figure 6.4 may bypass or go through

the PLL circuit.• The PLL circuit has the capability to multiply incoming signal frequency and

stabilize its output signal frequency.• Either the OSCCLK or the PLLCLK can be chosen as the SYSCLK which

will be divided by 2 to derive the bus clock to control the instruction execution and peripheral operation.

• The HCS12 clock generation circuit is shown in Figure 6.15.

Phaselockloop

1

0

1

0

Clockmonitor

OscillatorOSCCLK

PLLCLK

PLLSEL or SCM

SCM

clockphase

generator2

WAIT,STOP

wait(RTIWAI),stop(PSTP,PRE)

RTI enable

RTI

COP

wait (COPWAI),stop(PSTP, PCE)

COP enable

wait (SYSWAI),stop

stop (PSTP)

wait (CWAI,SYSWAI)stop

Coreclock

Busclock

oscillatorclock

oscillatorclock (pseudo stopmode)

extal

xtal

gatingcondition

= clock gate

Figure 6.15 HCS12 clock generation circuit

SYSCLK

Choice of Clock Source (2 of 2)

(SYNR + 1)PLLCLK = 2 OSCCLK ----------------------- (6.1)

(REFDV + 1)

reset:

0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0

0 0 0 0 0 0 0 0

Figure 6.8 The CRG synthesizer register (SYNR)

01234567

reset:

0 0 0 0 REFDV3 REFDV2 REFDV1 REFDV0

0 0 0 0 0 0 0 0

Figure 6.9 The CRG reference divider register (REFDV)

7 6 5 4 3 2 1 0

Phase Locked Loop (PLL) (1 of 5)

• The frequency of the PLLCLK is controlled by registers SYNR and REFDY using the following equation:

Selection of PLL for clock generation is controlled by the CRGSEL register.

reset:

PLLSEL PSTP CWAISYSWAI ROAWAI PLLWAI RTIWAI COPWAI

0 0 0 0 0 0 0 0

Figure 6.13 The CRG clock select register (CRGSEL)

7 6 5 4 3 2 1 0

PLLSEL: PLL select bit 0 = system clocks are derived from OSCCLK 1 = system clocks are derived from PLLCLKPSTP: pseudo stop bit This bit controls the functionality of the oscillator during the stop mode. 0 = oscillator is disabled in stop mode 1 = oscillator continues to run in stop mode (pseudo mode). The oscillator amplitude is reduced.SYSWAI: system clocks stop in wait mode bit 0 = The system clocks continue to run in wait mode. 1 = The system clocks stop.ROAWAI: Reduced oscillator amplitude in wait mode bit 0 = Normal oscillator amplitude in wait mode 1 = Reduced oscillator amplitude in wait modePLLWAI: PLL stops in wait mode bit 0 = PLL keeps running in wait mode 1 = PLL stops in wait mode. The CRG will clear the PLLSEL bit before entering wait mode. The PLLON bit remains set during wait mode but the PLL is powered down.CWAI: core stops in wait mode bit 0 = Core clock keeps running in wait mode. 1 = Core clock stops in wait mode.RTIWAI: RTI stops in wait mode bit 0 = RTI keeps running in wait mode. 1 = RTI stops and initializes the RTI dividers whenever the part goes into wait mode.COPWAI: COP stops in wait mode bit 0 = COP keeps running in wait mode 1 = COP stops and initializes the COP dividers whenever the part goes into wait mode.

Phase Locked Loop (PLL) (2 of 5)

PLL circuit is also controlled by the PLLCTL register.

reset:

CME PLLON PREAUTO ACQ 0 PCE SCME

0 0 0 0 0 0 0 0

Figure 6.14 The CRG PLL control register (PLLCTL)

7 6 5 4 3 2 1 0

CME: clock monitor enable bit 0 = clock monitor is disabled 1 = clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or self clock modePLLON: phase lock loop on bit 0 = PLL is turned off 1 = PLL is turned on. If AUTO bit is set, the PLL will lock automatically.AUTO: automatic bandwidth control bit 0 = automatic mode control is disabled and the PLL is under software control, using ACQ bit. 1 = high bandwidth filter is selectedACQ: acquisition bit (if AUTO bit = 1, this bit has no effect) 0 = low bandwidth filter is selected 1 = high bandwidth filter is selectedPRE: RTI enable during pseudo stop bit 0 = RTI stops running during pseudo stop mode 1 = RTI continues running during pseudo stop modePCE: COP enable during pseudo stop bit 0 = COP stops running during pseudo stop mode 1 = COP continues running during pseudo stop mode.SCME: self clock mode enable bit 0 = detection of crystal clock failure causes clock monitor reset 1 = detection of crystal clock failure forces the MCU in self clock mode

Phase Locked Loop (PLL) (3 of 5)

movb #2,SYNR ; set SYNR to 2movb #0,REFDV ; set REFDV to 0movb #$80,CRGSEL ; enable PLL, keep SYSCLK running in wait mode,

; keep RTI, COP, PLL & core running in wait modemovb #$60,PLLCTL ; disable clock monitor, enable PLL, set automatic

; bandwidth control, disable RTI & COP in pseudo stop

• In addition, the XCLKS pin must be grounded to select oscillator as clock source.

Phase Locked Loop (PLL) (4 of 5)• Example 6.2 There is a system that derives its bus clock from the PLL

circuit and an external clock of 8 MHz is selected. The desired bus clock is 24 MHz. Write an instruction sequence to perform the desired configuration.

• Solution– The SYSCLK frequency is 48 MHz.– The frequency of OSCCLK is 8 MHz.– 48 MHz = 2 8 MHz [SYNR + 1] /[REFDV + 1]

• One solution is to set SYNR and REFDV to 2 and 0, respectively.

movb #5,SYNR ; set SYNR to 5movb #0,REFDV ; set REFDV to 0movb #$80,CRGSEL ; enable PLL, keep SYSCLK running in wait mode,

; keep RTI, COP, PLL & core running in wait modemovb #$60,PLLCTL ; disable clock monitor, enable PLL, set automatic

; bandwidth control, disable RTI & COP in pseudo stop

• The XCLKS pin must be pulled to high to select external crystal to generate clock signals.

Phase Locked Loop (PLL) (5 of 5)• Example 6.3 There is a system that uses a 4 MHz crystal oscillator to

derive a 24 MHz bus clock. Write an instruction sequence to perform the required configuration.

• Solution The OSCCLK and PLLCLK frequencies are 4 MHz and 48 MHz, respectively.– 48 MHz = 2 4 MHz [SYNR + 1] /[REFDV + 1] – One solution is to set SYNR and REFDV to 5 and 0, respectively.

• The clock monitor is based on an RC circuit.• If no OSCCLK edges are detected within the RC

time delay, the clock monitor may reset the MCU if the CME bit in the PLLCTL register is set to 1.

• The SCME bit of the PLLCTL register must be cleared to 0 for clock monitor to work.

Clock Monitor

Real-time interrupt (RTI) (1 of 3)

• Main function is to generate periodic interrupt to the MCU.

• The RTI is enabled by the CRGINT register (shown in Figure 6.11).

• The interrupt interval of RTI is selected by the RTICTL register (shown in Figure 6.16).

• The actual available interrupt periods for RTI are listed in Table 6.4.

reset:

RTIE 0 0 LOCKIE 0 0 SCMIE 0

0 0 0 0 0 0 0 0

Figure 6.11 The CRG interrupt enable register (CRGINT)

7 6 5 4 3 2 1 0

RTIE: real time interrupt enable bit 0 = interrupt requests from RTI are disabled. 1 = interrupt requests from RTI are enabled.LOCKIE: lock interrupt enable bit 0 = LOCK interrupt requests are disabled. 1 = LOCK interrupt requests are enabled.SCMIE: self clock mode interrupt enable bit 0 = SCM interrupt requests are disabled 1 = Interrupt will be requested whenever the SCMIF bit is set

RTR5 RTR4 RTR3 RTR2 RTR10 RTR6 RTR0

7 6 5 4 3 2 1 0

0 1 0 0 00 0 0reset:

Figure 6.16 CRG RTI control register (RTICTL)

RTI (2 of 3)

Table 6.4 RTI interrupt period (in units of OSCCLK cycle)

RTR[3:0] RTR[6:4]

000(off)

001(210)

010(211)

011(212)

100(213)

101(214)

110(215)

111(216)

0000 (1)0001(2)0010 (3)0011 (4)0100 (5)0101 (6)0110 (7)0111 (8)1000 (9)1001 (10)1010 (11)1011 (12)1100 (13)1101 (14)1110 (15)1111 (16)

off*off*off*off*off*off*off*off*off*off*off*off*off*off*off*off*

210

2210

3210

4210

5210

6210

7210

8210

9210

10210

11210

12210

13210

14210

15210

16210

211

2211

3211

4211

5211

6211

7211

8211

9211

10211

11211

12211

13211

14211

15211

16211

212

2212

3212

4212

5212

6212

7212

8212

9212

10212

11212

12212

13212

14212

15212

16212

213

2213

3213

4213

5213

6213

7213

8213

9213

10213

11213

12213

13213

14213

15213

16213

214

2214

3214

4214

5214

6214

7214

8214

9214

10214

11214

12214

13214

14214

15214

16214

215

2215

3215

4215

5215

6215

7215

8215

9215

10215

11215

12215

13215

14215

15215

16215

216

2216

3216

4216

5216

6216

7216

8216

9216

10216

11216

12216

13216

14216

15216

16216

RTI (3 of 3)

Computer Operating Properly (COP) Circuit (1 of 2)

• Allow the user to determine whether the application software operates properly.

• The COP is a timer circuit that will time out if it is not rearmed within a preset time limit.

• The COP will reset the MCU when it times out and the user would know if the software operated properly.

• The application software would include an instruction sequence to prevent the COP from timing out.

• To prevent the COP from timing out, write $55 and then $AA into the ARMCOP register.

• The time out period of the COP is controlled by the COPCTL register.

• The contents of the COPCTL are shown in Figure 6.17.

0 0 0 CR2 CR1WCOP RSBCK CR0

7 6 5 4 3 2 1 0

0 1 0 0 00 0 0reset:

Figure 6.17 CRG COP control register (COPCTL)

WCOP: windowed COP mode bit When set, a write to the ARMCOP register must occur in the last 25% of the selected period. A write during the first 75% of the selected period will reset the MCU. 0 = normal COP operation 1 = windowed COP operationRSBCK: COP and RTI stop in active BDM mode bit 0 = allows the COP and RTI to keep running in active BDM mode 1 = stops the COP and RTI whenever the HCS12 is in active BDM modeCR2:CR0: COP watchdog time rate select (number of OSCCLK cycles) 000: COP disabled 001: 214

010: 216

011: 218

100: 220

101: 222

110: 223

111: 224

Computer Operating Properly (COP) Circuit (2 of 2)

Lower Power Mode

• It is desirable to minimize power consumption when the MCU is not busy performing useful operations.

• The execution of the WAI instruction places the HCS12 MCU in wait mode and reduces power consumption significantly.

• In wait mode, CPU clocks are stopped, but clock signals for peripheral functions continue to run.

• The CPU leaves the wait mode when one of more of the following events occur:– Maskable interrupts that are not disabled.– Nonmaskable interrupts– Resets

• Reset is not the best way to get out of wait state because it will restart everything and takes longer to resume normal operation.

Stop Mode

• Stop mode is entered when the MCU executes the STOP instruction. When this instruction is executed, the MCU enters standby mode.– The STOP instruction has no effect if the S flag of the

CCR register is 1.

• In stop mode, all clock signals in the MCU are stopped.

• Asserting the RESET, IRQ, or XIRQ signal ends the standby mode.

Resets

• There are four sources of reset:– Power-on (POR) and low-voltage detector (LVD) reset– RESET pin– COP reset– Clock monitor reset

Power-on Reset

• The HCS12 has a circuit to assert reset when VDD supply to the MCU has reached a certain level.

• The CRG module performs a quality check on the incoming clock signal as soon as a power-on reset is triggered.

• The CRG module will release the reset signal only when the clock check is successful.

IN

GND

RESET

To RESETof HCS12

VDD

MC34064

VDD

4.7

1

3

Figure 6.18 A typical external reset circuit

manual reset

4.7

4.7

2F

External Reset• The RESET pin allows the user to

reset the MCU.• The MCU can differentiate the

external and internal reset signals.• When the power supply drops to a

certain level, it may corrupt the EEPROM.

– It is desirable to have a circuit that can detect this situation and asserts a reset to the MCU.

• The Motorola MC34064 is a chip that can detect low voltage on power supply and reset the CPU.

• An external reset circuit incorporating an MC34064 is shown.

Table 6.5 HCS12 Mode Selection

BKGD MODB MODA Mode

00001111

00110011

01010101

Special single chipSpecial expanded narrow

Special peripheralSpecial expanded wide

Normal single chipNormal expanded narrow

Reserved (forced to peripheral)Normal expanded wide

Port A

general-purpose I/OADDR[15:8]DATA[7:0]ADDR/DATAADDR/DATAGeneral-purpose I/OADDR[15:8]DATA[7:0]--ADDR/DATA

Port B

general-purpose I/OADDR[7:0]ADDR/DATAADDR/DATAGeneral-purpose I/OADDR[7:0]--ADDR/DATA

HCS12 Operation Modes• The HCS12 can operate in eight different operation modes (shown in Table

6.5).• The states of MODC, MODB, and MODA pins are latched to determine the

MCU operation modes.• Expanded modes allow the user to access external memory where single

chip modes do not.• In expanded modes, Port A and B become the time-multiplexed address

and data port.