Chapter 6 (I)access.ee.ntu.edu.tw/.../ppt/lecture_10_chapter6-1_PartI_05-15-2003.… · Logic Circuits •Static CMOS •Pass Transistor Logic V1.0 4/25/03 V2.0 5/4/03 V3.0 5/15/03

EE1411

Combinational Circuits

Chapter 6 (I)Chapter 6 (I)Designing Designing CombinationalCombinationalLogic CircuitsLogic Circuits

••Static CMOSStatic CMOS••Pass Transistor LogicPass Transistor Logic

V1.0 4/25/03V2.0 5/4/03V3.0 5/15/03

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Revision ChronicleRevision Chronicle5/2: Add some NAND8 figures (to compare NAND8 circuits) from old Weste textbook to this slide.5/4:

Add 4 Pass-Transistor Logic Slides from WestetextbookSplit Chapter 6 into two parts: Part I focuses on Static and Pass Transistor Logic. Part II focuses on Dynamic Logic

5/15:Add the Transmission Gate slides (x5) from Kang’s textbook

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Combinational vs. Sequential LogicCombinational vs. Sequential Logic

CombinationalLogicCircuit

OutInCombinational

LogicCircuit

OutIn

State

Combinational Sequential

Output = f(In, Previous In)Output = f(In)

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Static CMOS CircuitsStatic CMOS Circuits•At every point in time (except during the switching transients) each gate output is connected to either

via a low-resistive path (PUN, PDN)

•The outputs of the gates assume at all times thevalue of the Boolean function, implemented by the circuit (ignoring the transient effects duringswitching periods).

•This is in contrast to the dynamic CMOS circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuitnodes.

VDD or Vss

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Static Complementary CMOSStatic Complementary CMOSVDD

F(In1,In2,…InN)

In1In2

InN

In1In2InN

PUN

PDN

PMOS only(good for transfer 1)

NMOS only (good for transfer 0)

……

Pull-up Network (PUN) and Pull-down Network (PDN) are Dual Logic Networks

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Threshold Drops in NMOS and PMOSThreshold Drops in NMOS and PMOS---- Check Candidates for PUN and PDNCheck Candidates for PUN and PDN

VDD

VDD → 0

CL

G

PDN

0 → VDD

CLD

PUN

VGS

G

VDD

S DVDD

0 → VDD - VTnD S

CL

VDD → |VTp|

SVGS

GVDD

CL

GS D

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Complementary CMOS Logic StyleComplementary CMOS Logic Style

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NMOS Transistors NMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection

Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high

X Y

A B

Y = X if A and B

X Y

A

B Y = X if A OR B

NMOS Transistors pass a “strong” 0 but a “weak” 1

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PMOS Transistors PMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection

X Y

A B

Y = X if A AND B = A + B

X Y

A

B Y = X if A OR B = AB

PMOS Transistors pass a “strong” 1 but a “weak” 0

PMOS switch closes when switch control input is low

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Example 1: NAND2 GateExample 1: NAND2 Gate

(Use DeMorgan’s Law)

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Example2: NOR2 GateExample2: NOR2 Gate

),3,2,1(),3,2,1(

Connnet to:PUN

GND Connect to:PDN

…… InInInFInInInG

VBABAF

BAG

DD

≡

⇒+=⋅=

⇒+=

DDV

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Design of Complex CMOS GateDesign of Complex CMOS GateDDV

D

AB

C

)( CBADF +⋅+=A

D

B C

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Constructing a Complex GateConstructing a Complex Gate

C

(a) pull-down network

SN1 SN4

SN2

SN3D

FF

A

DB

C

D

F

A

B

C

(b) Deriving the pull-up networkhierarchically by identifyingsub-nets

D

A

A

B

C

VDD VDD

B

(c) complete gateSN1

SN1

SN2

SN2

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Static CMOS PropertiesStatic CMOS PropertiesFull rail-to-rail swing: High noise marginsLogic levels not dependent upon the relative device sizes: RatiolessAlways a path to Vdd or GND in steady state: Low output impedanceExtremely high input resistance; nearly zero steady-state input current (input to CMOS gate)No steady-state direct path between power and ground: No static power dissipationPropagation delay function of output load capacitanceand resistance of transistors

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Switch Delay ModelSwitch Delay Model

A

ReqA

B

Rp

A

Rp

A

Rn

B

Rn CL

Cint

NOR2

CL

B

Rn

A

Rp

B

Rp

A

Rn Cint

NAND2

A

Rp

A

Rp

A

Rn CL

INV

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Input Pattern Effects on DelayInput Pattern Effects on DelayDelay is dependent on the patternof input (Assume Rp = 2 Rn for same size of transistors)Low-to-high transition:

Both inputs go low– Delay is 0.69 (Rp/2) CL

One input goes low– Delay is 0.69 (Rp) CL

High-to-low transition:Both inputs go high (required for NAND)

– Delay is 0.69 (2Rn)CL

ARp

BRp

CL

B

Rn

ACint

Rn

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Transistor SizingTransistor SizingAssumes Rp = 2Rn at same W/L

A

Rp

B

Rp

CL

A

Rn

B

Rn Cint

B

Rp

A

Rp

A

Rn

B

Rn CL

Cint

11

4

4

2 2

2

2

NAND is preferred than NOR implementation!!

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Delay Dependence on Input PatternsDelay Dependence on Input Patterns

-0.5

0

0.5

1

1.5

2

2.5

3

0 100 200 300 400

A=B=1→0

A=1, B=1→0

A=1→0, B=1

time [ps]

Vol

tage

[V]

57A= 1→0, B=1

76A=1, B=1→0

35A=B=1→0

50A= 0→1, B=1

62A=1, B=0→1

69A=B=0→1

Delay(psec)

Input DataPattern

NMOS = 0.5µm/0.25 µmPMOS = 0.75µm/0.25 µmCL = 100 fF

A=1, B=1→0 (for both Cint and CL)A=1, B=0→1 (Consider Body effect)

NAND2 is trueOUT connects to GND

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Transistor Sizing a Complex Transistor Sizing a Complex CMOS GateCMOS Gate

D

A

1

2

2 2

4

48

8

2/NR

case) criticalfor oneonly (wide,2/NR

B

C

OUT = D + A • (B + C)A

D

B C

EE14120


FanFan--In ConsiderationsIn Considerations

4-input NAND Gate

EE14121


FanFan--In ConsiderationsIn Considerations

DCBA

D

C

B

A CL

C3

C2

C1

R4

R3

R2

R1

Distributed RC model(Elmore delay)

tpHL = 0.69(R1C1+(R1+R2)C2

+ (R1+R2+R3)C3

+ (R1+R2+R3+R4)CL

=0.69 Reqn(C1+2C2+3C3+4CL)

Propagation (H L) delay deteriorates rapidly as a function of fan-in no. : Quadratically in the worst case.

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ttpp as a Function of Fanas a Function of Fan--InIn

tpLH

t p(p

sec)

fan-in

0

250

500

750

1000

1250

2 4 6 8 10 12 14 16

tpHL

Quadratic (H->L)

tp

(L H)Linear Increase in Intrinsic Capacitance,Assume Only one PMOS is On for criticalcase

EE14123


((tpHLtpHL, , tpLHtpLH) as a Function of Fan) as a Function of Fan--OutOut

Gates with a fan-in greater than or equal to 4 becomes excessively slow and should be avoided!

EE14124


ttpp as a Function of Fanas a Function of Fan--In and FanIn and Fan--OutOut

Fan-in: quadratic due to increasing resistance and capacitance

Fan-out: each additional fan-out gate adds two gate capacitances to CL To the preceding stage)

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Fast Complex Gates: Design Technique 1Fast Complex Gates: Design Technique 1Transistor sizing

Increase Intrinsic parasitic cap and create CL of the preceding stage

Progressive sizing

C3

C2

C1M1

M2

M3

CLDistributed RC line:

•M1 > M2 > M3 > … > MN(the FET closest to theoutput is the smallest)

•Not simple in Layout!

InN MN

In3

In2

In1

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Fast Complex Gates: Design Technique 1Fast Complex Gates: Design Technique 1

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Input reordering: Put late arrival signal near the output node.

C2

C1In1

In2

In3

M1

M2

M3 CL

C2

C1In3

In2

In1

M1

M2

M3 CL

critical path critical path

charged1

0→1charged

charged1

Delay determined by time to discharge CL, C1 and C2

Delay determined by time to discharge CL

1

1

0→1 charged

discharged

discharged

EE14128



Logic Restructuring (A)

F =NAND8 Gate

In general, C > B > A in speed(B)(C)

EE14129

Combinational Circuits(from Neil Weste, 2nd Ed, 93)

Tradeoff between Area and Speed (and Power?)

Design Technique 3: Logic RestructuringDesign Technique 3: Logic Restructuring

EE14130


Fast Complex Gates: Layout Technique Fast Complex Gates: Layout Technique

(A) (B)

(A): 4 internal cap2 output diff cap

(B): 4 internal cap4 output diff cap

(A) Is better than (B)

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Optimizing Performance in Combinational Optimizing Performance in Combinational NetworksNetworks

( )∑=

⋅+=N

iiii fgpDelay

1

CL

InOut

1 2 N

(in units of τinv)

For given N: Ci+1/Ci = Ci/Ci-1

To find N: Ci+1/Ci ~ 4How to generalize this to any combinational logic path? E.g., How do we size the ALU datapath to achieve maximum speed?

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Logical EffortLogical Effort

Inverter has the smallest logical effort and intrinsic delay of all static CMOS gatesLogical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same currentLogical effort increases with the gate complexity

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Logical EffortLogical EffortLogical effort is the ratio of input capacitance of a gate to the inputcapacitance of an inverter with the same output current

B

A

A B

F

VDDVDD

A B

A

B

F

VDD

A

A

F

1

2 2 2

2

21 1

4

4

Inverter 2-input NAND 2-input NOR

g = 5/3g = 4/3g = 1

EE14134



From Sutherland, Sproull

EE14135


Estimated Intrinsic Delay FactorEstimated Intrinsic Delay Factor

EE14136



( )fgptCCCRktDelay

p

in

Lunitunitp

⋅+=

+⋅==

0

1γ

(Assume γ = 1)

p – intrinsic delay : gate parameter g – logical effort : gate parameter f – effective fanout

Normalize everything to an inverter:ginv =1, pinv = 1

Divide everything by τinv(everything is measured in unit delays τinv)

EE14137


Delay in a Logic GatesDelay in a Logic GatesGate delay:

d = h + p

Effort delay Intrinsic delay

Effort delay:

h = g f

Logical Effort

Effective fanout = Cout/Cin

•Logical effort is a function of topology, independent of sizing•Effective fanout (electrical effort) is a function of load/gate size

EE14138


Logical Effort of GatesLogical Effort of Gates

Intrinsic�Delay

EffortDelay

1 2 3 4 5Fanout f

1

2

3

4

5

Inverter:

g = 1; p = 12-i

nput

NAND: g = 4/

3;p =

2

Nor

mal

ized

Del

ay

EE14139


Logical Effort of GatesLogical Effort of Gates

Nor

mal

ized

del

ay (d

)t

1 2 3 4 5 6 7

pINVtpNAND

F(Fan-in)

g = 1p = 1d = f+1

g = 4/3p = 2d = (4/3)f+2

Fan-out (f)

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Add Branching EffortAdd Branching Effort

Branching effort:

pathon

pathoffpathonC

CCb

−

−− +=

EE14141


Multistage Logic NetworksMultistage Logic Networks( )

1) assume(11

=

⋅+=

⋅+= ∑∑

==

γγ

N

iiii

N

i

iii fgpfgpDelay

•Stage Effort: hi = gifi•Path Electrical Effort: F = Cout/Cin

•Path Logical Effort: G = g1g2…gN

•Branching Effort: B = b1b2…bN

•Path effort (total): H = GFB

•Path delay (total) D = Σdi = Σpi + Σhi

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Optimum Effort per StageOptimum Effort per Stage

When each stage bears the same effort:

HhN =N Hh =

Stage efforts: g1f1 = g2f2 = … = gNfN

Effective fanout of each stage: ii ghf =

Minimum path delay

( ) PHNpfgD Niii +=+= ∑ )(ˆ /1

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Optimal Number of StagesOptimal Number of StagesFor a given load, and given input capacitance of the first gateFind optimal number of stages and optimal sizing

invN NpNHD += /1

( ) 0ln /1/1/1 =++−=∂∂

invNNN pHHH

ND

NHh ˆ/1=Substitute ‘best stage effort’

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Example: Optimize PathExample: Optimize Path1

ab c

5

g = 1f = a

g = 5/3f = b/a

g = 5/3f = c/b

g = 1f = 5/c

Effective fanout, F = 5G = 25/9H = GF=125/9 = 13.9h = 1.93 (optimal stage effort) = a = 1.93b = ha/g2 = 2.23c = hb/g3 = 5g4/f = 2.59

4 H

EE14145


Example Example –– 88--input ANDinput AND

EE14146


Method of Logical EffortMethod of Logical Effort

Compute the path effort: F = GBHFind the best number of stages N ~ log4FCompute the stage effort f = F1/N

Sketch the path with this number of stagesWork either from either end, find sizes: Cin = Cout*g/f

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

EE14147


SummarySummary

Sutherland,SproullHarris

EE14148


PassPass--TransistorTransistorLogicLogic

EE14149


PassPass--Transistor LogicTransistor LogicIn

puts Switch

Network

OutOut

A

B

B

B

• N transistors• No static consumption

EE14150


Pass Transistor Logic BasicsPass Transistor Logic Basics

)()()( 2211 nn

iii

VPVPVP

VPF

+++=

= ∑Logic Function:

{ }ImpedanceHigh :

,,,1,0 Signals PassSignals Control

ZZXXV

P

iii

i

−∈==

B

B

A

F = AB + 0B = AB

0

Example: AND GateExample: AND Gate

A, B: A is Input signal, B is the Control Signal

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Example: Design of XNOR2Example: Design of XNOR2

(b) Pass-networkKarnaugh map

A as the control signalsB as the passed signals

(a) Truth table

)()( BABAF ⋅+−⋅−=

(c) Logic function

EE14152


Example: Implementation of XNOR2Example: Implementation of XNOR2

(a) Transmission Gate (b)NMOS (c)Cross-couple

EE14153


Example2: Construct Boolean FunctionsExample2: Construct Boolean Functions

•Implement:

•Truth Table:

EE14154


NMOSNMOS--Only LogicOnly Logic

00.0

xOut

In3.0

VDD

In

Outx

0.5µm/0.25µm0.5µm/0.25µm

1.5µm/0.25µm

0.5 1 1.5 2

1.0

2.0

Volt a

ge[V

]Time [ns]Suffer from

•Vt degradation (Vx = Vdd- Vt(x))•Body effect (Vsb, Vx has value and Vt(x) is bigger than Vt(0))

EE14155


NMOSNMOS--only Switchonly Switch

CL

A = 2.5 V

B

C = 2.5VM2

M1

Mn

C = 2.5 V

A = 2.5 V B

VB does not pull up to 2.5V, but 2.5V -VTNThreshold voltage loss causes

static power consumptionNMOS has higher threshold than PMOS (body effect)

EE14156


NMOS Only Logic: NMOS Only Logic: Level Restoring TransistorLevel Restoring Transistor

Mn

M2

Mr

VDDVDDLevel Restorer

B

XA Out

M1

•Advantage: Full Swing•Restorer adds capacitance, takes away pull down current at X•Ratio problem among (Mr and Mn)

EE14157


Restorer SizingRestorer Sizing

0 100 200 300 400 5000.0

1.0

2.0

W/Lr =1.0/0.25 W/Lr =1.25/0.25

W/Lr =1.50/0.25

W/Lr =1.75/0.25

Vol

tage

[V]

Time [ps]

3.0

•Upper limit on Restorer Transistor size

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Solution 2: Single Transistor Pass Gate with Solution 2: Single Transistor Pass Gate with VVTT=0=0

VDD

VDD

2.5V

VDD

0V 2.5V

Out0V

WATCH OUT FOR LEAKAGE CURRENTS

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Complementary/Differential Pass Transistor Complementary/Differential Pass Transistor Logic (CPL/DPL)Logic (CPL/DPL)

A

B

A

B

B B B B

A

B

A

B

F=AB

F=AB

F=A+B

F=A+B

B B

A

A

A

A

F=A⊕ΒÝ

F=A⊕ΒÝ

OR/NOR EXOR/NEXORAND/NAND

F

F

Pass-TransistorNetwork

Pass-TransistorNetwork

AABB

AABB

Inverse

(a)

(b)

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Differential Cascode Voltage Switch Logic (DCVSL) (p.267)

VDD VDD

PDN1 PDN2

M1 M2

Out Out

AABB

VSS VSS

Differential Cascode Voltage Switch Logic (DCVSL)

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DCVSL ExampleDCVSL Example

B

A A

B B B

Out

Out

XOR-NXOR gate

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DCVSL Transient ResponseDCVSL Transient Response

0 0.2 0.4 0.6 0.8 1.0-0.5

0.5

1.5

2.5

A B

A B

A,BA,BV

olta

g e[V

]

Time [ns]

EE14163


Solution 3: Use of Transmission GateSolution 3: Use of Transmission GateC

C

A A BB

CC

C = 2.5 V

CL

C = 0 V

A = 2.5 VB

EE14164


Analysis of TG (Transmission Gate)Analysis of TG (Transmission Gate)

outDDnGS

outDDnDS

VVVVVV

−=

−=

,

,

DDpGS

DDoutpDS

VV

VVV

−=

−=

,

,PMOS:

NMOS:

G

G

S

S D

D

peqneqTGeq

pSD

outDDpeq

nDS

outDDneq

pSDnDSD

RRR

IVVR

IVVR

III

,,,

,,

,,

,,

||=

−=

−=

+=

EE14165


Analysis of TG (I)Analysis of TG (I)

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Analysis of TG (II)Analysis of TG (II)

EE14167


Resistance of Transmission GateResistance of Transmission Gate

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Application1: Inverting 2Application1: Inverting 2--toto--1 Multiplexer1 Multiplexer

AM2

M1

B

S

S

S F

VDD

GND

VDD

A BS S

S S

F

)( BSASF ⋅+⋅=

EE14169


Application2: 6Application2: 6--T(ransistor) XOR GateT(ransistor) XOR GateTruth Table

A

B

F

B

A

B

BM1

M2

M3/M4011101110000

FAB

A

A

A

A

B=0: Pass A SignalB=1: Inverting A Signal

6T has the inverter of B

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Application3: Transmission Gate Full AdderApplication3: Transmission Gate Full Adder(to be discussed in Chapter 11)(to be discussed in Chapter 11)

A

B

P

Ci

VDDA

A A

VDD

Ci

A

P

AB

VDD

VDD

Ci

Ci

Co

S

Ci

P

P

P

P

P

Sum Generation

Carry Generation

Setup

Similar delays for Sum and Carry

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Delay in Transmission Gate NetworksDelay in Transmission Gate Networks

V1 Vi-1

C

2.5 2.5

0 0

Vi Vi+1

CC

2.5

0

Vn-1 Vn

CC

2.5

0

In

V1 Vi Vi+1

C

Vn-1 Vn

CC

InReqReq Req Req

CC

(a)

(b)

C

Req Req

C C

Req

C C

Req Req

C C

Req

C

m

In

(c)

EE14172


Delay OptimizationDelay OptimizationBuffer can be

(a) Inverter pairs(b) One inverter +Final correcting inverter

EE14173


SummarySummary

Fan-in and Fan-out of gates play an important role in CMOS circuit speed.Concept of Logic Efforts can generalize the invert chain design to complex gate chain design.Pass Transistor Logic leads low-power, low-footprint designs, but it should be used with special care.

Documents

Chapter 6 (I)access.ee.ntu.edu.tw/.../ppt/lecture_10_chapter6-1_PartI_05-15-2003.… · Logic Circuits •Static CMOS •Pass Transistor Logic V1.0 4/25/03 V2.0 5/4/03 V3.0 5/15/03