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Chapter 5a: Single-Cycle CPU DataPath. Building A CPU. We’ve built a small ALU Add, Subtract, SLT, And, Or Could figure out Multiply and Divide. What about the rest How do we deal with memory and registers? What about control operations (branches)? How do we interpret instructions?. - PowerPoint PPT Presentation
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Building A CPU We’ve built a small ALU
Add, Subtract, SLT, And, Or Could figure out Multiply and Divide...
5.1
What about the rest How do we deal with memory and registers? What about control operations (branches)? How do we interpret instructions?
The whole thing... A CPU’s datapath deals with moving data around A CPU’s control manages the data
Datapath Overview
5.1
InstructionMemory
RegistersData Memory
Read reg. num A
Read reg. num B
Write reg num
Write reg data
Read reg data A
Read reg dataB
Read address
Instruction [31-0]
Read address
Write address
Write data
Read dataResult
PC
Instructions: R-type: 3 registers I-type: 2 registers, Data
Instructions: R-type: 3 registers I-type: 2 registers, Data
ALU Computes on: R-type: 2 registers I-type: Register and data
ALU Computes on: R-type: 2 registers I-type: Register and data
Data to write intodest. register from: ALU or Memory
Data to write intodest. register from: ALU or Memory
Memory: Address from ALU Data to/from regs
Memory: Address from ALU Data to/from regs
Current Instruction: PCCurrent Instruction: PC
Instruction Datapath
5.2
InstructionMemory
Read address
InstructionPC
Add
4
Instructions will be held in the instruction memory
The instruction to fetch is at the location specified by the PC
Instr. = M[PC]
Note: Regular instruction width(32 for MIPS) makes this easy
Note: Regular instruction width(32 for MIPS) makes this easy
• After we fetch one instruction, the PC must be incremented to the next instruction
• All instructions are 4 bytes
• PC = PC + 4
R-type Instruction Datapath
5.2
Read reg. num A
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Result
Zero
ALU
Instruction
R-type Instructions have three registers Two read (Rs, Rt) to provide data to the ALU One write (Rd) to receive data from the ALU
• We’ll need to specify the operation to the ALU (later...)
• We might be interested if the result of the ALU is zero (later...)
Read reg num A
Memory Operations
5.2
Data MemoryRead address
Write address
Write data
Read dataResult
Zero
signextend
16 32
Memory operations first need to compute the effective address LW $t1, 450($s3) # E.A. = 450 + $s3 Add together one register and 16 bits of immediate data Immediate data needs to be converted from 16-bit to 32-bit
Memory then performs load or store using destination register
Read reg. num A
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
Instruction
Branches
5.2
AddResult
Sh.Left2
Result
Zero
signextend
16 32
PC + 4
To controllogic
Instruction
Branches conditionally change the next instruction
BEQ $2, $1, 42 The offset is specified as the
number of words to be added to the next instruction (PC+4)Read reg. num A
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
Control logic has to decide if the branch is taken
Uses ‘zero’ output of ALU
Take offset, multiply by 4 Shift left two
Add this to PC+4 (from PC logic)
offset
Integrating the R-types and Memory
5.3
R-types and Load/Stores are similar in many respects Differences:
2nd ALU source: R-types use register, I-types use Immediate Write Data: R-types use ALU result, I-types use memory
Mux the conflicting datapaths together Punt on the control logic for now
Data MemoryRead address
Write address
Write data
Read dataResult
Zero
signextend
16 32
Read reg. num A
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
Instruction
0
1
1
0
MemoryDatapath
Adding the instruction memory
5.3
InstructionMemory
Add
4
Read address
Instruction [31-0]
Result
PC
Simply add the instruction memoryand PC to the beginning of the datapath.
Separate Instruction and Data memories are needed in order to allowthe entire datapath to complete its job in a single clock cycle.
Data MemoryRead address
Write address
Write data
Read dataResult
Zero 1
00
1
signextend
16 32
Read reg. num A
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
Adding the Branch Datapath
5.3
InstructionMemory
Add
4
Read address
Instruction [31-0]
Result
PCData MemoryRead address
Write address
Write data
Read dataResult
Zero 1
00
1
signextend
16 32
Read reg. num A
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
AddResult
Sh.Left2
0
1
Now we have the datapath for R-type, I-type, and branch instructions.
On to the control logic!
When does everything happen?
5.3
InstructionMemory
Data Memory
AddAdd
4
Read address
Instruction [31-0]
Read address
Write address
Write data
Read dataResult
Zero
Result
Result Sh.Left2
0
1
1
00
1
signextend
PC
16 32
Read reg. num A
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
Combinational Logic:Just does it! Outputs are always just a function of its inputs (with some delay)
Registers: Written at the end of the clock cycle. (Rising edge triggered).
clk
clk
clk
Single-Cycle Design
