Chapter 5: Signal conversion

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GCE A level Electronics – Chapter 5: Signal conversion

Chapter 5: Signal conversion

Learning Objectives:

At the end of this topic you will be able to:• explain the need for signal conversion between analogue and digital form in

communications and microprocessors• describe how an op-amp summing amplifier can be used as a digital-to-analogue converter

(DAC) to convert a digital signal into an analogue signal• analyse and design a DAC based upon an op-amp summing amplifier to meet a given

specification• describe how comparators can be used as an ADC to convert an analogue signal into a

digital signal• describe the process of digitising audio signals and explain the effects of sampling rate and

resolution• analyse and design a flash converter ADC based on comparators and priority encoders to

meet a specification and describe the factors affecting the resolution• select and apply the equation for calculating the resolution of a n-bit flash converter:

• compare the difference of a digital ramp ADC and a flash ADC.

n

i/p voltage rangeresolution

2=



Digital and analogue information:

The differences between analogue and digital signals were described earlier, in the AS E-book. In most situations, real world information exists in analogue form, not digital.

Sound signals, for example, such as speech and music, are analogue. However, they are often converted into digital format - before being transmitted through a communication system or being stored for example. At the end of the process, the digital signals can be converted back to recover the original analogue signal. The advantage in doing so is that, apart from minor losses inherent in the conversion process, no other loss of quality occurs.

On the other hand, an analogue signal suffers some loss of quality each time it is copied or processed.

The conversion process involves two sub-systems - an analogue-to-digital converter (ADC), which converts information from analogue into digital format and a digital-to-analogue converter (DAC), which converts a digital signal to an analogue signal.

A block diagram of a typical audio system is shown below:

Control systems have a different function. They use sensors, monitoring quantities such as temperature, light intensity, pressure or humidity, to control output devices such as motors and lamps.

To do so:

• the analogue signals from the sensor are converted to digital format• these are processed digitally• they are then converted back to analogue format for the output signal.

In some cases, the resulting output signal simply switches a device on or off. Sometimes, it delivers variable control, making a motor rotate faster or slower, making a piezo sound louder or quieter or a lamp brighter or darker.

A block diagram of a typical control system is shown below:

Analogue sensing units:

In the E-book for the AS course, the behaviour of sensing units using thermistors, LDR’s and phototransistors was examined.



Analogue-to-digital conversion:

The ADC is a system which outputs a bigger and bigger binary number as the analogue input voltage gets bigger and bigger. Usually, the binary number produced, doubles when the input voltage doubles i.e. when the input changes from VIN to 2VIN, the output changes from ‘nnnn’ to ‘2 x (nnnn)’.

There are a number of ways to design such a circuit. One type, the flash converter is based on the behaviour of comparators, studied earlier.

Comparators

These devices were described earlier in the AS course. The output of a comparator is always saturated, either in positive saturation - as close as possible to the positive supply voltage - or in negative saturation - as close as possible to the negative supply voltage.

The relative size of the two input voltages decides which of these occur. Often, the inverting input is provided as a reference voltage, Vref. The input voltage, VIN, connected to the non-inverting input is compared with this reference voltage.

With this arrangement:

• VOUT = +VSAT when VIN is bigger than Vref.

• VOUT = -VSAT when VIN is smaller than Vref.

where:

• +VSAT = positive saturation voltage• -VSAT = negative saturation voltage.

Op-amps obey the following relationship:

VOUT = G0 × (VIN – Vref)

where G0 is the open loop gain of the op-amp (usually > 106).

Using this equation when the op-amp has an output saturation voltage of 12V, the minimum difference between VIN and Vref that changes VOUT from -VSAT to +VSAT is:

(VIN – Vref) = VOUT

G0

= 12

106

= 12 mV

The comparator can be thought of as 1-bit ADC and is the basic building block of a flash converter.



Adding more comparators

The following circuit shows a flash converterconsisting of three comparators connectedto a resistor chain of four resistors.

The resistors form a voltage divider chain,which applies a different voltage, VREF, toeach comparator. This chain is connectedto a reference voltage VREF.

In the circuit diagram, Vref1 = 0.5 V, Vref2 =1.0 Vand Vref3 = 1.5 V.

The range of analogue input voltages shouldnot exceed VREF.

The graphs show how the comparator outputs change as the analogue input, VIN, is increased steadily from 0 V to 2 V:

Although the three outputs are digital they do not form a binary sequence.



Assuming that a voltage of +VSAT corresponds to logic 1 and -VSAT to logic 0, the following table shows the sequence created:

To design a flash converter that produces a binary output, an extra block called a priority encoder is needed.

2-bit Flash Converter

The basic circuit diagram for a 2-bit flash converter is shown below:

Notice:• the analogue input signal is connected to the non-inverting inputs of the comparators• their inverting inputs are connected to various points on a resistor chain, which creates a different

reference voltage for each comparator.

Each comparator compares the analogue input signal voltage, VIN, with its reference voltage, and outputs a voltage at either positive or negative saturation level, following the rules outlined above. At this stage, the analogue signal has been converted into a set of digital signals, but not into a pure binary number.

The outputs of the comparators become inputs for the priority encoder, a combinational logic system which converts the comparator outputs into a binary number.

The uppermost comparator in the system is used to indicate that the analogue signal has exceeded the voltage range that the ADC can handle. Usually, it does so by lighting an ‘overflow’ LED.

Analogue input voltage, VIN Output A Output B Output C

0 < VIN < 0.5 0 0 0 0.5 < VIN < 1.0 1 0 0 1.0 < VIN < 1.5 1 1 0

VIN > 1.5 1 1 1



3-bit Flash Converter

As the number of output bits increase, the number of comparators and the complexity of the priority encoder increase significantly.

The circuit diagram for a 3-bit flash converter is shown below:

The main advantage of the flash converter is its speed. The conversion time, to generate the binary number from an analogue signal, is very short, typically 100ns or less.

The analogue signal is connected directly to each comparator. Their outputs switch at the same time into either positive or negative saturation. (For this reason, this type of ADC is also known as a ‘parallel A to D converter’.)

The priority encoder consists of a number of logic gates, or equivalent, which rapidly generate the required binary number at the output.

The main disadvantage is its cost. This is the result of the complexity of the circuit.

The three-bit ADC, shown above, can output eight different binary numbers, from ‘000’ to ‘111’. Each of these corresponds to a small range of analogue input voltages. For example, if the three-bit ADC is designed for analogue signals in the range 0 to 8 V, then 000 would correspond to voltages from 0 V to 1 V, 001 from 1 V to 2 V, and so on. The circuit must be able to distinguish between these voltage ranges. To do so, a comparator is set up to respond to each of these ranges. This needs seven comparators, plus one more to detect the overflow condition.

In general, a n-bit ADC requires (2n – 1) comparators connected to the priority encoder, plus one for the overflow detection, making a total of 2n comparators. Most digital systems manipulate data in the form of eight-bit binary numbers, or more. For an eight-bit flash converter, 28 (= 256) comparators are needed. Hence it is an expensive circuit.

This type of ADC is widely used in applications such as digitising music or video signals in TV tuner cards, for example, where high conversion speed is essential.



Analysing an ADC circuit:

Here is the same 3-bit ADC circuit diagram, but with component values, reference voltage, and labels, added.

The voltage dropped across the resistorchain VREF = 0.8 V.

The voltage dropped across each resistor = 0.8/8 = 0.1 V.

Hence:

• voltage at A = 0.1V• voltage at B = 0.1 X 2 = 0.2 V• voltage at C = 0.1 X 3 = 0.3 V• voltage at D = 0.1 X 4 = 0. 4V.

Assuming that the positive saturation voltage is +12 V, and negative saturation voltage is 0 V, the behaviour of the comparators is described in the table below:

Note: The maximum analogue input voltage that can be applied to an ADC without causing an overflow is equal to VREF.

Analogue input VIN

Comparator outputs / V

S T U V W X Y

VIN < 0.1V 0 0 0 0 0 0 0

0.1V < VIN < 0.2V 12 0 0 0 0 0 0

0.2V < VIN < 0.3V 12 12 0 0 0 0 0

0.3V < VIN < 0.4V 12 12 12 0 0 0 0

0.4V < VIN < 0.5V 12 12 12 12 0 0 0

0.5V < VIN < 0.6V 12 12 12 12 12 0 0

0.6V < VIN < 0.7V 12 12 12 12 12 12 0

0.7V < VIN < 0.8V 12 12 12 12 12 12 12

VIN > 0.8V Z =+12V indicating overflow



The priority encoder:

The priority encoder is a combinational logic system, which inputs signals from the comparator outputs and processes them into binary numbers.

Assuming that positive saturation (+12 V) correspondsto logic 1 and negative saturation, (0V) to logic 0, thepriority encoder for the three-bit ADC shown earlier,obeys the following truth table:

We do not need to consider output Z, from the overflow comparator, as it is not connected to the priority encoder and the ‘Analogue input’ column is shown only for reference as it plays no part in the design.

Converting the truth table into a combinational logic system is potentially a very complex problem. With seven inputs, there are theoretically 27 (= 128) possible input combinations. In reality, only the eight shown in the truth table can ever occur. The remaining 120 combinations can never occur and so are ‘don’t care’ states, when it comes to generating Boolean expressions for the logic system.

For example, when the analogue voltage, VIN, is greater than 0.3V (making U change to positive saturation,) it is also greater than 0.2V (turning T to positive saturation,) and greater than 0.1V (turning S to positive saturation.) In other words, all rows where U = 1 but S and T are logic 0 cannot exist.

By inspection, the following logic expressions are obtained:

C = V

B = T.V + X

A = S.T + U.V + W.X + Y

Analogue input VIN

Priority encoder inputs (= comparator outputs)

Priority encoder output

S T U V W X Y C B A VIN < 0.1V 0 0 0 0 0 0 0 0 0 0 0.1V < VIN < 0.2V 1 0 0 0 0 0 0 0 0 1 0.2V < VIN < 0.3V 1 1 0 0 0 0 0 0 1 0 0.3V < VIN < 0.4V 1 1 1 0 0 0 0 0 1 1 0.4V < VIN < 0.5V 1 1 1 1 0 0 0 1 0 0 0.5V < VIN < 0.6V 1 1 1 1 1 0 0 1 0 1 0.6V < VIN < 0.7V 1 1 1 1 1 1 0 1 1 0 0.7V < VIN < 0.8V 1 1 1 1 1 1 1 1 1 1



The outputs C, B and A could be generated using appropriate logic gates, or using a multiplexer or memory IC. The logic gate solution for output A is shown below:

ADC Resolution:

This is a measure of the sensitivity of the ADC, i.e. a measure of the minimum change in the input signal that will guarantee a change in the output signal.

It is closely connected to two other parameters:

• the number of bits in the output• the analogue input voltage range for the ADC (determined by VREF).

Consider a three-bit ADC with an input voltage range of 4.0V.It has eight possible outputs – ‘000’, ‘001’, ‘010’, ‘011’, ‘100’, ‘101’, ‘110’ and ‘111’.

As the analogue input voltage changes:

• inputs smaller than 0.5 V produce an output number of ‘000’• inputs of 0.5 V, or up to 1.0 V, cause the output to be ‘001’• inputs of 1.0 V, or up to 1.5 V, cause the output to be ‘010’. and so on until:• inputs of 3.0 V, or up to 3.5 V, cause the output to be ‘110’• inputs greater than 3.5 V cause the output to be ‘111’.

When the input voltage exceeds 4.0 V, the output will still be ‘111’ but the overflow indicator will be activated.

Here the resolution is 0.5 V. Whenever the input changes by more than 0.5 V, there must be a change in the output number. A change of less than that may or may not cause the output to change. (Suppose that the input sits at 0.9 V, and then increases by 0.2 V. The output will change from ‘001’ to ‘010’. However, if the input sits at 1.2 V and increases by 0.2 V, the output will not change.)



Conversion of a continuously varying analogue signal into a discrete number of voltage levels is referred to as quantization. It creates an error called the quantization error, which ranges from zero to a maximum equal to the resolution.

For a n-bit ADC, of the type considered so far:

For example, for an eight-bit flash converter of this type with an input voltage range of 10 V,

Average quantization error = 20 mV

The smaller the resolution the smaller the quantization error.

Examples

1. A five-bit flash converter has an input voltage range of 2.0 V. What is its resolution?

2. What is the input voltage range of an eight-bit flash converter having a resolution of 0.05 V?

3. An ADC is required to have a minimum resolution of 1 mV. The input voltage range is 3 V. What is the minimum number of bits needed for the ADC to provide this resolution?

resolutionAverage quantization error = 2

n

input voltage rangeResolution = 2

n 8

i/p voltage rangeResolution =

210 10 = = = 0.0391 V = 39 mV

2562

. .n 5


22 0 = = 0 0625 V2

.

.

n

n

8


2

Input voltage range resolution x 2 0 05 x 2 12 8 V

=

==

n

n

n

n


2

i/p voltage range2 = resolution

3 V2 = 1 mV

2 = 3000



Method 1: Using logarithms Taking logs of both sides: n x log102 = log103000

n = log103000

log102 = 11.6

Therefore, choose a 12-bit ADC

Method 2: Trial and error: 2n = 3000

Try n = 9: 29 = 512 too small

Try n = 10 210 = 1024 too small

Try n = 11 211 = 2048 too small

Try n = 12 212 = 4024 greater than the minimum required

Therefore, choose a 12-bit ADC.



Investigation 5.1

Set up the following ADC circuit on Circuit Wizard.

(b) Adjust V1 to 0.5 V.

Measure the voltages at X, Y and Z and the logic levels at A, B and the Overflow.

Record the results in the table.

(c) Complete the table for the other values of V1.

(d) Comment on the performance of the ADC.

(e) What is the resolution of the ADC?

Analogue input

VI

Comparator output voltage

Binary output

X Y Z B A Overflow

V1 = 0.5 V

V1 = 1.5 V

V1 = 2.5 V

V1 = 3.5 V

V1 = 4.5 V



Designing a flash ADC to meet a given specification:

The specification for an ADC includes:

• the operational input voltage range• the number of bits in the output binary number• the resolution• the speed of conversion• the power supply used.

Here, we design an ADC with the following parameters:

• number of output bits = 4• input voltage range = 0 to 4 V• comparator outputs:

• positive saturation = +10 V• negative saturation = 0 V

A four-bit flash converter requires sixteen (=24) comparators, and hence sixteen equal sized resistors in the resistor chain, (for a linear response - output number directly proportional to the input voltage.)

• The input voltage range dictates the size of the reference voltage. Hence, the reference voltage is 4 V.

• The resolution is 4 = 0.25 V, using the formula given earlier. 16

The sixteen resistors divide the 4 V referencevoltage into 0.25 V portions.

The actual value of resistor used in the chainis not important. Too small a value wouldmean that large currents flow, dissipatinglarge amounts of power.

As a rule of thumb, the resistors should always be at least 1 kΩ. In this case, 10 kΩ resistors are used.

The circuit diagram for the ADC is shown opposite, though not drawn in full.



With fifteen inputs, there are theoretically 215 (= 32768) possible input combinations. Thankfully only the sixteen shown in the table that follows can ever occur.

The priority encoder is designed in the same way as before, by examining the truth table. This time, we assume that a comparator output voltage of +10 V is seen as logic 1, and an output of 0 V is seen as logic 0 by the priority encoder.

Here are logic expressions for the priority encoder:

D = R C = N.R + V B = L.N + P.R + T.V + X A = K.L + M.N + O.P + Q.R + S.T + U.V + W.X + Y

The overflow indicator functions as in the previous example.

(The logic expressions for the 4-bit priority encoder are provided for illustration purposes only. You are not expected to be able to design a 4-bit priority encoder.)

Analogue input VIN

Priority encoder inputs (= comparator outputs)

Priority encoder output

K L M N O P Q R S T U V W X Y D C B A

VIN < 0.25 V 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0.25 V< VIN < 0.50 V 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0.50 V< VIN< 0.75 V 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0.75 V< VIN < 1.00 V 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1.00 V< VIN < 1.25 V 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1.25 V< VIN < 1.50 V 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1.50 V< VIN < 1.75 V 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1.75 V< VIN < 2.00 V 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 2.00 V< VIN < 2.25 V 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 2.25 V< VIN < 2.50 V 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 1 2.50 V< VIN< 2.75 V 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 0 2.75 V< VIN < 3.00 V 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 1 1 3.00 V< VIN < 3.25 V 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 3.25 V< VIN < 3.50 V 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 3.50 V< VIN < 3.75 V 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 3.75 V< VIN < 4.00 V 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VIN > 4.00 V Z = +10 V indicating overflow



Exercise 5.1

1. (a) A five-bit flash converter has an input voltage range of 1.5 V. What is its resolution?

(b) What is the input voltage range of a ten-bit flash converter that has a resolution of 0.04 V?

(c) An ADC is required with a minimum resolution of 500 mV. The input voltage range is 2.0 V. What is the minimum number of bits needed for this ADC?

2. The diagram shows part of the circuit for a 2-bit flash ADC.

The system meets the following specification:

Analogue input VIN

Voltage at L

Voltage at M

Voltage at N

Binary output B A

0 to 0.25 V 0 V 0 V 0 V 0 0 0.25 V to 0.50 V 0 V 0 V 12 V 0 1 0.50 V to 0.75 V 0 V 12 V 12 V 1 0 0.75 V to 1.00 V 12 V 12 V 12 V 1 1



(a) Complete the circuit diagram by:

• adding a fourth comparator so that its output indicates an overflow condition, when the analogue input voltage exceeds 1.0 V

• adding all connections needed• labelling the inverting inputs of the op-amps with a ‘-‘ and the non-inverting inputs

with a ‘+’.

(b) Calculate suitable values for resistors P, Q, R and S.

Resistor P = Resistor Q = Resistor R = Resistor S = 3. Here is the circuit diagram for an

Analogue-to-Digital converter (ADC).

(a) What is the function of the following components in this system:

(i) the priority encoder

(ii) the comparator whose output is labelled W?

(b) Calculate the resolution of this ADC.

(c) What is the analogue input voltage range for this ADC?



(d) When VREF is reduced to +1.0 V, what is the effect of this change on:

(i) resolution?

(ii) analogue input voltage range?

(e) The comparators have saturation voltages of +6 V and +0 V and VREF is set at +1.0 V. The top graph shows how the input voltage VIN changes over a period of time. Use the axes provided to draw the signals at X, Y and Z over this time.



4. Design an ADC with the following parameters:

• number of output bits = 2• input voltage range = 0 to 3 V• comparator outputs:

• positive saturation = +12 V• negative saturation = 0 V

Your design should include:

• a circuit diagram labelled with component values and reference voltage• the resolution of the ADC• a table showing the operation of the circuit• Boolean expressions for outputs A and B of the priority encoder, expressed in terms of the

inputs (Hint: Use a Karnaugh map and make use of the “don’t care” states)• the logic circuit for the priority encoder.

Circuit diagram:



Circuit operation:

Truth table for priority encoder:

Boolean expressions:

Circuit diagram for priority encoder:

Analogue input VIN

Comparator outputs /V Binary number at output

B A

VIN <

< VIN <

< VIN <

< VIN <

VIN >

Comparator outputs Binary number at output B A



Flash ADC vs digital ramp ADC

The principle of the digital ramp converter is illustrated in the following block diagram.

When the ‘Start conversion switch’ is pressed,the counter is reset and begins to count from zero.The DAC converts the binary number producedinto an analogue voltage, which is compared to the analogue input voltage. The count continues until the output of the DAC is bigger than the analogue input voltage.The display shows the current binary number,a digitised measure of the analogue input voltage.

The structure or operation of the digital ramp ADC will not be examined, but you need to be able to compare its performance with that of the flash ADC:

• for a flash ADC, conversion time is much shorter, typically a few microseconds,• (determined by the time taken for a comparator to switch, plus the time for the logic gates in the

priority encoder to process the input signals. For the digital ramp ADC, conversion time depends on the size of the analogue signal. As the counter starts from zero each time the bigger the analogue input voltage, the further it must count before the DAC output reaches that value)

• the flash ADC circuit is more complex because of the large number of comparators needed (for example, an eight-bit flash ADC requires 256 comparators)

• as a result of this, flash ADC’s are more expensive.

Digital-to-analogue converters

A digital-to-analogue converter, (DAC), generates an analogue output voltage which increases as the binary number applied to the input increases.There are a number of ways of achieving this.The one outlined here uses a modified op-amp summing amplifier circuit.

The op-amp summing amplifier:

These devices were described earlier in the AS course.

The diagram shows a two-input summing amplifier.

The output voltage, VOUT, is calculated using the formula:

VOUT = -RF V1 + V2

R1 R2

Further input signals can be added, each with its own input resistor, as shown in the circuit diagram opposite, for a four-channel summing amplifier.

The formula for this circuit is:

VOUT = -RF V1 +

V2 + V3 +

V4

R1 R2

R3 R4



Example:

Calculate the output voltage, VOUT, for the following circuit:

By using VOUT = -RF

V1 + V2

+ V3 + V4

R1

R2 R3

R4

the output voltage will be:

VOUT = -100 2 + 1.4 + 0.2 + 0.11

100 56 10 22

= -7 V

Digital signals

A digital signal is a two-state signal, consisting of a number of bits, each logic 0 (~ 0V) or logic 1 (~+VS). The place value of the bit (how much it is worth,) depends on its position:

• the least significant bit (LSB) is worth either 0 (for logic 0) or 1 (for logic 1)• the next, on the left is worth either 0 (for logic 0) or 2 (for logic 1)• the next is worth 0 or 4 and so on and so forth.

Example:

Convert the binary number 10110101 into the equivalent decimal number.



The DAC circuit takes into account these properties of digital signals:

• the input voltages take one of two values, either the value representing logic 0, usually 0 V, or that representing logic 1, usually close to the positive supply voltage (+VS)

• the output voltage takes into account the place value of the logic 1 input signals, by having a voltage gain that reflects this place value

• in other words, if the input receiving the least significant bit (LSB) has a voltage gain of ‘G’, then the input connected to the next bit must have a gain of ‘2G’, the next a gain of ‘4G’ and so on

• In DAC circuits based on the summing amplifier, this is achieved by successively reducing the size of the input resistor. When the LSB input resistor is R, the next input resistor will be R, the next R 2 4and so on.

The design is based on an inverting amplifier, and so, when using positive logic (logic 1 = +VS,) the output voltage is negative.

• it must be powered from a split power supply, offering voltage rails at +VS, 0V and –VS• to overcome the inversion, a second inverting amplifier often follows the first, often with a voltage

gain of simply -1.

The next circuit diagram shows these ideas incorporated into a four-bit DAC:

Choosing resistor values for this circuit

It is very easy to saturate the output in a circuit like this. The simplest way to avoid this is to use fractional voltage gains for the summing amplifier.

In the above circuit, for example:

• input A, (LSB) has a voltage gain of 1

24

• input B has a gain of 1

12

• input C 1 6

• input D (MSB) 1

3

.



Analysing a DAC circuit:

To analyse the above circuit:

• think of it as four inverting amplifiers combined so that the output voltage is the sum of their outputs• the second op-amp has a voltage gain of -1, and so simply reverses the polarity of the output signal• assume that 0 V represents a logic 0 signal, and +12 V a logic 1.

For example:

1. When the input is 00012:

• A = 12 V and B = C = D = 0 V

• voltage gain on input A = - RF

= - 10

RIN 240

• so its output = - 12 x 10

= - 0.5 V 240

• the other inputs are set to 0 V and so output 0 V.

The final output = - (-0.5 + 0 + 0 + 0) = +0.5 V

2. When the input is 10112:

• A = B = D = 12 V and C = 0 V

• voltage gain on input A = − 10 , and its output = - 12 x 10 = -0.5 V

240 240

• voltage gain on input B = − 10 , and its output = - 12 x

10 = -1.0 V

120 120

• voltage gain on input D = − 10 , and its output = - 12 x

10 = -4.0 V.

30 30

The final output = - (-0.5) + (-1.0) + 0 + (-4.0) = +5.5 V



DAC output - summary

The behaviour of the four-bit DAC can be summarised in two ways:

• as a table of output voltages

• as a graph.

Viewed as a graph, the results show the characteristic staircase waveform. The output is analogue - it gets bigger as the digital input number gets bigger. However, it does not change continuously but rises in steps, often referred to as quantization steps.

The step size depends on the voltage gain of the least significant input of the DAC and the voltage that represents logic 1. Step size = VL1

RF

R1

VL1 = voltage corresponding to logic 1 RF = feedback resistance R1 = input resistance for least significant input.

Applying this formula to the example above, step size = 12 X 10k

= 0.5 V - the same answer as that 240k

obtained by calculating VOUT for an input of ‘0001’.

Binary number input V1 /V VOUT /V

D C B A 0 0 0 0 0 0 0 0 0 1 -0.5 0.5 0 0 1 0 -1.0 1.0 0 0 1 1 -1.5 1.5 0 1 0 0 -2.0 2.0 0 1 0 1 -2.5 2.5 0 1 1 0 -3.0 3.0 0 1 1 1 -3.5 3.5 1 0 0 0 -4.0 4.0 1 0 0 1 -4.5 4.5 1 0 1 0 -5.0 5.0 1 0 1 1 -5.5 5.5 1 1 0 0 -6.0 6.0 1 1 0 1 -6.5 6.5 1 1 1 0 -7.0 7.0 1 1 1 1 -7.5 7.5



Investigation 5.2

(a) Set up the 4-bit DAC circuit shown below.

(b) Measure and record the readings on voltmeters V1 and VOUT with all four switches open.

(c) Complete the table by closing the switches in the order shown and recording the readings on voltmeters V1 and VOUT.

(d) Comment on how well the results compare with the table given on page 24.

Binary number input V1 /V VOUT /V

D C B A 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1



Exercise 5.2

1. Here is the circuit diagram for a three-bit DAC.

Calculate the output voltage, VOUT, when the following binary numbers are applied to the input:

(a) 011

(b) 101

(c) 111

2. Here is the circuit diagram for a digital-to-analogue converter (DAC).

The most significant bit of the binary number is applied to input C, and the least significant bit to input A. The outputs of the op-amps saturate at +12 V and -12 V.



(a) What is the gain of amplifier Y?

(b) The following voltages are applied to inputs A, B and C:

• VA = +5 V• VB = 0 V• VC = 0 V

Calculate:

(i) V1

(ii) V2

(c) What is the maximum value of output voltage V2 that this 3- bit DAC will produce?

(d) The system uses +5 V to represent logic 1 and 0 V to represent logic 0.

Use the axes provided to draw a graph showing the relationship between V2 and the digital input signal, for the four values of input given.

Indicate the scale you are using for the vertical axis.



Designing a DAC to meet a given specification:

The performance of a DAC can be described in a number of ways, including:

• the number of bits that can be inputted• the voltage range for the output• the step size for the output voltage• the speed of conversion• the power supply used.

Here, we design a DAC with the following parameters:

• number of input bits = 4• output voltage range = 0 to 12 V• logic 1 = 8 V and logic 0 = 0 V• power supply = +15 V / 0 V / -15 V.

In general, a ‘n’-bit DAC will have 2n output voltage levels, with 2n – 1 steps between them.

As the graph given earlier shows, a four-bit DAC produces sixteen (= 24) output voltage levels, with fifteen ‘steps’ (24 – 1) between them.

These fifteen steps must cover the 0 to 12 V voltage range. Each step corresponds to a voltage change of (12 / 15) = 0.8 V.

Using the formula quoted earlier: Step size = VL1

RF

R1

where VL1 = voltage corresponding to logic 1 = 8 V RF = feedback resistance R1 = input resistance for least significant input, 0.8 = 8 x RF

so that: R1

RF = 0.1

R1

R1 = 10 x RFThe following values satisfy this requirement: RF = 10 kΩ R1 = 100 kΩ

In order to get the correct weighting for the voltage gains for the four inputs, the input resistors are in the ratio R1,

R1 , R1 and R1.

2 4

8

The final circuit diagram is shown below:



The two resistors used in the second inverting amplifier can have any value, as long as both are of equal resistance (to give a voltage gain of -1) and have resistance greater than 1 kW (to reduce the size of the current flowing in them, and hence the power dissipated.)

Exercise 5.3

1. The diagram shows the circuit for a three-bit digital-to-analogue converter. In this system, logic 1 is 12 V and logic 0 is 0 V.

(a) Calculate suitable values for the resistors so that the DAC has the following characteristics:

R1 =

R2 =

R3 =

R4 =

Digital input Output voltage C B A

0 0 0 0 V 0 0 1 - 0.5 V



(b) The DAC is connected to a counter, as shown in the following diagram.

Initially, the counter is reset.

Then ten pulses are sent into the counter.

Use the axes provided below to sketch the resulting output signal as this happens.



2. Design a DAC with the following characteristics:

• number of input bits = 3• output voltage range = 0 to 14 V• logic 1 = 10 V and logic 0 = 0 V• power supply = +15 V / 0 V / -15 V.

The design must use the following components:

• two op-amps• two 220 kΩ resistors• one 20 kΩ resistor• one 4 kΩ resistor• two other resistors, for which you must calculate the resistance values.

Circuit Diagram



Digitising audio signals

Analogue recording media, such as magnetic tape, suffer from noise. Each time an analogue recording is copied, more noise is introduced and the quality is reduced - once noise is added to an analogue signal it cannot be removed.

In digital recording, the analogue waveform is sampled at evenly-spaced time intervals. Each sample generates a binary number representing the amplitude of the analogue signal at that time. Digital recordings can be copied repeatedly without introducing additional noise.

The quality of a digital recording depends on:

• Sample rate:• must be more than twice the highest audio frequency present to allow the original

signal to be reconstructed from the samples, (Nyquist sampling theory - considered in more detail in a later chapter.)Common sampling rates:

• 8 kHz, (for speech signals)• 44.1 kHz (for music signals).

• Number of bits in a sample:• as this increases:

• resolution increases• quantization error decreases• quality of the recording increases• but• amount of storage space increases.

Audio CDs and most computer audio file formats use 16-bit. Other common bit formats are 12-bit, 24-bit and 32-bit.

A block diagram of a typical digital record/playback system is shown below.

Suppose that we want to record and playback audio signals up to a frequency of f kHz.

Recording:

The cut off frequency of the low pass filter on the input (recording) section must also be f kHz to remove any frequencies present that are too high for the chosen sampling rate. The sampling clock frequency must be greater than 2f kHz.

At each rising edge of the sampling clock pulse the sampling gate outputs the amplitude of the analogue signal at that instant.

The ADC then converts each sample of the analogue information into an n-bit word.



The following image illustrates some signals obtained during this sampling process:

Example:

An analogue signal is sampled at a frequency of 30kHz and converted into a 14-bit binary code. The signal is recorded for 10 minutes.

(a) Calculate the bit-rate and the file size of the digitized signal.

Bit-rate = Sampling frequency x no. of bits per sample

= 30 x 14 = 420 kbits

(420 kbps) second

File size = bit-rate x sampling time (in seconds)

= 420 x 600

= 252000 kbits (252 Mbit)

(b) The reference voltage of the ADC is 3 V. Determine the resolution of the ADC and the average quantization error.

This example shows that quantization error is very small for large values of n.

n 14


23 = = 244 mV

2

resolution 244 mVAverage quantization error = 122 mV2 2

= =



Digital signal processor:

This controls the format in which the audio files are stored. They can be stored uncompressed as ‘.wav’ files or compressed, to save space, as ‘.mp3’ or ‘.wma’ files for example. In addition, digital processing effects can be applied such as reverberation or pitch change.

Playback:

To playback the audio signal, the digital signal processor outputs each n-bit word, (fourteen bits in the example above), in parallel to the DAC. The DAC output is the staircase waveform described earlier.

This is passed through the reconstruction filter, another low-pass filter, which ‘smooths out’ the quantization steps as shown below. The sample rate has been increased to show the effect more clearly.

Exercise 5.4

1. For each of the following signals, determine the minimum sampling frequency required:

Signal Frequency range Sampling frequency A 200 Hz to 4 kHz

B 100 Hz to 5 kHz

C 80 Hz to 6.8 kHz

D 120 Hz to 8.2 kHz



2. A digital recording system uses a 24-bit encoding system. The maximum voltage range is 5 V.

Calculate:

(a) the resolution of the digitised signal

(b) the average quantization error.

3. A recording studio creates a 74 minute compact disc using a 16-bit format and a sampling frequency of 44.1 kHz.

Calculate how much data is stored on the disc.

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Chapter 5: Signal conversion