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UNIT 5 CMOS INVERTERprepared by Azhani binti Hashim1SOURCES OF CAPACITANCEIntrinsic capacitance is composed of diffusion and overlap capacitances.Extrinsic capacitance is contributed by wire and connecting gate.Wiring.Go to Slide 23STATIC CMOS INVERTERSwitch model of CMOS inverter:An infinite off-resistance : (|VGS| < |VT|)An infinite on-resistance : (|VGS| > |VT|)When NMOS on?When PMOS on?

STATIC CMOS INVERTERSWITCH MODELS OF CMOS INVERTERWhen Vin is high and equal to VDD, the NMOS transistor is on, while the PMOS is off. A direct path exists between Vout and the ground node, resulting in a steady-state value of 0V. When the input voltage is low (0V), NMOS and PMOS transistors are off and on, respectively. A path exists between VDD and Vout, yielding a high output voltage.

STATIC CMOS INVERTERProperties of static CMOS:High noise margin due to high output equal to VDD and low output equal to GND.Ratioless. Logic level not depends on transistor size.Output impedance is low due to finite resistance between:Output and VDD.Output and GND.resulting less sensitive tonoise and disturbances.

STATIC CMOS INVERTERProperties of static CMOS:Input resistance is high due to the gate of MOS transistor is perfect insulator. Therefore the input of inverter only connects to transistor gate, the steady-state input current nearly zero. Resulting this CMOS inverter can have an infinite fan-out theoritically. Practically, fan-out increases the propagation delay.STATIC CMOS INVERTERProperties of static CMOS:No direct path exists between the supply and ground. Resulting no static power consumption by gate terminal.

static power consumption is power dissipation for dc supply only. 7STATIC CMOS INVERTERCMOS Inverter Load linesThe PMOS I/V relations :

Graph for IDSn vs VDSn ?What DC operating point means?"The application of a DC voltage in forward bias mode to a circuit containing a diode will result in a specific DC voltage and DC current across the diode, known as the DC operating point, Q point (VDQ, IDQ)."8STATIC CMOS INVERTERCMOS Inverter Load linesLoad-lines curve of PMOS are obtained by mirroring x-axis and horizontal shift over VDD.

What DC operating point means?"The application of a DC voltage in forward bias mode to a circuit containing a diode will result in a specific DC voltage and DC current across the diode, known as the DC operating point, Q point (VDQ, IDQ)."9STATIC CMOS INVERTERCMOS Inverter Load lines

STATIC CMOS INVERTERCMOS Inverter Load linesFor DC operating point to be valid :current for NMOS and PMOS must be equal.DC point must be located at the intersection of corresponding load lines.Intersection : (Vin = 0, 0.5, 1, 1.5, 2 and 2.5V) Observation : all operation points are at high or low output level.What DC operating point means?"The application of a DC voltage in forward bias mode to a circuit containing a diode will result in a specific DC voltage and DC current across the diode, known as the DC operating point, Q point (VDQ, IDQ)."11

STATIC CMOS INVERTERCMOS Inverter Load lines

STATIC CMOS INVERTER

STATIC CMOS INVERTERCMOS Inverter Voltage Transfer Characteristicshow very narrow transition zone.A small change in input voltage results in a large output variation.

STATIC CMOS INVERTERSwitch model of dynamic behavior of static CMOS inverter:

STATIC CMOS INVERTERCL = output capacitance which composed:drain diffusion capacitances of the NMOS and PMOS transistor.Capacitance of the connecting wires.Input capacitance of the fan out gates.

Back to Slide 40STATIC CMOS INVERTERThe gate response time is determined by the time it takes to charge the CL through Rp. Therefore, propogation delay are proportional to constant RpCL.A fast gate is built either by keeping CL small or decreasing the Rp.How to decrease resistance?

STATIC CMOS INVERTERDecreasing RP or Rn can be achieved by increasing ratio.

Small transistor sizing give better performance of CMOS inverter.

STATIC CMOS INVERTERRobustness of CMOS Inverter:Switching ThresholdNoise marginROBUSTNESS OF CMOS INVERTERSwitching ThresholdSwitching Threshold, VM is defined as point where Vin = Vout.PMOS and NMOS are saturated since VDS = VGS.

ROBUSTNESS OF CMOS INVERTERAn analytical expression for VM is obtained by equating the currents through the transistors.

Therefore, VM equation is:

Equation 5.3 can be simplified:

Generally VM located around the middle of voltage swing.

Kp or kn is gain factor of the transistor28ROBUSTNESS OF CMOS INVERTERFrom equation 5.2, the required ratio of PMOS vs NMOS transistor sizes for desired VM can be obtained.

ROBUSTNESS OF CMOS INVERTERThe the above example, setting the ratio to 3, 2.5 and 2 yields VM of 1.22V, 1.18V and 1.13V respectively.First observation :Small variation of the ratio do not give big effect on VM. Therefore, VM relatively insensitive to variation in the device ratio.

ROBUSTNESS OF CMOS INVERTER

ROBUSTNESS OF CMOS INVERTERVin has a very noisy zero value. Passing this signal through a symmectrical inverter would lead to erroneous value.

ROBUSTNESS OF CMOS INVERTERSolution for this erroneous is by raising the threshold of the inverter.How to increase VM?

ROBUSTNESS OF CMOS INVERTERHow to increase VM? Increasing the width of PMOS moves VM to VDD. Increasing the width of NMOS moves VM to GND. the inverter are called asymmetrical inverter due to changing on VM value. However, changing VM to suitable value are not easy, due to first observation on device ratio.DEVICE VARIATION ON VTC CURVEThe devices sizes have only a minor impact on the switching threshold of the inverter, VM.

From figure 5.11, the variations mostly cause a shift in the VM but the operation of the gates is by no means affected.This prove robustness behaviour on wide range of device variation.

SCALING THE SUPPLY VOLTAGEReducing the supply voltage indiscriminately has a positive impact on the energy dissipation. But, is absolutely detrimental to the performance on the gate.The dc-characteristic such as the transistor threshold (VT) becomes sensitive to variations in the device.Scaling the supply voltage means reducing the signal swing. Its helps reduce the internal noise but makes the design more sensitive to external noise sources that do not scale.detrimental = memudaratkan37SCALING THE SUPPLY VOLTAGE

DYNAMIC BEHAVIOR OF CMOS INVERTERSwitch model of dynamic behavior of static CMOS inverter:

A fast gate is built either by keeping the CL _______.

DYNAMIC BEHAVIOR OF CMOS INVERTERThis figure shows the schematic of cascaded inverter pair. It includes all the capacitances influencing Vout. CL breaks down into Cgd12, Cdb1, Cdb2.

DYNAMIC BEHAVIOR OF CMOS INVERTERGate-Drain Capacitance, Cgd12.M1 and M2 are either in cut-off or in the saturation mode. This contribute to Cgd12 (overlap capacitances of M1 and M2).Using lumped capacitor model (getting CL), require this gate-drain capacitor replaced by a capacitance-to-ground. Miller effect.

DYNAMIC BEHAVIOR OF CMOS INVERTERMiller Effect

During a low-high or high-low transition, the terminals of the gate-drain capacitor are moving in opposite direction. The capacitance-to-ground must have a value that is twice as the gate-drain capacitor.

DYNAMIC BEHAVIOR OF CMOS INVERTERDiffusion Capacitance, Cdb1 and Cdb2.The capacitance between drain and bulk due to the reverse-biased pn junction.It is a nonlinear capacitor and depends heavily on the applied voltage.Best approach is to replace this nonlinear capacitor by a linear one by using a multiplication factor Keq.