Chapter 5 Digital Electronics - Walther-Meißner-Institutdecoder A memory cell B decoder B memory cell A address memory I/O B address register I/OC carry out carry out data in function

Chapter 5

Digital Electronics

AS-Chap. 5 - 2

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fast (< 100 GHz) low-power (aJ / gate)

5.1 Superconductivity and Digital Electronics

requires cooling new technology new periphery (power supply, packaging, ...)

AS-Chap. 5 - 3

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The Cryotron (1956)

Icontr Igate Icontr

Igate

0 1

(a) (b)

5.1.1 Historical Development

• low switching speed of ≈ 10 ns limited by the L/R time

• control line has higher critical magnetic field switching of gate line into normal state

AS-Chap. 5 - 4

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Icontr Igate

0 1

(a)

Icontr

Igate

0 1

(b)

The Josephson Switch (1966, Matisoo, IBM)


JJ JJ

• critical current of dc SQUID is suppressed below Igate by magnetic field generated by control line switching to voltage state

• sub-ns switching speed achievable

AS-Chap. 5 - 5

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Rapid Single Flux Quantum (RSFQ) Logic (1985)


(Likharev, Nakajima)

AS-Chap. 5 - 6

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1. Fast, low power

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-12

10-11

10-10

10-9

10-8

10-7

ga

te d

ela

y (

s)

power dissipation / gate (W)

5.1.2 Advantages of Josephson Switching Devices

AS-Chap. 5 - 9

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2. Matched superconducting striplines for wiring

3. Junction technology available (Nb based)

for 1 Mio. switching elements

5.1.2 Advantages of Josephson Switching Devices

W: line width tI: insulator thickness tM: magnetic thickness e: dielectric constant

AS-Chap. 5 - 10

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1. no transistor-like superconducting devices limited gain, fan-out, small parameter spread of Josephson junctions required

5.1.2 Disadvantages of Josephson Switching Devices

AS-Chap. 5 - 12

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Ic

I

V 2D/e

Igate

Igate Icontr IL

Ic Ls RJ(V) C RL

5.2 The voltage state Josephson logic

• Josephson junction stays in the voltage state after switching latching logic

• to switch back to the zero-voltage state the gate current has to be switched off

AS-Chap. 5 - 13

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JJ RL

Ib

Ig

Ls C R(V)

5.2 The voltage state Josephson logic

Simplified circuit diagram

AS-Chap. 5 - 14

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Characteristic Times

5.2.1 Operation Principle and Switching Times

with

AS-Chap. 5 - 15

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Switching Speed 1. Turn-on delay:


3. Steering time:

2. Rise time:

AS-Chap. 5 - 16

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0 20 40 60 t (ps)

0 20 40 60 t (ps)

I gate

+ I co

ntr

I L

tt tr

0

DI


AS-Chap. 5 - 18

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5.2.2 Power Dissipation

Ic

I

V Vg = 2D/e

Igate

for Nb-junction technology:

𝑉𝑔 ≃ 3 mV

𝐼𝑐 ≥ 1 mA @ 4.2 K to avoid thermally activated processes

with 𝑉𝑔 ≃ 𝐼𝑐𝑅N and 𝐼𝑐 ≥ 1 mA ⇒ 𝑅N ≤ 3 Ω

𝑅sg ∼ 10 ⋅ 𝑅N ⇒ 𝑅sg ≤ 30 Ω

⇒ 𝑃diss ≤ 3 × 10−7 Watt ⇒ 𝐸 = 𝑃diss ⋅ 𝜏 ≤ 3 × 10−18 J

AS-Chap. 5 - 19

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comparison to semiconductor technology

AS-Chap. 5 - 20

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3) 1. latching nature of Josephson junction based switch requires to

switch off the bias current

2. global clock system required

3. ac power source Josephson junctions biased with ac current source Shapiro steps

4. switching back into the zero voltage state takes long time problem to recapture the phase in local minimum running state may occur, if we switch on the bias current after a too short time punchthrough effect

5.2.3 Global Clock, Punchthrough

AS-Chap. 5 - 21

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5.2.4 Josephson Logic Gates

general requirements:

• high fan out: a single switching gate should be capable of triggering N

consecutive gates

• large operating margins for stable operation and large tolerable parameters

spread

• small size allowing for very large scale integration (VLSI)

• short switching time allowing for high clock frequency

• low power dissipation allowing for high integration density

• sufficient input -- output isolation allowing for directionality of logic signals

AS-Chap. 5 - 22

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magnetically coupled gate

directly/galvanically coupled gate:

Icontr Igate

Icontr Igate

2Ic

Igate

S

R

Ism(Icontr)

Icontr

Ic Ic

Ic Ic

2Ic

Igate

S

R

Ism(Icontr)

Icontr

0

0

Ism

Ism


AS-Chap. 5 - 23

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Icontr

Ic 2Ic Ic

Rd Rd

Igate

RL

Icontr 0

S

R

(a) (b) Is

m

Igate

A

B

3-Junction Interferometer Logic (JIL) Gate


AS-Chap. 5 - 25

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IA

Ic 3Ic

Rd

3L

RL

IA 0

S

R

(a) (b) IB

Igate

A

B

L

IB

Igate

Current Injection Device (CID)


AS-Chap. 5 - 27

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Icontr J2

RL

Icontr 0

S

R

(a) (b)

Ic1

Igate

Igate

J1

Ism

Ic1+Ic2

Ic1-Ic2

Ioff

Josephson Atto Weber Switch (JAWS)


AS-Chap. 5 - 29

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Icontr

RL

Icontr 0

S

R

(a) (b) Igate

Igate

Ism

Ic1+Ic2

Ic1

Directly Coupled Logic (DCL) Gate


AS-Chap. 5 - 31

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Icontr

RL

(a) (b) Igate

R3

RBP

Icontr J2

R4 RL J1

Igate

J3

R3

Resistor Coupled Josephson Logic (RCJL) Gate


AS-Chap. 5 - 33

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Icontr

RL

Icontr 0

S

R

(a) (b) Igate

Igate

Ism

Ri

Rp

J1

A

B

J2

J3

J4

4-Junction Logic (4JL) Gate


AS-Chap. 5 - 35

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AS-Chap. 5 - 36

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NDRO: Non-Destructive Read-Out DRO: Destructive Read-Out Speed: ≈ CPU speed

5.2.5 Memory Cells

AS-Chap. 5 - 37

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Igate

write write

L/2 L/2

read J3

J1 J2

NDRO

5.2.5 Memory Cells

“0” no flux in the loop no circulating current junction J3 is in zero voltage state: 𝑽 𝑱𝟑 = 𝟎 “1” a single or several flux quanta in the loop finite circulating current junction J3 is in voltage state: 𝑽 𝑱𝟑 ≠ 𝟎

bias current of J3 is below its zero field critical current

AS-Chap. 5 - 38

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Icontr 0

Ism

``0” ``1”

WR1 WR0

Rea

d

2Ic

J1 J2

control line Icontr

Igate

L

Igate

DRO

5.2.5 Memory Cells

“0” no flux in the loop threshold characteristic 𝐼𝑠

𝑚 𝐼contr is peaked at 𝐼contr = 0

“1” a single or several flux quanta in the loop threshold characteristic 𝐼𝑠

𝑚 𝐼contr is peaked at 𝐼contr ≠ 0 corresponding to a single flux quantum in the SQUID loop

“READ” vary 𝐼gate and 𝐼contr allong the green arrows:

voltage state for “1” and zero voltage state for “0” memory content is destroyed during read-out

AS-Chap. 5 - 40

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5.2.5 Memory Cells

AS-Chap. 5 - 41

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MUX shift

Q register

MUX shift

MUX MUX destination controller

source controller

function controller

output controller

A decoder

A memory

cell

B decoder

B memory

cell

A address B address memory I/O

register

I/OC

carry out carry out

data in

function

control

carry in

output

control

destination

control

source

control

ALU

5.2.6 Microprocessors

AS-Chap. 5 - 43

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ETL-JC1: integrating Josephson element based on niobium into 4LSI chips, it demonstrated the principle of Josephson computer.

Josephson register and arithmetic logic unit.


AS-Chap. 5 - 44

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AS-Chap. 5 - 45

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AS-Chap. 5 - 46

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(20

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5.3 RSFQ Logic

• nonlatching logic,

• clock frequencies above 100 GHz,

• requirement of overdamped Josephson junctions,

• low power consumption: 𝑃diss ⋅ 𝜏 ≃ 10−18 J per bit.

AS-Chap. 5 - 47

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S1

S2

S3

Sn

Sout

V(t)

t

S1

S2

Sout

``0”

``1”

T

T

t t´

5.3.2 Information in RSFQ Logic

AS-Chap. 5 - 49

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Ic

I

V IcRL

Igate

Igate + Icontr

V

t 0 0

0

1 0

Igate Icontr IL

Ic Ls RL

Ic

I

V 2D/e

Igate

Igate + Icontr

0

1

0

5.3 RSFQ Logic

latching voltage state logic

non-latching flux quantum logic

AS-Chap. 5 - 50

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Ic

I

V IcRL

Igate

Igate + Icontr

V

t 0 0

0

1 0

Igate Icontr IL

Ic Ls RL

Ic

I

V 2D/e

Igate

Igate + Icontr

0

1

0

5.3 RSFQ Logic

latching voltage state logic

non-latching flux quantum logic

AS-Chap. 5 - 51

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-1.0

-0.5

0.0

0.5

1.0

I(t)

/ I

c

0 10 20 30 40 500.0

0.5

1.0

1.5

2.0

V(t

) / I c

R

t / tc

(a)

(b)

5.3.1 Basic Components of RSFQ Circuits

generation of RSFQ pulses

AS-Chap. 5 - 52

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SFQ pulse generation

pulse duration: 𝚽𝟎/𝟐𝑰𝒄𝑹𝑵 ≃ 1 ps for 𝐼𝑐𝑅𝑁 = 1 mV


AS-Chap. 5 - 53

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Igate

L

SFQ out

J1

J2

ramp in

Icontr

Icontr

0

Ism

t pulse reset

I1

I2

Vout

0 t

Vout

0 Icontr

``0” ``1”

Igate

I1 I2

L2

SFQ out

J2

J1

dc in

Igate

Vout

L1

L3 J3

(a) (c)

(b) (d)


dc to SFQ converter

AS-Chap. 5 - 54

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(20

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J1 J2 J3

Igate,2 Igate,3

L1 L2 L3 A B

J1

L1 A

J2

L2

J3

L3

B

C

Igate,1

Igate,2

Igate,3

J2

Igate

B J1

L2 A

L1

Josephson transmission line

buffer stage pulse splitter


AS-Chap. 5 - 56

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J1 J2

Igate

L

F LS

LR

JS

JR

S

R

LF

0 1

Icirc

Ism

IS

``0” ``1”

Igate

IR

(a) (b)

RS flip-flop or DRO register


AS-Chap. 5 - 57

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J1 J2

Igate,2 L

C LS

LR

JS

JR T L3

0 1

Icirc

OR gate A

B

Igate,1

J1 J2

Igate,A L

LS

LR

JS

JR T

0 1

Icirc

J1 J2

Igate,B L

LS

LR

JS

JR T L3

0 1

Icirc

B

A L3

JA

JB

JA

JB

JC

C

Igate,C

AND gate

5.3.3 Basic Logic Gates

AS-Chap. 5 - 58

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J1 J2

Igate

L

out

LS

LR

JS

JR

in

T

0 1

Icirc

J3

NOT gate


AS-Chap. 5 - 59

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Igate

0 1

Icirc

Igate

0 1

Icirc

Igate

0 1

Icirc

Igate

0 1

Icirc

Igate

T

out in

shift register


AS-Chap. 5 - 60

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simulation: maximum delay about 6𝜋𝜏𝑅𝐿

overdamped Josephson junctions:

5.3.5 Maximum Speed of RSFQ Logic

3 µm technology: 2𝜋𝜏𝑅𝐿 ≃ 3 ps

AS-Chap. 5 - 61

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but: power dissipation mainly determined by dissipation in biasing resistors: ≈ 1µW/gate


with 𝐼𝑐 ≃ 100 𝜇𝐴 and ∫ 𝑉𝑑𝑡 = Φ0

AS-Chap. 5 - 62

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Applications of RSFQ

5.3.7 Prospects of RSFQ

AS-Chap. 5 - 63

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AS-Chap. 5 - 64

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Pseudo random bit generator, operated up to 17 GHz


AS-Chap. 5 - 66

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________________________

Stony Brook ____________________________________________

PetaFLOPS Scale Computing:

Speed and Power Scales (Year 2006)

Semiconductors (CMOS)

Performance: > 100K chips @

<10 GFLOPS each

Power: >150 W per chip

total >15 MW

Footprint: >30x30 m2

Latency >3 ms

Superconductors (RSFQ)

Performance: 4K processors @

256 GFLOPS each

Power: 0.05 W per PE node

total 250 W @ 5 K

(100 kW @ 300 K)

Footprint: 1x1 m2

Latency 20 ns

K. K. Likharev, SUNY Stony Brook


AS-Chap. 5 - 67

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K. K. Likharev, SUNY Stony Brook

5.3.8 Fabrication Technology

AS-Chap. 5 - 68

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1 THz

HTS RSFQ (??)

100 GHz 30M JJ

3M JJ 0.4 mm

300K JJ 0.8 mm

10K JJ 1.5 mm

3.5 mm

10 GHz 0.05 mm

0.07 mm

0.10 mm

0.12 mm

0.14 mm

0.20 mm

1 GHz

"no known solutions"

optical lithography

100 MHz

1995 1998 2001 2004 2007 2010

Year

RSFQ ROADMAP (VLSI circuit clock frequency)

RSFQ (Stony Brook Forecast)

CMOS (SIA Forecast 1997)

LTS RSFQ

5.3.9 RSFQ Roadmap

________________________

Stony Brook ____________________________________________

AS-Chap. 5 - 70

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x(t)

0

x (tk)

t 0

1

2

3

4

5

6

T tk

ym

5.4 Analog-to-Digital Converters

step 1: transform the time-continuous signal 𝑥 𝑡 into a time-discrete signal 𝑥𝑘 = 𝑥 𝑡𝑘 : 𝑡𝑘 are the points in time at which the signal is sampled, usually one writes 𝑡𝑘 = 𝑘 ⋅ 𝑇, with 𝑘 an integer and 𝑇 the sampling period

ADC – principle of operation

step 2: transform the real number 𝑥 into a set of discrete numbers 𝑦𝑚, which most conveniently are represented by a set of integer numbers 𝑦𝑚 = 𝑚, smallest step in the quantization process: least significant bit (LSB)

ADC converts an analog signal 𝑥 𝑡 into a digital signal 𝑚, 𝑘 , 𝑚, 𝑘 = integer numbers

AS-Chap. 5 - 71

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superconducting ADCs are based on the principle of flux quantization in a closed superconducting loop and the fast switching of Josephson junctions


• practical devices: the input signal S to be measured (e.g. a current or voltage) is converted into a magnetic flux Φ (cf. SQUID sensors)

• corresponding circuit has to determine the integer 𝑚 satisfying the relation

𝑚 − 1 Φ0 ≤ Φ ≤ 𝑚 Φ0 the flux generated by the input signal S is determined within an accuracy of Φ0/2

• important fact: the quantization process relies on a fundamental physical constant and therefore has an inherent precision not known for semiconductor devices

• there exist various ways to determine the number 𝑚 and hence types of ADCs.

AS-Chap. 5 - 72

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superconductor technology exhibits a set of characteristics uniquely suitable for the implementation of ADC:

• high switching speed of JJs providing a very short aperture

time 𝜏𝑎 and hence a very high speed and resolution for ADCs

• low power consumption

• natural quantization

• quantum accuracy

• high sensitivity

• low noise


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5.4.1 Foundations of ADCs

resolution

• both the range of the input signal 𝑥 and the number of output values 𝑦𝑚 is limited

• the number of output values is usually given as a power of 2:

- n-bit ADC integer numbers range from 0 to 2𝑛 − 1

- representation of any integer number in this range:

𝑥 = 𝑥020 + 𝑥121 + 𝑥222 + ⋯ + 𝑥𝑛−12𝑛−1 with 𝑥0, 𝑥1, 𝑥2, … , 𝑥𝑛−1 = 0 or 1

• scale and offset the input signal in the analog domain so that x′ = 𝑎𝑥 + 𝑏

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0 1 2 3 4 5 6 7 0

1

2

3

4

5

6

7

analog input

dig

ital

ou

tpu

t, e

rro

r

x

xmin

xmax

0

2n-1

ym


scaling & offset

resolution

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• example:

voltage measurement with 16 bit ADC (216 = 65536 quantization levels)

full scale measurement range is -10 V to +10 V

ADC voltage resolution is: 10𝑉− −10𝑉

65536=

20𝑉

65536= 0.305 mV


resolution

• effective number of bit (ENOB):

analog signal has limited signal-to-noise ratio (SNR)

it is impossible to resolve the signal beyond a certain number of bits

required SNR per bit:

20 log10 2 = 6.02 dB (16 bit ADC: SNR = 96.32 dB)

AS-Chap. 5 - 76

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accuracy

• the magnitude of the quantization error at the sampling instant is between zero and ½ LSB

• the instances 𝑡𝑖 of the sampling process are determined by the sampling period 𝑇 if the original signal >> LSB, the quantization error is not correlated with the signal, and has a uniform distribution then, the quantization error can be treated as white noise its root mean square (rms) value is the standard deviation of this distribution

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accuracy

• detailed calculation of 𝜖rms

quantization noise 𝜖 𝑛 is treated as a random variable in interval

−𝑞

2, +

𝑞

2,

it has the probability density 𝑝𝜖 𝑥 = 1/𝑞 for 𝑥 ≤ 𝑞/2 and 𝑝𝜖 𝑥 = 0 for 𝑥 > 𝑞/2 (in our case: 𝑞 = 1)

thus, the probability that a given round-off error 𝜖 𝑛 lies in the interval 𝑥1, 𝑥2 is given by

variance of the random variable 𝜖 𝑛 , which is treated as a random

variable in interval −𝑞

2, +

𝑞

2

AS-Chap. 5 - 78

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dynamic range of ADCs

• for n-bit ADC the peak-to-peak amplitude is 𝐴𝑝𝑝 = 2𝑛 − 1

• for a sinusoidal input signal, then the rms value of its amplitude is given by

𝐴rms = 𝐴𝑝𝑝/2 2

• the dynamic range (DR) of an ADC is defined as 𝐴rms/𝜖rms using the approximation 2𝑛 − 1 ≃ 2𝑛 (valid for large 𝑛), we obtain for a 𝑛-bit ADC

(98.1 dB for a 16-bit ADC)

AS-Chap. 5 - 79

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Claude Elwood Shannon Harry Nyquist


sampling rate

• Shannon-Nyquist sampling theorem: The successful reproduction of a band-limited signal 𝑥 𝑡 is only possible if the sampling rate is higher than twice the highest frequency of the signal: 𝑓𝑠𝑎𝑚 ≥ 2𝑓𝑚𝑎𝑥

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sampling rate & sampling theorem

What happens if we increase the signal frequency 𝑓𝑆 above half of the sampling frequency 𝑓sam/2 (same sampling frequency 𝑓sam in all subfigures): for 𝑓𝑆 > 𝑓sam/2, we have a second possible signal (dashed lines), which has exactly the same sampling points

no unique result of the sampling process

𝒇𝑺 = 𝒇𝒔𝒂𝒎/𝟐

𝒇𝑺 > 𝒇𝒔𝒂𝒎/𝟐

𝒇𝑺 < 𝒇𝒔𝒂𝒎/𝟐

AS-Chap. 5 - 81

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• mathematical description of the sampling theorem:

the sampling of a signal 𝑆(𝑡) can be described by the multiplication of 𝑆(𝑡) with periodic array 𝐶 Δ𝑡 of Dirac 𝛿-functions (Dirac comb) yielding the sampled signal 𝑆sam

mathematically this corresponds to a convolution using the convolution theorem we obtain

𝑭𝑻 𝑺𝐬𝐚𝐦 𝝎 = 𝑭𝑻 𝑺 ⋅ 𝑭𝑻 𝑪 𝚫𝒕 𝝎

here, the Fourier transform 𝐹𝑇 𝑆sam (𝜔) = 𝐹𝑇 𝑆sam 𝜔 +2𝜋

Δ𝑡 is

periodic with angular frequency 𝜔sam = 2𝜋/Δt, where Δ𝑡 is the distance between two sampling instances

if 𝑓sam =1

Δ𝑡< 2𝑓S,max (𝑓S,max = maximum signal frequency), lower and

higher frequencies are superimposed in frequency space and can no longer be separated

AS-Chap. 5 - 82

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X(f) (top blue) and XA(f) (bottom blue) are continuous Fourier transforms of two different functions, S(t) and SA(t) (not shown). When the functions are sampled at rate fsam, the images (green) are added to the original transforms (blue) when one examines the discrete-time Fourier transforms (DTFT) of the sequences. In this example, the DTFTs are identical, which means the sampled sequences are identical, even though the original continuous pre-sampled functions are not. If these were audio signals, S(t) and SA(t) might not sound the same. But their samples (taken at rate fsam) are identical and would lead to identical reproduced sounds; thus SA(t) is an alias of S(t) at this sample rate. In this example (of a bandlimited function), such aliasing can be prevented by increasing fsam such that the green images in the top figure do not overlap the blue portion.

−𝑓sam

−𝑓sam

+𝑓sam

+𝑓sam

−𝐵 − 𝑓sam + 𝐵 +𝑓sam − 𝐵 + 𝐵

𝑋(𝑓)

𝑋𝐴(𝑓)

𝑓

𝑓

AS-Chap. 5 - 83

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0 1 2 3

-1

0

1

S

t


𝑡𝐴

sampling rate & aperture time

• sampling process takes a finite amount of time given by the so-called aperture time 𝑡a

• the sampling frequency 𝑓sam must smaller than 1/𝑡𝑎

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sampling rate & signal frequency/bit resolution

• the input signal is not allowed to changes by more than 1 LSB during 𝑡a (otherwise the error in the conversion process would exceed the resolution of the ADC)

upper limit of the ADC frequency bandwidth

• for a harmonic signal 𝑆 = sin 2𝜋𝑓𝑡 with frequency 𝑓 and amplitude 1, the

maximum slew rate is 𝑑𝑆

𝑑𝑡= 2𝜋𝑓 cos 2𝜋𝑓𝑡 = 2𝜋𝑓

time to slew by one LSB is 𝜏 = 2

(2𝑛−1) 2𝜋𝑓 (peak-to-peak amplitude is 2)

since 𝜏 ≥ 𝑡𝑎 to keep error smaller than ±LSB

𝒇 ≤𝟏

(𝟐𝒏−𝟏) 𝝅

𝟏

𝒕𝒂= 𝒇𝑩 (𝑓𝐵 is input bandwidth of ADC)

2𝑛𝑓𝐵 ≃ 1/𝑡𝑎 : the aperture time is limiting the performance of the ADC

(to increase the bit resolution, we have to reduce the bandwidth and vice versa)

• if a signal is sampled at 2𝑓𝐵, we say that it is sampled at the Nyquist rate 𝑓sam = 2𝑓𝑁 = 2𝑓𝐵

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Output size (bits)

Input frequency

1 Hz 44.1 kHz 192 kHz 1 MHz 10 MHz 100 MHz 1 GHz

8 1,243 µs 28.2 ns 6.48 ns 1.24 ns 124 ps 12.4 ps 1.24 ps

10 311 µs 7.05 ns 1.62 ns 311 ps 31.1 ps 3.11 ps 0.31 ps

12 77.7 µs 1.76 ns 405 ps 77.7 ps 7.77 ps 0.78 ps 0.08 ps

14 19.4 µs 441 ps 101 ps 19.4 ps 1.94 ps 0.19 ps 0.02 ps

16 4.86 µs 110 ps 25.3 ps 4.86 ps 0.49 ps 0.05 ps –

18 1.21 µs 27.5 ps 6.32 ps 1.21 ps 0.12 ps – –

20 304 ns 6.88 ps 1.58 ps 0.16 ps – – –

24 19.0 ns 0.43 ps 0.10 ps – – – –

32 74.1 ps – – – – – –


sampling rate & signal frequency/bit resolution

𝒕𝒂 =𝟏

(𝟐𝒏−𝟏) 𝝅

𝟏

𝒇𝑩

AS-Chap. 5 - 86

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aliasing

• if the input signal is changing much faster than the sampling rate, spurious signals called aliases will be produced at the output of the DAC

• the frequency of the aliased signal is the difference between the signal frequency and the sampling rate

• to avoid aliasing, the input to an ADC must be low-pass filtered to remove frequencies above half the sampling rate. This filter is called an anti-aliasing filter.

sampling instances

time / period of the signal

sign

al

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• advantages:

− significant reduction of the requirement for the anti-alias filter leading to a significant cost reduction

− reduction of quantization noise within the input bandwidth

reduction of a factor 𝑂𝑆𝑅 improvement of dynamic range by 10 log OSR (dB)

− use one-bit ADC and heavy oversampling (penalty: complexity of the digital part and processing speed)


oversampling

• the term oversampling is used, if the sampling rate is larger than the Nyquist rate 𝑓𝑁

• the oversampling rate is defined as: 𝐎𝐒𝐑 = 𝒇𝒔𝒂𝒎/𝟐𝒇𝑵

example: if an audio signal of 20 kHz bandwidth is sampled at a rate of 160 kHz (2𝑓𝑁 = 2𝑓𝐵 = 40 kHz) , i.e. an OSR of four

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out Sref

Sin JQ

Isens

L

Icirc

Sin Vout

JQ

L

Icirc

Sin Vout

JS

L Sin

Vout

JQ

RL

RB

semiconductor comparator superconducting one-junction SQUID comparator

Superconducting quasi-one-junction SQUID comparator (QOS)

superconducting voltage to frequency quantizer

5.4.2 The Comparator

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Igate

L/2

Icirc

Sin

OUT-

JQ2 JQ1

OUT+

L/2

Ism

0 Iin

- Igate

+ - + - + - + - +

5.4.2 The Comparator

incremental quantizer

threshold characteristic

if the analog signal increases or decreases, the threshold characteristic is crossed in the one or the other direction to a different flux state

flux quanta enter or leave the superconducting loop via the quantizer Josephson junctions 𝐽𝑄+ and 𝐽𝑄− resulting in SFQ voltage pulses at the

outputs OUT+ and OUT-, respectively

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5.4.3 Aperture Time

• minimum aperture time given by switching time of Josephson junctions 𝑡𝑎 ∼ 2 𝑝𝑠

• achievable performance of ADC: 𝒇𝑩 ≤𝟏

(𝟐𝒏−𝟏) 𝝅

𝟏

𝒕𝒂

bandwidth of more than 1 MHz for a 16 bit ADC

• fast switching speed of Josephson junctions cannot be fully used due to several technical hurdles: – junctions are embedded into complex circuits the actual switching

speed of the junction may be larger due to parasitic capacitances and inductances

– the SFQ pulses do not arrive exactly at the intended moment

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5.4.4 Different Types of ADCs

two main categories: 1. Nyquist-sampling ADCs (e.g. flash converters)

an ideal Nyquist ADC samples a bandwidth-limited signal at a sampling rate 𝑓sam = 2𝑓𝑁 and provides an accurate digital representation of that signal

composed of a large number of separate quantizers (single-bit comparators), each defining a single quantization level performance limited by the precision of the quantization levels

2. Oversampling ADCs (e.g. delta-sigma converters)

signal is sampled at a frequency 𝑓sam ≫ 2𝑓𝑁 using a single quantizer

feedback techniques and digital filtering have to be used to decrease the quantization noise and enhance the effective dynamic range

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offset

input Comparator clock

offset


offset


offset


offset


R

R

R

R

R

R

2R

2R

2R

2R

2R

S/2

S/4

S/8

S/16

S/32

offset

clock analog signal S

D0 (MSB)

D1

D2

D3

D4 (LSB)


Flash ADC

most significant bit

least significant bit

R/2R resistor ladder signal division

AS-Chap. 5 - 93

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time

anal

og

sign

al

VCO f = V/F0

ga

te

counter

gate

co

ntr

ol

analog input

digital output

VC

O

ou

tpu

t

gate

co

ntr

ol

pu

lse

s to

co

un

ter

time

time

time

pass

block

T t


Counting Coverters

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Delta-Sigma Converters

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the evolution of 𝑛𝑟 = − 𝑆𝑁𝑅 + 10 log10 𝐵𝑊 for semiconductor based delta-sigma modulators (DSM) and Nyquist ADCs over time

5.5 Prospects of Superconducting ADCs

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Performance of superconductor lowpass ADCs compared to semiconductor state-of-the-art ADCs (A. Gupta, in Microwave Symposium Digest (MTT), 2011 IEEE MTT-S International)

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15-bit ADC chip

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superconducting sigma-delta ADC

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A 1998 HYPRES superconductor transient digitizer: (a) Block diagram. (b) A superconductor chip with two transient digitizers based on a 6-bit flash ADC and a 32-bit-deep memory. (c) A fast pulse capture: 4 ns for 8 GS/s (top) and 2 ns for 16 GS/s (bottom).


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A 2007 HYPRES second-order band-pass sigma-delta ADC. (a) Schematics of ADC modulators with implicit and explicit feedback loops. (b) X-band ADC chip consisting of second-order band-pass ADC modulator centered for 7.4 GHz and digital signal processor.


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Chapter 5 Digital Electronics - Walther-Meißner-Institutdecoder A memory cell B decoder B memory cell A address memory I/O B address register I/OC carry out carry out data in function