CHAPTER5

IMPLIMENTATION

AND

SIMULATION RESULT

5.1 HOW TO SIMULATE AND IMPLIMENT RC6 ALCORITHM?

We have implemented cryptography in Xilinx 9.2i edition software.We have seen how to

make a program in Xilinx now we will see the results. And we will also come to know that how

to give inputs and how to check test bench and see output. RTL schematic shows a functional

digital circuit having inputs and outputs. Test bench waveform is used to check whethre our

digital circuit works perfectly or not.for that specific steps must be followed as described in this

section.

5.2 TESTING METHODOLOGY

our design should be tested by developing a testbench that ,

(1) Reads in plaintext, user-supplied keys, and expected ciphertext from a file.

(2) Uses the key scheduler to take the user-supplied keys and generate the round keys.

(3) Send the appropriate the control signals, plaintext, and round keys to the encryptor and

decryptor.

(4) Tests to ensure that the ciphertext is correctly generated and that the plaintext from the

decryptor matches the plaintext to the encryptor. If discrepancies occur between the

expected results and actual results, errors should be reported.

1) A diagram showing the logical hierarchy of your modules including module names and brief descriptions of what each module does.

2) Detailed block diagrams for the encryptor and decryptor, which show registers, functional units, multiplexers, control signals, etc.

3) State transition graphs or ASM charts for the finite state machines that control your encryptor and decryptor.

4) VHDL code for your encryptor, decryptor, key scheduler, and testbench. This code should be commented well.

5) Pre-synthesis simulation results for the modules from part 5. Include comments and annotated waveform for ease of interpretation of results. Also indicate whether or not results are correct and any known bugs.

5.3 ABOUT RTL SCHEMETIC

1) After checking syntex successfully, RTL schematic can be viewed from PROCESSES/

VIEW RTL SCHEMATIC .It shows digital circuit input and output diagram for RC6

ENCRYPTION algorithm.

2) RTL schematic of decryptor

After checking syntex successfully, RTL schematic can be viewed from PROCESSES/

VIEW RTL SCHEMATIC .It shows digital circuit input and output diagram for RC6

DECRYPTION algorithm.

STEP1:- for giving the inputs we change from synthesis and implementation to behavioral

simulation and add a new source by right clicking on project name

STEP 2:- then the screen appears as shown below . in that screen select a test bench waveform

and write the name we wan to give to test bench .

STEP 3:- then in clock input window select single clock and give clock high and low time as

10ns and all other parameters as shown below.

STEP 4:- In fig below we can see how to give inputs to encryptor .inputs are given after delay of

20ns staring from 50ns and giving 16 bit input after every 20ns. 16 bit round keys are also given

as shown and a start_e signal is made high so that program takes inputs.

STEP 5:-In fig below we can see the output test bench of encryptor the cipher text is available

after 1800ns. The cipher text is available after ready_e signal goes high.this cipher text is given

to decryptor

STEP 6:-Similarly output of encryptor is given to decryptor after same time delay as in encryptor

and start signal and round keys are also given

STEP 7:-When simulation is done we can see output of decryptor as shown below. The plain text

which was given in encryptor is obtained in decryptor output.

SYNTHESIS REPORT FOR ENCRYPTOR

States 12

| Transitions 14

Inputs 2

Outputs 11

Clock rising_edge

Reset positive

|Reset type asynchronous

Reset State 000001

Encoding automatic

Implementation automatic

MACRO STATISTICS

FSMs 1

Adders/Subtractors 135

16-bit adder 135

Counters 1

7-bit up counter 1

Registers 197

Flip-Flops 197

Latches 1

16-bit latch 1

Multiplexers 2

16-bit 16-to-1 multiplexer 2

Xors 16

16-bit xor2 2

16-bit xor3 14

FINAL RESULTS

RTL Top Level Output File Name encryptor.ngr

Top Level Output File Name encryptor

Output Format NGC

Optimization Goal Speed

Keep Hierarchy YES

Target Technology SPARTAN 3

Macro Preserve YES

YES YES

YES YES

wysiwyg NO

Design Statistics # IOs 52

Cell Usage:

AND1 9915

AND2 4468

AND3 89

AND4 19

AND5 3

GND 1

INV 1587

OR2 3635

OR3 78

OR5 1

VCC 1

XOR2 33

FlipFlops/Latches 200

FDC 68

FDCE 112

FTC 4

LD 16

IO Buffers 52

IBUF 35

OBUF 17

CPU:66.77 / 66.91 s |Elapsed : 67.00 / 67.00s Total memory usage is 265560 kilobytes

SYNTHESIS REPORT FOR DECRYPTOR

States 12

Transitions 14

Inputs 2

Outputs 12

Clock clock (rising_edge)

Reset reset (positive)

Reset type asynchronous

Reset State 000001

Encoding automatic

Implementation automatic

Macro Statistics

# Adders/Subtractors 135

16-bit adder 129

16-bit subtractor 6

# Counters 1

7-bit up 1

# Registers 12

1-bit register 1

16-bit register 11

# Comparators 1

# Logic shifters 2

16-bit shifter logical right 2

# Xors 78

1-bit xor2 62

16-bit xor2 2

16-bit xor3 14

FINAL RESULTS

RTL Top Level Output File Name decryptor.ngr

Top Level Output File Name decryptor

Output Format NGC

Optimization Goal Speed

Keep Hierarchy YES

Target Technology SPARTAN 3

Macro Preserve YES

XOR Preserve YES

Clock Enable YES

wysiwyg NO

Cell Usage :

# BELS 10352

# AND2 4470

# AND3 181

# AND5 2

# GND 1

# INV 1957

# OR2 3480

# OR3 228

# OR4 1

# XOR2 32

# FlipFlops/Latches 191

# FDC 84

# FDCE 103

# FTC 4

# IO Buffers 52

# IBUF 35

# OBUF 17

CPU : 66.24 / 67.56 s Elapsed : 66.00 / 67.00 s

Total memory usage is 261464 kilobytes