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Chapter 4 Stochastic Modeling and Stochastic Timing. UCLA EE201C Professor Lei He. Outline. Process Variation Trends Modeling Statistic Static Timing Analysis (SSTA) Monte Carlo simulation Path-based and block-based SSTA. As Good as Models Tell …. - PowerPoint PPT Presentation
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Chapter 4Stochastic Modeling and Stochastic Timing
UCLA EE201C Professor Lei He
Outline
Process Variation Trends Modeling
Statistic Static Timing Analysis (SSTA) Monte Carlo simulation Path-based and block-based SSTA
As Good as Models Tell… STA (static timing analysis) assumed:
Delays are deterministic values Everything works at the extreme case (corner
case) Useful timing information is obtained
However, anything is as good as models tell Is delay really deterministic? Do all gates work at their extreme case at the
same time? Is the predicated info correlated to the
measurement? …
Factors Affecting Device Delay Manufacturing factors
Channel length (gate length) Channel width Thickness of dioxide (tox) Threshold (Vth) …
Operation factors Power supply fluctuation Temperature Coupling …
Material physics: device fatigue Electron migration hot electron effects …
Lithography Manufacturing Process
As technology scales, all kinds of sources of variations Critical dimension (CD) control for minimum feature size Doping density Masking
Process Variation Trend
Keep increasing as technology scales down [Nassif 01] Absolute process variations do not scale well Relative process variations keep increasing
0.00%
15.00%
30.00%
45.00%
1997 1999 2002 2005 2006
Leff Tox Vth
Variation Impact on Delay [Visweswariah 04]
Extreme case: guard band [-40%, 55%] In reality, even higher as more sources of
variation Can be both pessimistic and optimistic
Sources of Variation Impact on DelayInterconnect wiring(width/thickness/Inter layer dielectric thickness)
-10% ~ +25%
Environmental 15 %
Device fatigue 10%
Device characteristics(Vt, Tox)
5%
Variation-aware Delay Modeling Delay can be modeled as a random
variable (R.V.) R.V. follows certain probability
distribution
Some typical distributions Normal distribution Uniform distribution
Review of Probability R.V. X can take value from its domain
randomly Domain can be continuous/discrete, finite/infinite
PDF vs. CDF
x
dxxfxXPxF
dxxfdxxXxP
)()()(: (c.d.f.)Function on Distributi Cumulative
)()(: (p.d.f.)Function Density y Probabilit
x
dx
f (x)
1
0x
F (x)
Review of Probability Mean and Variance
Normal Distribution
dxxfxxE
dxxfxxE
xxx
x
)()(}){(
)(}{
222
]2
)([
2
1)( :PDF
2
2
x
x
x
xExpxf
μx
σx
x
f (x)
Multivariate Distribution Similar definition can be extended for
multivariate cases Joint PDF (JPDF), Covariance Becomes much more complicated Correlation MATTERS!!
)()(),(:tIndependen
0or 0),cov( :edUncorrelat
: Coeffcientn Correlatio
}{}{}{),cov(: Covariance
),(),()},({ :Mean
),(),( :JPDF
yfxfyxf
yx
yExExyEyx
dxdyyxfyxyxE
dxdyyxfdyyYydxxXxP
YX
xy
yx
xyxy
xy
Types of Process Variation Inter-die vs. intra-die
variations Die to die / wafer to
wafer / lot to lot Within a single die
Random vs. systematic CMP and OPC related Doping density, lens
aberration Many more “confusing”
terms … OCV/ACLV CMP Partly due to the fact that
this area is fairly new and ever changing
-4 -3 -2 -1 0 1 2 3 4
Global Sigma
No
of
Ch
ips
-4 -3 -2 -1 0 1 2 3 4
With-in Chip Sigma
0
0.2
0.4
0.6
0.8
1
1.2
No
of
Tran
sist
ors
Variation-aware Delay Modeling How to characterize delay variations?
SPICE simulation Measurement
Example for a 2-stage buffer Assume only channel length is R.V. for 65nm
technology Uniform distribution with domain ~ 10% of its
nominal value Random sample channel length from 0.9~1.1,
and measure the delays through SPICE Plot delay PDF
Variation-aware Timing Analysis
How this would affect our STA? Min-Max approach would be too risky Corner-based STA is too expensive
2^n corners
To be accurate, analyze timing statistically
But how? Every label (delays) in the DAG is modeled
as a R.V. with certain distribution Should use multivariate R.V. analysis
Correlation is KEY!
Correlation Types Correlation interpretation:
Gates, wires, and paths become slower or faster simultaneously
Due to the common sources of underlying variations
Global variation Inter-chip variations
Structural correlation Path re-convergence
Spatial correlation Devices close-by have higher correlation
than that far-apart
Statistical Static Timing Analysis: SSTA
Fairly new (hot) topic Many debates Many new ideas Not quite consistency across different ref. Unfortunately/Fortunately, live with it…
In this lecture, cover some typical ones Monte Carlo simulation (Golden case) One path-based approach One block-based approach More for your own entertainment
Monte Carlo Simulation
Definition: A technique involving the use of random
numbers solving physical or mathematical problems
Characteristics Physical process is simulated without
explicitly knowing equations that describe the system output
Only requirement is that the physical system be described by PDF
Monte Carlo for SSTA Randomly sample each R.V. in accordance
with its respective PDF Instantiate a specific DAG Solving STA using the technique we
discussed before This is called one Monte Carlo run Run it many times until certain data
statistics converge Stopping condition can be fairly sophisticated
Finally, extract statistics from Monte Carlo runs PDF of RAT/AT/Slack Yield curve …
Monte Carlo Simulation Pros
Conceptually easy Implementation not that difficult Make use of previous STA algorithm Accurate, used as golden case (benchmarking)
Cons Computationally expensive No many diagnostic information if something is
wrong No incremental computation possible
Efficient solution Analytical Statistical static timing analysis (SSTA)
SSTA Algorithms Objective
Find probability distribution of circuit delay Path Based SSTA
Statistically calculate path delay distributions Find statistical maximum of these path delays Identify potential critical paths
Block Based SSTA Traverse DAG to calculate the delay distribution
for each node Widely used due to the incremental computation
capability
Path-based SSTA [Orshansky DAC-02] Key operations
Summation Path delay = sum(node delay)
Maximum Critical path delay = max(path delay)
Delay model First order approximation Obtained from SPICE simulation
}max{ ,
,,
,
kpc
jgkp
iinomjg
DD
DD
GDD
Path-based SSTA: Key Operations
Gate delay variance and covariance Path delay variance and covariance
Path-based SSTA: Approximation Maximum operation is approximated
Closed form is not known yet Lower and upper bound for path delay me
an Let D={D1...Dn } be an arbitrary path delay dis
tribution with correlation Let X={X1...Xn } identical to D but WITHOUT co
rrelation Can prove an upper bound for mean(D):
Mean(D) < Mean(X) Similarly an lower bound can be established
Path-based SSTA: Approximation
Lower and upper bound for path delay variance
Result from theory of Gaussian process: Borell Inequality Variance of max{D1…Dn} around its mean is s
maller than variance of a single Di with largest variance
Path-based SSTA: Experiment Results
Timing approximation is tighter Variation is smaller Mean clock frequency is smaller
Block-based SSTA: [Devgan ICCAD03] AT and gate delays are modeled as R.V.
AT as CDFs Gate Delays as PDFs For easy computation
Delay distributions can take any form Model CDFs as Piece-Wise Linear functions Model PDFs as constant step functions
CumulativeProbability
1.0
A
1.0
A1 A2 A3
P1
P2
P3
Block-based SSTA: Key Operations
AdditionAT2 = AT1+D1
1 2D1
AT1 AT2AT2 = AT1 D1
( : convolution, Assuming independence for now)
CDF PDF
Block-based SSTA: Key Operations
Closed form for addition
=t1+t2
0.5s1u1(t1+t2-t)2
t2
u1
t1
s1
Block-based SSTA: Key Operations Maximum C = max (A, B)
CDF of C = CDF of A x CDF of B Assume independence for now Closed form computation via PWL
=
t3=max(t1,t2)
s1s2(t-t1)(t-t2)
x
t2
s2
t1
s1
Block-based SSTA: Correlation
Correlation due to path reconvergence AT5 and AT6 are correlated due to shared AT4
Exact handling this correlation would cause exponential complexity
Utilize the structure of the circuits
PI
PI
PO
AT1AT2D1
D2
D3D4
D6
D7
AT4
AT3
AT5
AT6
D8D9
Block-based SSTA: Correlation
This formula works well for this simple case
How does this work for general cases?
A2 and A3 are related
A4 = max(A2+D24, A3+D34)
1
3
24
A2 = A1 + D12 and A3 = A1 + D13
A4=max(A1+D12+D24, A1+ D13+D34) =A1+max(D12+D24, D13+D34)
Block-based SSTA: General Cases
General situation An input of a gate can depend on many
preceding timing points There may be shared paths in the input
cone
A
B
C
D1234
z
G1
G2
G3
G4
Block-based SSTA: Heuristic Algorithm
Create a dependency list Keep track of the reconvergence fanout node
s a particular node depends on Basically a list of pointers
Compute the dominant common node For each pair wise max
Determine that by statistical dominance and logic level
Take out the common part contributed by the dominant node
Perform max of the two CDFs An example follows
Block-based SSTA: Example
D12
34
z
G4A B
A B C
A C
C
Dependency list for G4:
Create the dependency list
A
B
C
D1234
z
G1
G2
G3
G4
Block-based SSTA: Example
D12
34
z
G4B
B
C
C
D12
34
z
G4A B
A B C
A C
C
Dependency list for G4:
Dominant common node
Block-based SSTA: Example
D12
34
z
G4B
BC
C
Compute the pair wise max
ATD = max(A1+D1z, A2+ D2z, A3+D3z, A4 + D4z)
ATx = AB + max(A1-AB +D1z, A2-AB+ D2z)
ATy = Ac + max(A3-Ac +D3z, A4-Ac+ D4z)
ATD = max (ATx, ATy)
Block-based SSTA: Experiments Runtime comparison
SSTA w/ correlation and w/o correlation
Circuit
w/ correlation
w/o correlation
C432 1.5 1.0
C499 1.26 1.0
C880 1.22 1.0
C1908 1.33 1.0
C2670 1.23 1.0
C3540 1.26 1.0
C6288 1.20 1.0
C7552 1.30 1.0
Block-based SSTA: Experiments Timing distribution
SSTA w/ correlation and w/o correlation and Monte Carlo Simulation
30 0 0 3 1 0 0 3 20 0 33 0 0 3 4 00 3 50 0 3 6 0 0 3 70 0 38 0 00
0 .2
0 .4
0 .6
0 .8
1
m on t e c a rlo
no d e pde p
Conclusion & Summary
Summary Timing analysis is a key part of the design
process Static timing analysis (STA)
Sign off tools for tape out Statistical static timing analysis (SSTA)
Arises due to process variation when technology continues to scale
More to be done for SSTA Correlations matter Interconnect variability Slew propagation Gate delay models How to guide for optimal design?