Chapter 4: Designing Combinational Systemsfaculty.montgomerycollege.edu/auchechu/EE 244/EE244_Chpt4.pdf · ES 244: Digital Logic Design Chapter 4 Chapter 4: Designing Combinational

ES 244: Digital Logic Design Chapter 4

Chapter 4: Designing Combinational Systems

Uchechukwu Ofoegbu

Temple University


Gate Delay

((0.1)((0.1)’’.0).0)’’

= 1= 1((0.1)((0.1)’’.1).1)’’

= 0= 0((1.1)((1.1)’’.1).1)’’

= 1= 1((1.0)((1.0)’’.0).0)’’

= 1= 1((1.1)((1.1)’’.1).1)’’

= 1= 1


OneOne--bit Carry Ripple Adderbit Carry Ripple Adder–

s = sum

–

cout –

carry-out–

a, b = added bits–

C = carry in

a b c cout s0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

–

S = a’b’c+a’bc’+ab’c’+abc–

cout = a’bc+ab’c+abc’+abc–

= bc+ac+ab–

S = c(a’b’+ab)+c’(ab’+a’b)–

cout = c’(a+b)+ab–

S = c(aΦb)’+c’(aΦb) = c Φ(aΦb)–

Xor

can be replaced with 4 two input NAND gates

–

cout = c(aΦb)+ab

5 three5 three--input NAND, 3 twoinput NAND, 3 two--input NAND, 1 fourinput NAND, 1 four--

input NAND, and three not gates if input NAND, and three not gates if complemented inputs are not availablecomplemented inputs are not available

11 two11 two--input NAND, three not gatesinput NAND, three not gates2 two2 two--input XOR, 3 twoinput XOR, 3 two--input input NANDsNANDs, 1 three, 1 three--

input ORinput OR


OneOne--bit Full Binary Adderbit Full Binary Adder

Gate implementation for the One-bit Full Adder

n-bit “ripple-carry” binary adder

Worst case propagation delay – 2n time units; Gate delay=1


Copyright © 2008 The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

Gate Delay through a 1-bit Adder


Gate Delay through an n-bit Adder

1.1.

Delay from inputs to Delay from inputs to ccoutout

++

2.2.

(n(n--2)*delay from 2)*delay from ccinin

to to ccoutout

++

3.3.

Max(delayMax(delay

from from ccinin

to to ccoutout

or or ccinin

to s)to s)

For the multilevel adder:For the multilevel adder:

55∆∆

+ 2(n+ 2(n--2) 2) ∆∆

+ 3 + 3 ∆∆

= (2n+4) = (2n+4) ∆∆

What is the delay for a 64 What is the delay for a 64 bit adder?bit adder?

Total delay does Total delay does not have to be so not have to be so

long!!long!!


•

SOP minimization for two-bit adders•

Complex equations•

Fan-in limitations•

With a maximum fan-in of 7, adding n-bit would have a total delay of (n+1)∆

•

Four-bit adders•

7483, 7483A, 74283 –

differ only in pin connections•

Produces the sum with four-level inputs•

Uses combination of NAND, NOR, AND, NOT and XOR gates

•

Delay from ccinin

to to ccoutout

= 3= 3∆•

Total delay = of (3/4 n+1)∆•

4-bit adders are cascaded for larger adders

Gate Delay ImprovementsGate Delay Improvements


OneOne--bit Full Binary Adderbit Full Binary Adder

Gate implementation for the One-bit Full Adder

n-bit “ripple-carry” binary adder

Worst case propagation delay – 2n time units; Gate delay=1

aa

bb

ccss

CCoutout





•

Carry-Look-Ahead Adder•

Carry generate signal (g) is 1 if that stage of the adder has a carryout of 1 whether or not there was a carry-in

•

Carry propagate signal (p) is 1 if that stage of the adder has a

carryout of 1 if he carry-in is 1

•

Both g and p can be generated for all n bits in 1 gate delay.•

The carry out is 1 if the last bit generated a carry, or if it propagated a carry and the stage below it generated one.

•

All the carries can be generated in 2 additional delays after g and p are available,

independent of n.•

All sums can be generated in 4∆, independent of n.


http://upload.wikimedia.org/wikipedia/commons/1/16/16-bit_lookahead_carry_unit.svg


OneOne--bit Full Binary bit Full Binary SubtractorSubtractor/Adder/Adder

•

Subtract y from x , with a borrow-in from the previous bit position, bin–

d: difference–

bout : borrow-out

x y bin bout d0 0 0 0 00 0 1 1 10 1 0 1 10 1 1 1 01 0 0 0 11 0 1 0 01 1 0 0 01 1 1 1 1

inout ybbxyxb ++=

)( yxbd in ⊕⊕=


Organization of a 1-bit comparator

•

Compares two numbers to determine if –

A is less than B

–

A is equal to B–

A if greater than B

•

Can be extended to any bit size


Truth Table for Simple 1Truth Table for Simple 1--bit Comparatorbit ComparatorA2 B2 A1 B1 Y: A=B0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 0

1 1 1 1

1.1.

In groups, In groups, come up with a minimum SOP come up with a minimum SOP expression for this simple expression for this simple comparator. comparator. Assume all inputs are available in Assume all inputs are available in both complimented and both complimented and uncomplementeduncomplemented

versions, design versions, design a logic circuit for your algebraic a logic circuit for your algebraic expressionexpression

What is the minimum delay for What is the minimum delay for your designyour design


Group WorkGroup Work

•

1•

3

•

5

•

Homework: 2, 4, 7,


•

Selects one of several outputs when activated•

n-bit binary number results in 2n

output lines

Binary DecodersBinary Decoders



Selected output is highSelected output is high



Selected output is lowSelected output is low



Selected output is high only when Enable Selected output is high only when Enable bit is high or Enable Prime is lowbit is high or Enable Prime is low


Active Low and three enable bitsActive Low and three enable bits

Active when ALL THREE enable bits are Active when ALL THREE enable bits are activeactive






•

Exact Opposite of a binary decoder•

Used to select a device from several possible devices

•

If only one of the inputs can be 1, then the truth table for a 4-2 encoder is:

Binary EncodersBinary Encoders

AA00 AA11 AA22 AA33 zz00 zz111 0 0 0 0 00 1 0 0 0 10 0 1 0 1 00 0 0 1 1 1

ZZ0 0 ==AA22

+A+A33

ZZ1 1 ==AA11

+A+A33

What is the difference What is the difference between Device between Device AA0 0

and when there is no and when there is no device signaling?device signaling?


0 1 2 3 4 5 6 7

0 4 5 6 7

1 6 7 2 3 4 5

2 7 5 6 3 4 6 1 2 4 6

( )

NR A A A A A A A AZ A A A AZ A A A A A AZ A A A A A A A A A A

′ ′ ′ ′ ′ ′ ′ ′== + + +

′ ′= + + +′ ′ ′ ′ ′ ′= + + +

Priority EncodersPriority Encoders


MultiplexersMultiplexers

•

A switch that is used to pass one input as a function of select inputs


MultiplexersMultiplexers



•

10 –

assume you have 4-input NAND also available

•

13*


Programmable Logic DevicesProgrammable Logic Devices

•

Also known as gate arrays

•

Involves gate diagrams combinational circuits with lines for all possible connection


Programmable Logic Devices Programmable Logic Devices -- IllustrationIllustration

•

Base array is manufactured first

•

Each connection is added when needed based on user specifications



•

A fuse in connected in the midst of each connection line

•

If the connection is not wanted, the fuse is blown

Field Programmable Gate Arrays (Field Programmable Gate Arrays (FPGAsFPGAs))



(a) Unprogrammed and-gate.(b) Unprogrammed or-gate. (c) Programmed and-gate

realizing the term ac.(d) Programmed or-gate realizing

the term a + b. (e) Special notation for an and-

gate having all its input fuses intact.

(f) Special notation for an or-gate having all its input fuses intact.

(g) And-gate with nonfusible inputs.

(h) Or-gate with nonfusible inputs.

Field Programmable Gate Arrays (Field Programmable Gate Arrays (FPGAsFPGAs))


W(A, B, C, D) = Σm(3, 7, 8, 9, 11, 15)X(A, B, C, D) = Σm(3, 4, 5, 7, 10, 14, 15)Y(A, B, C, D) = Σm(1, 5, 7, 11, 15)

Programmable ROMsProgrammable ROMs

•

You only need a list of minterms

•

One AND gate for each minterm

•

Appropriate minterm

gates are connected to each output


W = AB′C′

+ A′CD + ACDX = A′BC′

+ ACD′

+ A′CD + BCDY = A′C′D′

+ ACD + BCD7 terms

•

You only need SOP expressions

•

Main concern is the number of AND gates available

•

You may use just a sum of minterms, or minimize each function or maximize charing

Programmable Logic Arrays Programmable Logic Arrays -- PLAsPLAs

W = AB′C′

+ CDX = A′BC′

+ ACD′

+ A′CD + (BCD or ABC)Y = A′C′D′

+ ACD + (BCD or A’BD)8 or 9 terms depending on if we choose BCD


W = AB′C′

+ CDY = A′BC′

+ A′CD + ACD′

+ {BCD or

ABC}Z = A′C′D′

+ ACD + {A′BD or

BCD}

•

Each output comes from an OR gate that has its own group of AND gates

Programmable Array Logic Programmable Array Logic -- PALPAL



•

14d ROM



•

14d

F = F = A' B' C' DA' B' C' D

+ A' C D' + A' B C + + A' C D' + A' B C + A C' D'A C' D'

+ + A C' DA C' DG = G = A' B' C' DA' B' C' D

+ A B' + + A B' + A C' DA C' D

+ + A C DA C D

H = H = A' B' C' DA' B' C' D

+ B C + + B C + A C' D'A C' D'

+ + A C DA C D

PLA



•

14d PLA



PAL

Documents

Chapter 4: Designing Combinational Systemsfaculty.montgomerycollege.edu/auchechu/EE 244/EE244_Chpt4.pdf · ES 244: Digital Logic Design Chapter 4 Chapter 4: Designing Combinational