Chapter 3

Boolean Algebra and Digital Logic

Linda Null, Julia Lobur

Figure 03.UN01: "I've always loved that word, Boolean."

Claude Shannon

Table 03.T01: Truth Table for AND

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Table 03.T02: Truth Table for OR

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Table 03.T03: Truth Table for NOT

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Table 03.T04: The Truth Table for F(x,y,z) = x + y z′

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Table 03.T05: Basic Identities of Boolean Algebra

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Table 03.T06: Truth Table for the AND Form of DeMorgan's Law

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Table 03.T07: Truth Table Representation for a Function and Its Complement

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Table 03.T08: Truth Table Representation for the Majority Function

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Figure 03.F01: The Three Basic Gates

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Figure 03.F02: a) The Truth Table for XOR b) The Logic Symbol for XOR

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Figure 03.F03: Truth Table and Logic Symbols for NAND

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Figure 03.F04: Truth Table and Logic Symbols for NOR

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Figure 03.F05: Three Circuits Constructed Using Only NAND Gates

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Figure 03.F06: A Three-Input OR Gate Representing x + y + z

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Figure 03.F07: A Three-Input AND Gate Representing x yz

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Figure 03.F08: AND Gate with Two Inputs and Two Outputs

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Figure 03.F09: Logic Diagram for F(x, y, z) = x + y'z

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Figure 03.UN02: Line drawing showing a circuit.

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Figure 03.F10: Simple SSI Integrated Circuit

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Figure 03.UN08: Line drawing showing a function that evaluates to one AND gate using x and y as input.

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Table 03.T09: Truth Table for a Half-Adder

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Figure 03.F11: Logic Diagram for a Half-Adder

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Figure 03.F12: a) Truth Table for a Full-Adder b) Logic Diagram for a Full-Adder

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Figure 03.F13: Logic Diagram for a Ripple-Carry Adder

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Figure 03.F14: a) A Look Inside a Decoder b) A Decoder Symbol

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Figure 03.F15: a) A Look Inside a Multiplexer b) A Multiplexer Symbol

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Table 03.T10: Parity Generator

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Table 03.T11: Parity Checker

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Figure 03.F16: 4-Bit Shifter

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Figure 03.F17: A Simple Two-Bit ALU

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Figure 03.F18: A Clock Signal Indicating Discrete Instances of Time

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Figure 03.F19: Example of Simple Feedback

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Figure 03.F20: SR Flip-Flop Logic Diagram

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Figure 03.F21: a) SR Flip-Flop b) Clocked SR Flip-Flop c) Characteristic Table for the SR Flip-Flop d) Timing Diagram for the SR Flip-Flop (assuming initial state of Q is 0)

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Table 03.T12: Truth Table for SR Flip-Flop

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Figure 03.F22: a) JK Flip-Flop b) JK Characteristic Table c) JK Flip-Flop as a Modified SR Flip-Flop d) Timing Diagram for JK Flip-Flop (assuming initial state of Q is 0)

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Figure 03.F23: a) D Flip-Flop b) D Flip-Flop Characteristic Table c) D Flip-Flop as a Modified SR Flip-Flop d) Timing Diagram for D Flip-Flop

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Figure 03.F24: JK Flip-Flop Represented as a Moore Machine

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Figure 03.F25: Simplified Moore Machine for the JK Flip-Flop

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Figure 03.F26: JK Flip-Flop Represented as a Mealy Machine

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Figure 03.F27: a) Block Diagram for Moore Machines b) Block Diagram for Mealy Machines

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Figure 03.F28: Components of an Algorithmic State Machine

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Figure 03.F29: Algorithmic State Machine for a Microwave Oven

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Figure 03.UN02: Finite State Machine for Accepting a Variable Name

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Figure 03.F30: a) 4-Bit Register b) Block Diagram for a 4-Bit Register

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Figure 03.F31: 4-Bit Synchronous Counter Using JK Flip-Flops

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Figure 03.F32: 4 x 3 Memory

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Figure 03.F33: Convolutional Encoder for PRML

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Figure 03.F34: Stepping Through Four Clock Cycles of a Convolutional Encoder.

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Table 03.T13: Characteristic Table for the Convolutional Encoder in Figure 3.33

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Figure 03.F35: Mealy Machine for the Convolutional Encoder in Figure 3.33

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Figure 03.F36: Mealy Machine for a Convolutional Decoder

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Figure 03.F37: Trellis Diagram Illustrating State Transitions for the Sequence 00 10 11 11

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Figure 03.F38: Trellis Diagram Illustrating Hamming Errors for the Sequence 10 10 11 11

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Figure 03.AP01: Minterms for Two Variables

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Figure 03.AP02: Minterms for Three Variables

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Figure 03.AP03: Kmap for F(x,y) = x + y

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Figure 03.AP04: Groups Contain Only 1s

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Figure 03.AP05: Groups Cannot Be Diagonal

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Figure 03.AP06: Groups Must Be Powers of 2

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Figure 03.AP07: Groups Must Be as Large as Possible

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Figure 03.AP08: Minterms and Kmap Format for Three Variables

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Figure 03.AP09: Minterms and Kmap Format for Four Variables

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Figure 03.UN10: Illustration of a Kmap with 3 circled groups.

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