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Logic and Computer Design Fundamentals
Chapter 3 – CombinationalLogic DesignLogic Design
Part 2 – Combinational Logic
Hoang Trang
Reference: © 2008 Pearson Education IncReference: © 2008 Pearson Education, Inc.
Overview
Part 2 – Combinational Logic• Decoding using Decoders
=> Implementing Combinational Functions with Decoders
• Encoding using Encoders• Selecting using Multiplexers Implementing Combinational FunctionsImplementing Combinational Functions
with Multiplexers
Hoang Trang Reference Chapter 3 2
Enabling Function
Enabling permits an input signal to passEnabling permits an input signal to pass through to an output
XFEN
En= 0, F=0EN
(a)
X
En=1, F=X
En= 0 F=1
Hoang Trang Reference Chapter 3 3
ENX
F
(b)
En= 0, F=1
En=1, F=X
Decoding
Decoding:+ convert an n-bit input code to an m-bit output code (n m 2n)
+ each valid code word (input) produces a unique output codeq p Circuits that perform decoding are called
decodersdecoders
Hoang Trang Reference Chapter 3 4
Decoder Examples 1-to-2 Decoder A D0 D1
D0 A
2-to-4 Decoder
0 1 0
1 0 1
(a) (b)
D1 AA
A1
0
A0
0
D0
1
D1
0
D2
0
D3
0A1
A0(a) (b)
0
0
1
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
D0 A1 A0
D1 A1 A0
Note: the 2-4-linemade up of 2 1-to-2-line
(a)
D2 A1 A0
Hoang Trang Reference Chapter 3 5
pdecoders and 4 AND gates
(b)
D3 A1 A0
Decoder Expansion
General procedure given in book for any decoder with n inputs and 2n outputsn inputs and 2 outputs.
This procedure builds a decoder backward from the outputs.
The output AND gates are driven by two decoders with their numbers of inputs either equal or differing by 1.
Th d d th d i d i th These decoders are then designed using the same procedure until 2-to-1-line decoders are reached.
The procedure can be modified to apply to decoders p pp ywith the number of outputs ≠ 2n
Hoang Trang Reference Chapter 3 6
Decoder Expansion - Example 1
3-to-8 decoder (ex: IC 74138)• Number of output ANDs = 8• Number of inputs to decoders driving output
ANDs = 3• Closest possible split to equal 2-to-4 decoder 1-to-2 decoder
(next slide for result)
Hoang Trang Reference Chapter 3 7
Decoder Expansion - Example 1
Result 4 2-input ANDs 8 2-input ANDs
D A2’ A1’ A0’D0A 0
A
D1
A2’.A1’.A0’
A2’.A1’.A0
2-to-4-Linedecoder
A 1 D2
D3
A2’.A1.A0’
A2’.A1.A0Decoder: “minterm generator”
A 2
D4
D5
A2.A1’.A0’
A2.A1’.A0
1-to-2-Line decoders D6
D7
A2.A1.A0’=> Implement any function!!!
Hoang Trang Reference Chapter 3 83-to-8 Line decoder
A2.A1.A0minterm
Decoder Expansion - Example 2 4-to-16 decoder
• Number of output ANDs = 16• Number of output ANDs = 16• Number of inputs to decoders driving output ANDs
= 4• Closest possible split to equal
2 2-to-4 decoders
Hoang Trang Reference Chapter 3 9
Decoder Expansion - Example 3 7-to-128 decoder
• Number of output ANDs = 128• Number of output ANDs = 128• Number of inputs to decoders driving output ANDs
= 7• Closest possible split to equal
4-to-16 decoder 3 to 8 decoder 3-to-8 decoder
Complete using known 3-8 and 2-to-4 line decoders
Hoang Trang Reference Chapter 3 10
Decoder with Enable In general, attach m-enabling circuits to the outputs See truth table below for functionSee truth table below for function
• Note use of X’s to denote both 0 and 1• Combination containing two X’s represent four binary combinations
Alternatively, can be viewed as distributing value of signal EN to 1 of 4 outputs
In this case called a
EN
A 1
In this case, called ademultiplexer A 0
D0
DEN A1 A0 D0 D1 D2 D3 D1
D2
EN A1 A0 D0 D1 D2 D3
011
X00
X01
010
001
000
000
Hoang Trang Reference Chapter 3 11
D3
(b)
11
11
01
00
00
10
01
(a)
Combinational Logic Implementation- Decoder and OR Gates
Implement m functions of n variables with:S f i i (SOP)• Sum-of-minterms expressions (SOP)
• One n-to-2n-line decoder• m OR gates one for each output• m OR gates, one for each output
Approach 1:• Find the truth table for the functions• Find the truth table for the functions• Make a connection to the corresponding OR from
the corresponding decoder output wherever a 1 appears in the truth table
Approach 2
Hoang Trang Reference Chapter 3 12
• Find the minterms for each output function• OR the minterms together
Decoder and OR Gates Example
0A P101234
ABCD
1
P Finding sum of
i t i
45678
D P2
minterms expressionsP1 = m(1,2,5,6,8,11,12,15)P (1 3 4 6 8 10 13 15)
89101112
P4
P2 = m(1,3,4,6,8,10,13,15)P4 = m(2,3,4,5,8,9,14,15) Find circuit
12131415
Hoang Trang Reference Chapter 3 13
Find circuit Is this a good idea?
Decoder and OR Gates Example: BCD to excess-3 conversionBCD to excess 3 conversion
Hoang Trang Reference Chapter 3 14
Implement? By using decoder????
Decoder and OR Gates Example: BCD to excess-3 conversionBCD to excess 3 conversion
Hoang Trang Reference Chapter 3 15
Encoding Encoding - the opposite of decoding - the conversion
of an m-bit input code to an n-bit output code with nof an m-bit input code to an n-bit output code with nm 2n such that each valid code word produces a unique output codeq p Circuits that perform encoding are called encoders An encoder has 2n (or fewer) input lines and n outputAn encoder has 2 (or fewer) input lines and n output
lines which generate the binary code corresponding to the input values
Hoang Trang Reference Chapter 3 16
Encoder Example
A decimal-to-BCD encoder• Inputs: 10 bits corresponding to decimal
digits 0 through 9, (D0, …, D9)• Outputs: 4 bits with BCD codes• Function: If input bit Di is a 1, then the
(A A A A ) i C f ioutput (A3, A2, A1, A0) is the BCD code for i,D9=1 => output: A3A2A1A0=1001D7=1 => output: A3A2A1A0=0111What happens? D9=1 and D7=1????
Hoang Trang Reference Chapter 3 17
What happens? D9 1 and D7 1????
Priority Encoder
If more than one input value is 1, then the d j t d i d d t kencoder just designed does not work.
One encoder that can accept all possiblecombinations of input values and produce a meaningful result is a priority encoder. Among the 1s that appear, it selects the
most significant input position (or the least significant input position) containing a 1 and responds with the corresponding
Hoang Trang Reference Chapter 3 18
binary code for that position.
Priority Encoder Example Priority encoder with 5 inputs (D4, D3, D2, D1, D0) - highest priority to
most significant 1 present - Code outputs A2, A1, A0 and V where V indicates at least one 1 presentindicates at least one 1 present.No. of Min-terms/Row
Inputs Outputs
D4 D3 D2 D1 D0 A2 A1 A0 V1 0 0 0 0 0 X X X 01 0 0 0 0 1 0 0 0 12 0 0 0 1 X 0 0 1 12 0 0 0 1 X 0 0 1 14 0 0 1 X X 0 1 0 18 0 1 X X X 0 1 1 1
Xs in input part of table represent 0 or 1; thus table entries correspond to product terms instead of minterms. The column on the left shows that all
16 1 X X X X 1 0 0 1
Hoang Trang Reference Chapter 3 19
p32 minterms are present in the product terms in the table
Priority Encoder Example (continued)
Could use a K-map to get equations, but can be read directly from table and manually optimized if careful:A2 = D4
A1 = D3 + D2 = F1, F1 = (D3 + D2)D4 D3D4 D4
A0 = D3 + D1 = (D3 + D1)V = D4 + F1 + D1 + D0
D4 D3D4 D2 D4 D2
Hoang Trang Reference Chapter 3 20
Selecting
Selecting of data or information is a critical function in digital systems andcritical function in digital systems and computers Circuits that perform selecting have: Circuits that perform selecting have:
• A set of information inputs from which the selection is madeselection is made
• A single output• A set of control lines for making the selectionA set of control lines for making the selection
Logic circuits that perform selecting are called multiplexers
Hoang Trang Reference Chapter 3 21
called multiplexers
Multiplexers
A multiplexer selects information from an input line and directs the information toinput line and directs the information to an output lineA i i i A typical multiplexer has n control inputs (Sn 1, … S0) called selection inputs, 2n
i f i i ( )information inputs (I2n 1, … I0), and one
output Y A multiplexer can be designed to have m
information inputs with m 2n as well as
Hoang Trang Reference Chapter 3 22
n selection inputs
2-to-1 Multiplexer
Since 2 = 21, n = 1 The single selection variable S has two values:
• S = 0 selects input I0
S 1 l t i t I• S = 1 selects input I1
The equation:Y I + SISY = I0 + SI1
The circuit:S
DecoderEnablingCircuits
S
I0Y
Hoang Trang Reference Chapter 3 23
SI1
2-to-1 Multiplexer (continued)
Note the regions of the multiplexer circuit shown:• 1 to 2 line Decoder• 1-to-2-line Decoder• 2 Enabling circuits• 2-input OR gate
To obtain a basis for multiplexer expansion, we combine the Enabling circuits and OR gate into a 2 2 AND-OR circuit:AND-OR circuit:
• 1-to-2-line decoder• 2 2 AND-OR
In general, for an 2n-to-1-line multiplexer:• n-to-2n-line decoder• 2n 2 AND-OR
Hoang Trang Reference Chapter 3 24
2 2 AND OR
Example: 4-to-1-line Multiplexer
2-to-22-line decoder 22 2 AND-OR
S1Decoder
Enabling circuits
S1Decoder
S1Decoder
4 3 2 AND-ORS0
S0
Y
S0
YI 1
I 0
Y
I2
Hoang Trang Reference Chapter 3 25
I 3
Multiplexer Width Expansion Select “vectors of bits” instead of “bits”
U lti l i f 2n 2 AND OR i Use multiple copies of 2n 2 AND-OR in parallel Example:
4 3 2 AND-ORI0,0
Y0. Example:
4-to-1quad multi- 2-to-4-Line decoder
4 3 2 AND-ORI3,0I 0,1D0A 0 Y1
.
.
.
. .quad multiplexer 4 3 2 AND-ORI3,1
I 0,2
D3A 1
Y2
. ..
.
.
4 3 2 AND-ORI3,2I 0,3
Y3
.
.
.
Hoang Trang Reference Chapter 3 26
I 3,3
.
Other Selection Implementations
Three-state logic in place of AND-ORS
I0
I
S0
I1
I 2
S1Y
I3
Gate input cost = 14 compared to 22 (or (b)
Hoang Trang Reference Chapter 3 27
18) for gate implementation
Combinational Logic Implementation- Multiplexer Approach 1p pp Implement m functions of n variables with:
• Sum-of-minterms expressionsSum of minterms expressions• An m-wide 2n-to-1 multiplexer
Design: g• Find the truth table for the functions.• In the order they appear in the truth table:
Apply the function input variables to the multiplexer inputs Sn 1, … , S0
Label the outputs of the multiplexer with the output variables
• Value-fix the information inputs to the multiplexer using the values from the truth table (for don’t
Hoang Trang Reference Chapter 3 28
using the values from the truth table (for don t cares, apply either 0 or 1)
Combinational Logic Implementation- Multiplexerp
Hoang Trang Reference Chapter 3 29
Example: Gray to Binary Code
Design a circuit to GrayA B C
Binaryx y zconvert a 3-bit Gray
code to a binary code
A B C x y z0 0 0 0 0 01 0 0 0 0 11 1 0 0 1 0 The formulation gives
the truth table on the
1 1 0 0 1 00 1 0 0 1 10 1 1 1 0 0
right It is obvious from this
1 1 1 1 0 11 0 1 1 1 00 0 1 1 1 1
table that X = C and theY and Z are more complex
0 0 1 1 1 1
Hoang Trang Reference Chapter 3 30
p
Gray to Binary (continued)
Rearrange the table soth t th i t bi ti
GrayA B C
Binaryx y zthat the input combinations
are in counting orderA B C x y z0 0 0 0 0 00 0 1 1 1 10 1 0 0 1 1
Functions y and z can be implemented using
0 1 0 0 1 10 1 1 1 0 01 0 0 0 0 1be implemented using
a dual 8-to-1-line multiplexer by:
1 0 1 1 1 01 1 0 0 1 01 1 1 1 0 1multiplexer by:
• connecting A, B, and C to the multiplexer select inputs• placing y and z on the two multiplexer outputs
1 1 1 1 0 1
Hoang Trang Reference Chapter 3 31
• connecting their respective truth table values to the inputs
Gray to Binary (continued)
D01D00
D11D10
1 10 0
D03D02D01
D13D12D11
11
11
0 0D04D05D06D07
OutD14D15D16D17
Out
1
1
11 0
0
0
0
Y Z
D07
S1S0
AB
S2
C
D17
S1S0
AB
S2
C
10
8-to-1MUX
8-to-1MUX
Note that the multiplexer with fixed inputs is identical to a
S0C S0C
Hoang Trang Reference Chapter 3 32
ROM with 3-bit addresses and 2-bit data!
Combinational Logic Implementation- Multiplexer Approach 2p pp
Implement any m functions of n + 1 variables by using:• An m wide 2n to 1 line multiplexer• An m-wide 2 -to-1-line multiplexer• A single inverter
Design:• Find the truth table for the functions.• Based on the values of the first n variables, separate the truth
table rows into pairsp• For each pair and output, define a rudimentary function of the
final variable (0, 1, X, )• Using the first n variables as the index, value-fix the
XUsing the first n variables as the index, value fix the information inputs to the multiplexer with the corresponding rudimentary functions
• Use the inverter to generate the rudimentary function X
Hoang Trang Reference Chapter 3 33
Use the inverter to generate the rudimentary function X
Example: Gray to Binary Code
Design a circuit to GrayA B C
Binaryx y zconvert a 3-bit Gray
code to a binary code
A B C x y z0 0 0 0 0 01 0 0 0 0 11 1 0 0 1 0 The formulation gives
the truth table on the
1 1 0 0 1 00 1 0 0 1 10 1 1 1 0 0
right It is obvious from this
1 1 1 1 0 11 0 1 1 1 00 0 1 1 1 1
table that X = C and theY and Z are more complex
0 0 1 1 1 1
Hoang Trang Reference Chapter 3 34
p
Gray to Binary (continued) Rearrange the table so that the input combinations are in
counting order, pair rows, and find rudimentary functionsg , p , yGrayA B C
Binaryx y z
RudimentaryFunctions of
C for y
Rudimentary Functions of
C for zC for y C for z
0 0 0 0 0 00 0 1 1 1 1
F = C F = C
0 1 0 0 1 10 1 1 1 0 01 0 0 0 0 1
F = C F = C
1 0 0 0 0 11 0 1 1 1 01 1 0 0 1 0
F = C
F CF C
F = C
Hoang Trang Reference Chapter 3 35
1 1 1 1 0 1F = CF = C
Gray to Binary (continued) Assign the variables and functions to the multiplexer inputs:
D00C D10C
D03D02D01D00
Out YCC
C
C D13D12D11D10
Out ZC
CCC C
S1S0
AB
D03
8-to-1MUX
C D13
8-to-1MUX
S1S0
AB
C
Note that this approach (Approach 2) reduces the cost by almost half compared to Approach 1.Thi lt i l ROM lik This result is no longer ROM-like
Extending, a function of more than n variables is decomposed into several sub-functions defined on a subset of the variables.
Hoang Trang Reference Chapter 3 36
The multiplexer then selects among these sub-functions.