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Chapter2<1>
DigitalDesignandComputerArchitecture,2nd Edition
Chapter2
DavidMoneyHarrisandSarahL.Harris
Chapter2<2>
• Introduction• BooleanEquations• BooleanAlgebra• FromLogictoGates• MultilevelCombinationalLogic• X’sandZ’s,OhMy• Karnaugh Maps• CombinationalBuildingBlocks• Timing
Chapter2::Topics
Chapter2<3>
Alogiccircuitiscomposedof:• Inputs• Outputs• Functionalspecification• Timingspecification
inputs outputsfunctional spec
timing spec
Introduction
Chapter2<4>
• Nodes– Inputs:A,B,C– Outputs:Y,Z– Internal:n1
• Circuitelements– E1,E2,E3– Eachacircuit
A E1
E2E3B
C
n1
Y
Z
Circuits
Chapter2<5>
• CombinationalLogic– Memoryless– Outputsdeterminedbycurrentvaluesofinputs
• SequentialLogic– Hasmemory– Outputsdeterminedbypreviousandcurrentvaluesofinputs
inputs outputsfunctional spec
timing spec
TypesofLogicCircuits
Chapter2<6>
• Everyelementiscombinational• Everynodeiseitheraninputorconnectstoexactlyoneoutput
• Thecircuitcontainsnocyclicpaths• Example:
RulesofCombinationalComposition
Chapter2<7>
• Functionalspecificationofoutputsintermsofinputs
• Example:S =F(A,B,Cin)Cout =F(A,B,Cin)
A S
S = A B CinCout = AB + ACin + BCin
BCin
CL Cout
BooleanEquations
Chapter2<8>
• Complement:variablewithabaroveritA,B,C
• Literal:variableoritscomplementA,A,B,B,C,C
• Implicant:productofliteralsABC,AC,BC
• Minterm:productthatincludesallinputvariablesABC,ABC,ABC
• Maxterm:sumthatincludesallinputvariables(A+B+C),(A+B+C),(A+B+C)
SomeDefinitions
Chapter2<9>
Y = F(A, B) =
• All equations can be written in SOP form• Each row has a minterm• A minterm is a product (AND) of literals• Each minterm is TRUE for that row (and only that row)• Form function by ORing minterms where the output is TRUE • Thus, a sum (OR) of products (AND terms)
Sum-of-Products(SOP)Form
A B Y0 00 11 01 1
0101
minterm
A BA BA B
A B
mintermnamem0m1m2m3
Chapter2<10>
Y = F(A, B) =
Sum-of-Products(SOP)Form
• All equations can be written in SOP form• Each row has a minterm• A minterm is a product (AND) of literals• Each minterm is TRUE for that row (and only that row)• Form function by ORing minterms where the output is TRUE • Thus, a sum (OR) of products (AND terms)
A B Y0 00 11 01 1
0101
minterm
A BA BA B
A B
mintermnamem0m1m2m3
Chapter2<11>
Y = F(A, B) = AB + AB = Σ(1, 3)
Sum-of-Products(SOP)Form
• All equations can be written in SOP form• Each row has a minterm• A minterm is a product (AND) of literals• Each minterm is TRUE for that row (and only that row)• Form function by ORing minterms where the output is TRUE • Thus, a sum (OR) of products (AND terms)
A B Y0 00 11 01 1
0101
minterm
A BA BA B
A B
mintermnamem0m1m2m3
Chapter2<12>Y = F(A, B) = (A + B)(A + B) = Π(0, 2)
• All Boolean equations can be written in POS form• Each row has a maxterm• A maxterm is a sum (OR) of literals• Each maxterm is FALSE for that row (and only that row)• Form function by ANDing the maxterms for which the
output is FALSE• Thus, a product (AND) of sums (OR terms)
Product-of-Sums(POS)Form
A + BA B Y0 00 11 01 1
0101
maxterm
A + BA + BA + B
maxtermnameM0M1M2M3
Chapter2<13>
• Youaregoingtothecafeteriaforlunch– Youwon’teatlunch(E)– Ifit’snotopen(O)or– Iftheyonlyservecorndogs(C)
• Writeatruthtablefordeterminingifyouwilleatlunch(E).
O C E0 00 11 01 1
BooleanEquationsExample
Chapter2<14>
• Youaregoingtothecafeteriaforlunch– Youwon’teatlunch(E)– Ifit’snotopen(O)or– Iftheyonlyservecorndogs(C)
• Writeatruthtablefordeterminingifyouwilleatlunch(E).
O C E0 00 11 01 1
0010
BooleanEquationsExample
Chapter2<15>
SOP&POSForm• SOP– sum-of-products
• POS– product-of-sums
O C E0 00 11 01 1
mintermO CO CO CO C
O + CO C E0 00 11 01 1
maxterm
O + CO + CO + C
Chapter2<16>
• SOP– sum-of-products
• POS– product-of-sums
O + CO C E0 00 11 01 1
0010
maxterm
O + CO + CO + C
O C E0 00 11 01 1
0010
minterm
O CO CO C
O C
E = (O + C)(O + C)(O + C)= Π(0, 1, 3)
E = OC= Σ(2)
SOP&POSForm
Chapter2<17>
• Axiomsandtheoremstosimplify Booleanequations
• Likeregularalgebra,butsimpler:variableshaveonlytwovalues(1or0)
• Duality inaxiomsandtheorems:– ANDsandORs,0’sand1’sinterchanged
BooleanAlgebra
Chapter2<18>
BooleanAxioms
Chapter2<19>
• B 1 = B• B + 0 = B
T1:IdentityTheorem
Chapter2<20>
1 =
=
B
0B
B
B
• B 1 = B• B + 0 = B
T1:IdentityTheorem
Chapter2<21>
• B 0 = 0• B + 1 = 1
T2:NullElementTheorem
Chapter2<22>
0 =
=
B
1B
1
0
• B 0 = 0• B + 1 = 1
T2:NullElementTheorem
Chapter2<23>
• B B = B• B + B = B
T3:Idempotency Theorem
Chapter2<24>
B =
=
B
BB
B
B
• B B = B• B + B = B
T3:Idempotency Theorem
Chapter2<25>
• B = B
T4:IdentityTheorem
Chapter2<26>
= BB
• B = B
T4:IdentityTheorem
Chapter2<27>
• B B = 0• B + B = 1
T5:ComplementTheorem
Chapter2<28>
B =
=
B
BB
1
0
• B B = 0• B + B = 1
T5:ComplementTheorem
Chapter2<29>
BooleanTheoremsSummary
Chapter2<30>
BooleanTheoremsofSeveralVars
Note: T8’ differs from traditional algebra: OR (+) distributes over AND (•)
( )
Chapter2<31>
Y =AB +AB
SimplifyingBooleanEquationsExample1:
Chapter2<32>
Y =AB +AB=B(A +A) T8=B(1) T5’=B T1
SimplifyingBooleanEquationsExample1:
Chapter2<33>
Y =A(AB +ABC)Example2:
SimplifyingBooleanEquations
Chapter2<34>
Y =A(AB +ABC)=A(AB(1+C)) T8=A(AB(1)) T2’=A(AB) T1=(AA)B T7=AB T3
Example2:
SimplifyingBooleanEquations
Chapter2<35>
• Y =AB =A +B
• Y =A +B =A B
AB Y
AB Y
AB Y
AB Y
DeMorgan’s Theorem
Chapter2<36>
• Backward:– Bodychanges– Addsbubblestoinputs
• Forward:– Bodychanges– Addsbubbletooutput
AB Y A
B Y
AB YA
B Y
BubblePushing
Chapter2<37>
AB
YCD
• What is the Boolean expression for this circuit?
BubblePushing
Chapter2<38>
AB
YCD
• What is the Boolean expression for this circuit?
Y = AB + CD
BubblePushing
Chapter2<39>
AB
C
DY
• Begin at output, then work toward inputs• Push bubbles on final output back • Draw gates in a form so bubbles cancel
BubblePushingRules
Chapter2<40>
AB
C YD
BubblePushingExample
Chapter2<41>
AB
C YD
no outputbubble
BubblePushingExample
Chapter2<42>
bubble oninput and outputA
B
C
DY
AB
C YD
no outputbubble
BubblePushingExample
Chapter2<43>
AB
C
DY
bubble oninput and outputA
B
C
DY
AB
C YD
Y = ABC + D
no outputbubble
no bubble oninput and output
BubblePushingExample
Chapter2<44>
• Two-levellogic:ANDsfollowedbyORs• Example:Y =ABC +ABC +ABC
BA C
Y
minterm: ABC
minterm: ABC
minterm: ABC
A B C
FromLogictoGates
Chapter2<45>
• Inputsontheleft(ortop)• Outputsonright(orbottom)• Gatesflowfromlefttoright• Straightwiresarebest
CircuitSchematicsRules
Chapter2<46>
• WiresalwaysconnectataTjunction• Adotwherewirescrossindicatesaconnectionbetweenthewires
• Wirescrossingwithout adotmakenoconnection
wires connectat a T junction
wires connectat a dot
wires crossingwithout a dot do
not connect
CircuitSchematicRules(cont.)
Chapter2<47>
A1 A00 00 11 01 1
Y3 Y2 Y1 Y0A3 A20 00 00 00 0
0 00 10 11 01 10 0
0 10 10 11 0
0 11 01 01 10 00 1
1 01 01 11 1
1 01 11 11 1
A0
A1
PRIORITYCiIRCUIT
A2
A3
Y0
Y1
Y2
Y3
• Example:PriorityCircuitOutputassertedcorrespondingtomostsignificantTRUEinput
Multiple-OutputCircuits
Chapter2<48>
0
A1 A00 00 11 01 1
0
00
Y3 Y2 Y1 Y00000
0011
0100
A3 A20 00 00 00 0
0 0 0 1 0 00 10 11 01 10 0
0 10 10 11 0
0 11 01 01 10 00 1
1 01 01 11 1
1 01 11 11 1
0001
1110
0000
0000
1 0 0 01111
0000
0000
0000
1 0 0 01 0 0 0
A0
A1
PRIORITYCiIRCUIT
A2
A3
Y0
Y1
Y2
Y3
• Example:PriorityCircuitOutputassertedcorrespondingtomostsignificantTRUEinput
Multiple-OutputCircuits
Chapter2<49>
A1 A00 00 11 01 1
0000
Y3 Y2 Y1 Y00000
0011
0100
A3 A20 00 00 00 0
0 0 0 1 0 00 10 11 01 10 0
0 10 10 11 0
0 11 01 01 10 00 1
1 01 01 11 1
1 01 11 11 1
0001
1110
0000
0000
1 0 0 01111
0000
0000
0000
1 0 0 01 0 0 0
A3A2A1A0Y3Y2
Y1
Y0
PriorityCircuitHardware
Chapter2<50>
A1 A00 00 11 01 1
0000
Y3 Y2 Y1 Y00000
0011
0100
A3 A20 00 00 00 0
0 0 0 1 0 00 10 11 01 10 0
0 10 10 11 0
0 11 01 01 10 00 1
1 01 01 11 1
1 01 11 11 1
0001
1110
0000
0000
1 0 0 01111
0000
0000
0000
1 0 0 01 0 0 0
A1 A00 00 11 XX X
0000
Y3 Y2 Y1 Y00001
0010
0100
A3 A20 00 00 00 1
X X 1 0 0 01 X
Don’tCares
Chapter2<51>
• Contention:circuittriestodriveoutputto1and 0– Actualvaluesomewhereinbetween– Couldbe0,1,orinforbiddenzone– Mightchangewithvoltage,temperature,time,noise– Oftencausesexcessivepowerdissipation
• Warnings:– Contentionusuallyindicatesabug.– Xisusedfor“don’tcare”andcontention- lookatthecontext
totellthemapart
A = 1Y = X
B = 0
Contention:X
Chapter2<52>
• Floating,highimpedance,open,highZ• Floatingoutputmightbe0,1,orsomewhereinbetween– Avoltmeterwon’tindicatewhetheranodeisfloating
TristateBuffer
E A Y0 0 Z0 1 Z1 0 01 1 1
A
E
Y
Floating:Z
Chapter2<53>
• Floatingnodesareusedintristatebusses– Manydifferentdrivers– Exactlyoneisactiveatonce
en1
to busfrom bus
en2
to busfrom bus
en3
to busfrom bus
en4
to busfrom bus
sha
red
bu
s
processor
video
Ethernet
memory
TristateBusses
Chapter2<54>
• Booleanexpressionscanbeminimizedbycombiningterms
• K-mapsminimizeequationsgraphically• PA +PA =P
C 00 01
0
1
Y
11 10AB
1
1
0
0
0
0
0
0
C 00 01
0
1
Y
11 10AB
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
B C0 00 11 01 1
A0000
0 00 11 01 1
1111
11000000
Y
Karnaugh Maps(K-Maps)
Chapter2<55>
C 00 01
0
1
Y
11 10AB
1
0
0
0
0
0
0
1
B C0 00 11 01 1
A0000
0 00 11 01 1
1111
11000000
Y
• Circle 1’s in adjacent squares• In Boolean expression, include only
literals whose true and complement form are not in the circle
Y = AB
K-Map
Chapter2<56>
C 00 01
0
1
Y
11 10AB
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
1
B C Y0 0 00 1 01 01 1 1
Truth Table
C 00 01
0
1
Y
11 10ABA
0000
0 0 00 1 01 0 01 1 1
1111
K-Map
3-InputK-Map
Chapter2<57>
C 00 01
0
1
Y
11 10AB
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
1 0
B C Y0 0 00 1 01 01 1 1
Truth Table
C 00 01
0
1
Y
11 10ABA
0000
0 0 00 1 01 0 01 1 1
1111
0
1
1
1
0
0
0
K-Map
Y = AB + BC
3-InputK-Map
Chapter2<58>
• Complement:variablewithabaroveritA,B,C
• Literal:variableoritscomplementA,A,B,B,C,C
• Implicant:productofliteralsABC,AC,BC
• Primeimplicant: implicant correspondingtothelargestcircleinaK-map
K-MapDefinitions
Chapter2<59>
• Every1mustbecircledatleastonce• Eachcirclemustspanapowerof2(i.e.1,2,4)squaresineachdirection
• Eachcirclemustbeaslargeaspossible• Acirclemaywraparoundtheedges• A“don'tcare”(X)iscircledonlyifithelpsminimizetheequation
K-MapRules
Chapter2<60>
01 11
01
11
10
00
00
10AB
CD
Y
0
C D0 00 11 01 1
B0000
0 00 11 01 1
1111
1
110111
YA00000000
0 00 11 01 1
0000
0 00 11 01 1
1111
11111111
11
100000
4-InputK-Map
Chapter2<61>
01 11
1
0
0
1
0
0
1
101
1
1
1
1
0
0
0
1
11
10
00
00
10AB
CD
Y
0
C D0 00 11 01 1
B0000
0 00 11 01 1
1111
1
110111
YA00000000
0 00 11 01 1
0000
0 00 11 01 1
1111
11111111
11
100000
4-InputK-Map
Chapter2<62>
01 11
1
0
0
1
0
0
1
101
1
1
1
1
0
0
0
1
11
10
00
00
10AB
CD
Y
Y = AC + ABD + ABC + BD
0
C D0 00 11 01 1
B0000
0 00 11 01 1
1111
1
110111
YA00000000
0 00 11 01 1
0000
0 00 11 01 1
1111
11111111
11
100000
4-InputK-Map
Chapter2<63>
0
C D0 00 11 01 1
B0000
0 00 11 01 1
1111
1
110X11
YA00000000
0 00 11 01 1
0000
0 00 11 01 1
1111
11111111
11
XXXXXX
01 11
01
11
10
00
00
10AB
CD
Y
K-MapswithDon’tCares
Chapter2<64>
0
C D0 00 11 01 1
B0000
0 00 11 01 1
1111
1
110X11
YA00000000
0 00 11 01 1
0000
0 00 11 01 1
1111
11111111
11
XXXXXX
01 11
1
0
0
X
X
X
1
101
1
1
1
1
X
X
X
X
11
10
00
00
10AB
CD
Y
K-MapswithDon’tCares
Chapter2<65>
0
C D0 00 11 01 1
B0000
0 00 11 01 1
1111
1
110X11
YA00000000
0 00 11 01 1
0000
0 00 11 01 1
1111
11111111
11
XXXXXX
01 11
1
0
0
X
X
X
1
101
1
1
1
1
X
X
X
X
11
10
00
00
10AB
CD
Y
Y = A + BD + C
K-MapswithDon’tCares
Chapter2<66>
• Multiplexers• Decoders
CombinationalBuildingBlocks
Chapter2<67>
• SelectsbetweenoneofN inputstoconnecttooutput
• log2N-bitselectinput– controlinput• Example: 2:1Mux
Multiplexer(Mux)
Y0 00 11 01 1
0101
0000
0 00 11 01 1
1111
0011
0
1
S
D0Y
D1
D1 D0S Y01 D1
D0
S
Chapter2<68>2-<68>
• Logicgates– Sum-of-productsform
Y
D0
S
D1
D1
Y
D0
S
S 00 01
0
1
Y
11 10D0 D1
0
0
0
1
1
1
1
0
Y = D0S + D1S
• Tristates– For an N-input mux, use N
tristates– Turn on exactly one to
select the appropriate input
MultiplexerImplementations
Chapter2<69>
A B Y0 0 00 1 01 0 01 1 1
Y = AB
00
Y011011
A B
• Using the mux as a lookup table
LogicusingMultiplexers
Chapter2<70>
A B Y0 0 00 1 01 0 01 1 1
Y = AB
A Y
0
1
0 0
1
A
BY
B
• Reducing the size of the mux
LogicusingMultiplexers
Chapter2<71>
2:4Decoder
A1A0
Y3Y2Y1Y000
011011
0 00 11 01 1
0001
Y3 Y2 Y1 Y0A0A10010
0100
1000
• N inputs, 2N outputs• One-hot outputs: only one output HIGH at
once
Decoders
Chapter2<72>
Y3
Y2
Y1
Y0
A0A1
DecoderImplementation
Chapter2<73>
2:4Decoder
AB
00011011
Y = AB + AB
Y
ABABABAB
Minterm
= A B
• OR minterms
LogicUsingDecoders
Chapter2<74>
A
Y
Time
delay
A Y
• Delay between input change and output changing
• How to build fast circuits?
Timing
Chapter2<75>
A
Y
Time
A Y
tpd
tcd
• Propagation delay: tpd = max delay from input to output
• Contamination delay: tcd = min delay from input to output
Propagation&ContaminationDelay
Chapter2<76>
• Delay is caused by– Capacitance and resistance in a circuit– Speed of light limitation
• Reasons why tpd and tcd may be different:– Different rising and falling delays– Multiple inputs and outputs, some of which are
faster than others– Circuits slow down when hot and speed up when
cold
Propagation&ContaminationDelay
Chapter2<77>
AB
C
D Y
Critical Path
Short Path
n1n2
Critical (Long) Path: tpd = 2tpd_AND + tpd_OR
Short Path: tcd = tcd_AND
Critical(Long)&ShortPaths
Chapter2<78>
• When a single input change causes an output to change multiple times
Glitches
Chapter2<79>
AB
C
Y
00 01
1
Y
11 10AB
1
1
0
1
0
1
0
0
C
0
Y = AB + BC
• What happens when A = 0, C = 1, B falls?
GlitchExample
Chapter2<80>
A = 0B = 1 0
C = 1
Y = 1 0 1
Short Path
Critical Path
B
Y
Time
1 0
0 1
glitch
n1
n2
n2
n1
GlitchExample(cont.)
Chapter2<81>
00 01
1
Y
11 10AB
1
1
0
1
0
1
0
0
C
0
Y = AB + BC + ACAC
B = 1 0Y = 1
A = 0
C = 1
FixingtheGlitch
Chapter2<82>
• Glitches don’t cause problems because of synchronous design conventions (see Chapter 3)
• It’s important to recognize a glitch: in simulations or on oscilloscope
• Can’t get rid of all glitches – simultaneous transitions on multiple inputs can also cause glitches
WhyUnderstandGlitches?
