Chapter 15 Multistage Amplifiers

2 Microelettronica – Circuiti integrati analogici 2/edRichard C. Jaeger, Travis N. Blalock

Copyright © 2005 – The McGraw-Hill Companies srl

Chapter 15Multistage Amplifiers

Microelectronic Circuit Design

Richard C. Jaeger

Travis N. Blalock



Chapter Goals

• Understand analysis and design of ac-coupled multistage amplifiers including voltage gain, input and output resistances and small signal limitations.

• Understand analysis and design of dc-coupled multistage amplifiers.

• Discuss characteristics of Darlington configuration and cascode amplifier.

• Explore dc and ac properties of differential amplifiers.• Understand basic three-stage op amp.• Explore design of class-A, class-B, class-AB output stages.• Discuss characteristics and design of electronic current sources.• Continue understanding the use of SPICE in circuit analysis.



AC-coupled Amplifiers: Circuit



AC-coupled Amplifiers: Description• MOSFET M1operating in C-S configuration provides high input resistance

and moderate voltage gain.• BJT Q2 in C-E configuration, the second stage, provides high gain.• BJT Q3, an emitter-follower gives low output resistance and buffers the high

gain stage from the relatively low load resistance.• Bias resistors are replaced by• Input and output of overall amplifier is ac-coupled through capacitors C1

and C6.• Bypass capacitors C2 and C4 are used to get maximum voltage gain from the

two inverting amplifiers.• Interstage coupling capacitors C3 and C5 transfer ac signals between

amplifiers but provide isolation at dc, and prevent Q-points of the transistors from being affected.

212RR

BR

433RR

BR



AC-coupled Amplifiers: Equivalent Circuits

AC Equivalent

Small-signal Equivalent

DC Equivalent



AC-coupled Amplifiers: Input Resistance and Voltage Gain

Ω598kΩ2.17Ω6201

I

R

kΩ31.4kΩ8.51kΩ7.42

I

R

Ω232Ω250kΩ3.33

L

R

ΩM1G

RinR

-4.78Ω478S01.011

1v2

v

1

LR

mg

vA

kΩ54.33

)13

(32

322

LR

or

IR

inR

IR

LR

-222kΩ54.3mS8.62

222

v3

v

2

L

Rm

gv

A

950.0

3)1

3(

3

3)1

3(

3v

ov3

LR

or

LR

ov

A

998123

in

RI

Rin

R

vA

vA

vAvA

Ω478Ω2390Ω5982

598211

r

inR

IR

LR



AC-coupled Amplifiers: Output Resistance

Ω3990Ω54200Ω4310

222xixv

3

or

IRRCE

outIR

thR

To find output resistance, test voltage is applied at amplifier output.

5.6081

3990S0796.0

988.03300

13

3

3

333003

3300xixv

3

xv

3300xv

eirixi

o

thR

mg

oout

RoutR

outR



AC-coupled Amplifiers: Current and Power GainInput current delivered to amplifier from source is

and current delivered to load by amplifier is

iv71090.9i

v

ii

inR

IR

sv99.3250

s998v

250i

v

250ov

oi vA

61003.4

iv71090.9

i3.99v

iioi iA

91002.461003.4998

iioi

ivov

i

AvAsPoP

PA



AC-coupled Amplifiers: Input Signal Range• For first stage,

• For second stage,

• For third stage,

• On the whole,

V202.0990.0

)21(2.0)(2.0 ivTNVGS

V1

v

mV06.10.990

mV05.1mV05.14.780.005mV5

mV5

iv

v1A1

v

1v

v1A

2v

be2v

μV7.92005.0)990.0(

21

331

mV53

331

)sv990.0(21

331

3v

be3v

vA

vA

LR

mg

iv

bev

LR

mg

vA

vA

LR

mg

μV7.92μV)7.92mV,06.1mV,202min( i

v

mV5.92μV)7.92(998μV)7.92( vAov



AC-coupled Amplifiers: Methods to Improve Voltage Gain• Gain of C-S amplifier is inversely proportional to square

root of drain current, so voltage gain could be increased by reducing ID1 while maintaining a constant voltage drop across RD1. Signal range could be improved by increasing current in output stage and voltage drop across RE3.

• Q1 could be replaced with a FET. This could cause gain loss in third stage since gain of C-D amplifier is typically < that of a C-C stage. However, this loss could be made up by improving gain of first and second stages.



Common-Emitter Cascade

To achieve maximum gain, several C-E stages can be cascaded.

For the final stage,

For all other stages,

1231-n

vov

...

1v2

v

iv1

v

vA

vA

vAvA

CCVLRmngvnA 10

)1

(

i

rLiRmigviA

If gain is limited by interstage resistances, each stage has a gain of about -10VCC and overall gain is:

If gain is limited by input resistance of transistors, it is given by:

Normally as signal and power levels usually increase in each successive stage of most amplifiers. Since o< 10VCC , this case often represents the actual limit.

n

CCVvnA

10

CCVonoo

CnIC

InvnA 10...

3211

1CI

CnI



Direct-coupled Amplifiers: Circuit

• Coupling capacitors in series with signal path- C1, C3, C5, and C6 are eliminated as they prevent the amplifier from providing gain at dc or very low frequencies.

• Additional bias resistors in individual stages are also removed, making design less expensive.

• Bypass capacitors- C2 and C4 affect gain at low frequencies but don’t inherently prevent the amplifier from operating at dc.

• Symmetrical power supplies are used to set Q-point voltages at input and output to about zero.

•Alternating pnp or p-channel and npn or n-channel transistors are used from stage to stage to take maximum advantage of available power supply voltage.



Direct-coupled Amplifiers: DC Analysis

Voltage at drain of M1 provides base bias for Q2 and voltage at collector of Q2 provides base bias for Q3. All transistors operate in active region irrespective of direct connection between stages.

2216005.7(0

201.02

2

D

ITNVGS

VnKDI

So, ID = 6.66. mA (which would produce 10.7 V drop across RS1 and cut off FET) or ID =5.29 mA (correct value).

IB2 << ID,

which is enough to pinch off M1.

F2 =150, so IC2 =1.83 mA and IB2 = 12.2 A.IB3 << IC2,

which < 0.7 V , so Q2 is in active region.

V26.3964.022.4

V22.46205.7

DSV

DIDV

1.84mA1400

5.7

EB2

VD

V

E2I

V82.3

V10.1V5.74700

C2V

EB2V

D1V

EC2V

C2I

C2V



Direct-coupled Amplifiers: DC Analysis (contd.)

0.4V0.7V-V10.1 BE3

VC2

VoV

mA99.32503300

V5.7

oVoV

LI3

IE3

I

F3 = 80, so IC3 =3.94 mA and IB3 = 49.3 A

V10.70.40V-5.75.7 E3

VCE3

V thus Q3 is in active region.

There is an offset voltage of 0.4 V at output and a nonzero dc current exists in 250 W load resistor. In an ideal design, offset voltage would be zero and no dc current would appear in load.

Based on Q-point values, small-signal parameters can be calculated.



Direct-coupled Amplifiers: AC Analysis

• Values of interstage capacitors are higher than those in ac-coupled amplifier due to absence of bias resistors.

• Overall characteristics are similar to those in ac-coupled amplifier as Q-points and small-signal parameters of transistors are similar

• Dc coupling requires fewer components than ac-coupling but Q-points of various stages become interdependent.

• If Q-point of one stage shifts, Q-points of all other stages might also shift.



Direct-coupled Amplifiers: Darlington Circuit

Darlington circuit behaves similar to the single transistor but has a current gain given by the product of current gains of individual transistors.

DC Analysis: For F1, F2 >>1,

VBE of composite transistor = 2 diode voltage drops. So VCE >(VBE1 + VBE2) .

BIF2F1C2

IC1

IC

I

AC Analysis: For the composite transistor,

212

1

11' r

oyr

012

y

2/221

'm

gymg

o2ryor )3/2(

1

22'

210

211

21'oo

vy

yo

3/2

02

1v2

v'

fi

f



Direct-coupled Amplifiers: Cascode Circuit

Cascode circuit is cascade connection of C-E and C-B amplifiers, used in high gain amplifiers and high output resistance current sources.

DC Analysis: For a high current gain,

For forward-active operation of Q2,C1

IC1

IFC2I

CI

AC Analysis: For the composite transistor,

11

11' ryr

012

y

121'

mgymg

o2r

o2yor

1

22'

10

211

21'o

vy

yo

220

21

v2

v'

foi

f

BEVBBVBE1

VBE2

VBBVCE1

V 2



Differential Amplifiers

• Differential amplifiers,also considered the C-C/C-B cascade, eliminate the bypass capacitors as well as the external coupling capacitors at the input and output of direct-coupled amplifiers.

• Each circuit has two inputs.

• Differential-mode output voltage is the voltage difference between collectors, drains of the two transistors.Ground referenced outputs can also be taken from collector/drain.

• Ideal differential amplifier uses perfectly matched transistors.



Bipolar Differential Amplifiers: DC Analysis

Both inputs are set to zero, emitters are connected together.

If transistors are matched,

BEVBE2

VBE1

V

CV

C2V

C1V

CI

C2I

C1I EI

E2I

E1I BI

B2I

B1I

EE2R

BEV

EEV

EI

EIFCI

F

CI

BI

CR

CI

CCV

C2V

C1V CE2

VCE1

V

V0C2

VC1

VOD

V

Terminal currents are also equal.



Small-Signal Transfer Characteristic

T

V2id

v

CI

TV2

BE2v

BE1v

CI

C2I

C1I tanh2tanh2

The current switch is a digital application of the differential amplifier. Large-signal transfer characteristic of differential amplifier is given by:

Even-order distortion terms are eliminated.This increases signal-handling capability of differential pair. For small-signal operation, liner term must be dominant. Hence, we set the third-order term to be one-tenth the linear term.

...

7

31517

5

152

3

312

TV2id

v

TV2id

v

TV2id

v

TV2id

v

CI

mV273.02 id

vTVid

v



Bipolar Differential Amplifiers: DC Analysis (Example)• Problem: Find Q-points of transistors in the differential

amplifier.

• Given data: VCC=VEE=15 V, REE=RC=75k, F =100

• Analysis: A3.95)3102(75

V7.015

EE2R

BEV

EEV

EI

A4.94101100 EIEIFC

I

A944.0100

A4.94

F

CI

BI

V62.8V)7.0(--V92.7

V92.715

EVC

VCE

VC

RC

IC

V

Due to symmetry, both transistors are biased at Q-point (94.4 A, 8.62V)



Bipolar Differential Amplifiers: AC Analysis

21id

v

icvv 22id

v

icvv

Circuit analysis is done by superposition of differential-mode and common-mode signal portions.

21 cv

cv

odv

221 c

vc

vocv

icvid

v

ccAcd

A

dcAdd

A

ocvod

v

Add = differential-mode gain

Acd = common-mode to differential-mode conversion gain

Acc = common-mode gain

Adc = differential mode to common-mode conversion gain

For ideal symmetrical amplifier, Acd = Adc = 0.

Purely differential-mode input gives purely differential-mode output and vice versa.

icvid

v

ccAdd

A

ocvod

v 0

0



Bipolar Differential Amplifiers: Differential-mode Gain and Input Resistance

0ev0)22(evev)

4v

3v)((

mggEEGEEGgmg

2id

v

4v

ev2id

v

3v ev

2id

v

4v

Output signal voltages are:

2id

v

c1v

CRmg

2id

v

c2v

CRmg

idv

odv

CRmg

2id

v

3v

Emitter node in differential amplifier represents virtual ground for differential-mode input signals.



Bipolar Differential Amplifiers: Differential-mode Gain and Input Resistance (contd.)

CRmg

ddA

0ic

vidvod

vDifferential-mode gain for balanced output, is:

If either vc1 or vc2 is used alone as output, output is said to be single-ended.

c2v

c1v

odv

220

icvid

vc1

v

1dd

AC

Rmg

ddA

22

0ic

vidvc2

v

2dd

AC

Rmg

ddA

Differential-mode input resistance is small-signal resistance presented to differential-mode input voltage between the two transistor bases.

If vid =0, . For single-ended outputs,

ridR 2

b1i/

idv

CRorC

Rod

R 2)(2 CR

odR

r

)2/id

v(

b1i



Bipolar Differential Amplifiers: Common-mode Gain and Input Resistance

Both arms of differential amplifier are symmetrical. So terminal currents and collector voltages are equal. Characteristics of differential pair with common-mode input are similar to those of a C-E (or C-S) amplifier with large emitter (or source) resistor.

Output voltages are:EE

Ror )1(2ic

v

bi

icv

)1(2bi

c2v

c1v

EERor

CRo

CRo

icv

icv

)1(2

)1(2b

i)1(2ev

EERor

EERo

EERo



Bipolar Differential Amplifiers: Common-mode Gain and Input Resistance (contd.)

EEV

CV

EER

CR

EERor

CRo

ccA22)1(2

0id

vicvocv

Common-mode gain is given by:

For symmetrical power supplies, common-mode gain =0.5. Thus, common-mode output voltage and Acc is 0 if REE is infinite. This result is obtained since output resistances of transistors are neglected. A more accurate expression is:

Therefore, common-mode conversion gain is found to be 0.0c2

vc1

vod

v

EE

RoroC

RccA2

11

EERorEE

Ror

icR )1(22

)1(2

bi2ic

v



Common-Mode Rejection ratio (CMRR)• Represents ability of amplifier to amplify desired differential-mode input

signal and reject undesired common-mode input signal.

• For differential output, common-mode gain of balanced amplifier is zero, CMRR is infinite. For single-ended output,

• For infinite REE , CMRR is limited by of . If term containing REE is dominant

Thus for differential pair biased by resistor REE , CMRR is limited by available negative power supply.

• Due to mismatches, , gives fractional

mismatch between small-signal device parameters in the two arms of differential pair. Hence gmREE product is maximized.

EERmgfo

ccAddA

cmAdmA

2112

12/CMRR

EEVEERC

IEERmg 2040CMRR

gg

EERmgCMRR21

)21

(2gggg

gg



Analysis of Differential Amplifiers Using Half-Circuits

• Half-circuits are constructed by first drawing the differential amplifier in a fully symmetrical form- power supplies are split into two equal halves in parallel, emitter resistor is separated into two equal resistors in parallel.

• None of the currents or voltages in the circuit are changed.

• For differential mode signals, points on the line of symmetry are virtual grounds connected to ground for ac analysis

• For common-mode signals, points on line of symmetry are replaced by open circuits.



Bipolar Differential-mode Half-circuits

Applying rules for drawing half-circuits, the two power supply lines and emitter become ac grounds. The half-circuit represents a C-E amplifier stage.

2id

v

c1v

CRmg

2id

v

c2v

CRmg

idv

c2v

c1vov

CRmg

Direct analysis of the half-circuits yield:

ridR 2

b1i/

idv

)(2 orCR

odR



Bipolar Common-mode Half-circuits

• All points on line of symmetry become open circuits.• DC circuit with VIC set to zero is used to find amplifier’s Q-point.• Last circuit is used for for common-mode signal analysis and

represents the C-E amplifier with emitter resistor 2REE.



Bipolar Common-mode Input Voltage Range

For symmetrical power supplies, VEE >> VBE, and RC = REE,

EER2

CR

F

CCV

BEV

EEV

EER2

CR

F

CCV

ICV

EER

EEV

BEV

ICV

FCI

ICV

CR

CI

CCV

CBV

1

1

2

0

3CC

V

ICV



Biasing with Electronic Current Sources• Differential amplifiers are biased using electronic

current sources to stabilize the operating point and increase effective value of REE to improve CMRR

• Electronic current source has a Q-point current of ISS and an output resistance of RSS as shown.

• DC model of the electronic current source is a dc current source, ISS while ac model is a resistance RSS.

SPICE model includes both ac and dc models.

SSR

0V

SSI

DCI



MOSFET Differential Amplifiers: DC Analysis

Op amps with MOSFET inputs have a high input resistance and much higher slew rate that those with bipolar input stages.

Using half-circuit analysis method, we see that IS = ISS /2.

nKSS

I

TNVnKD

2I

TNVGS

V

TNVGS

VnKDI

2

2

DRDIDDVD2

VD1

V 0oV and

GSVDRDIDDV

SVDV

DSV



Small-Signal Transfer Characteristic

MOS differential amplifier gives improved linear input signal range and distortion characteristics over that of a single transistor.

Second-order distortion product is eliminated and distortion is greatly reduced. However some distortion prevails as MOSFETs are nor perfect square law devices and some distortion arises through voltage dependence of output impedances of the transistors.

22

2 TNV

GS2v

TNV

GS1vnK

D2I

D1I

2id

vGS

VGS2

v

For symmetrical differential amplifier with purely differential-mode input

2id

vGS

VGS1

v

idvmg

idvTNV

GSVnK

D2I

D1I



MOSFET Differential Amplifiers: DC Analysis (Example)• Problem: Find Q-points of transistors in the differential

amplifier.

• Given data: VDD=VSS=12 V, ISS =200 A, RSS = 500 k, RD = 62 k = 0.0133 V-1, Kn = 5 mA/ V2, VTN =1V

• Analysis:A100

2SS

I

DI

V8.6

TNVDRDI-DDVIC

VTNV

DR

DI-

DDV-

ICV

GDV

V20.125mA/V

A2001 GS

V

V7V2.1)A)(62k100(-V12 DS

V

To maintain pinch-off operation of M1 for nonzero VIC ,



MOSFET Differential Amplifiers: Differential-mode Input Signals

2id

v

d1v DRmg

2id

v

d2v DRmg

idv

odv DRmg

Source node in differential amplifier represents virtual ground Differential-mode gain for balanced output is

Gain for single-ended output is

DRmgdd

A

0ic

vidvod

v

220

icvid

vd1

v

1dd

AD

Rmg

ddA

220

icvid

vd2

v

2dd

AD

Rmg

ddA

id

R DRod

R 2



MOSFET Differential Amplifiers: Common-mode Input Signals

Electronic current source is modeled by twice its small-signal output resistance representing output resistance of the current source.

Common-mode half-circuit is similar to inverting amplifier with 2RSS as source resistor.

icv

21d2v

d1v

SSRmgD

Rmg

icv

icv

21

2sv

SSRmgSS

Rmg

0d2

vd1

vod

v Thus, common-mode conversion gain= 0

SSR

DR

SSRmgD

RmgccA

2210

idvic

vocv

Due to infinite current gain of FET, ro can be neglected.

icR



Common-Mode Rejection ratio (CMRR)• For purely common-mode input signal, output of balanced MOS

amplifier is zero, CMRR is infinite. For single-ended output,

• RSS (which is much > REE and thus provides more Q-point stability) should be maximized.

• To compare MOS amplifier directly to BJT amplifier, assume that MOS amplifier is biased by

• From given data in example, MOS amplifier’s CMRR=54 or 35 dB (almost 10 dB worse than BJT amplifier).To increase CMRR in BJT and FET amplifiers, current sources with higher RSS or REE are used.

SSRmg

SSR

DR

DRmg

ccAddA

cmAdmA

)2/(

2/)(2/CMRR

SSI

GSV

SSV

SSR

TNV

GSV

GSV

SSV

TNV

GSV

SSR

SSI

TNV

GSV

SSR

DI

)(2CMRR



Two-port model for Differential Amplifiers

Two-port model simplifies circuit analysis of differential amplifiers.

Expressions for FET are obtained by substituting RSS for REE.

EERfocR

orodR

EERcmv

cmv

EERmg

mgcmi

dmvmg

dmi

2

2

221



Differential Amplifier Design (Example)

• Problem: Find Q-points of transistors in the differential amplifier.

• Given data: Adm=40 dB, Rid >250 k single-ended CMRR> 80 dB, VIC at least ±5V, MOSFETs with: = 0.0133 V-1, Kn’ = 50 A/ V2, VTN =1V,

BJTs with : F =100, VA =75V, IS =0.5 fA

• Assumptions: Active-region operation, symmetrical power supplies, o = F, vid maximum of ±30 mV.

• Analysis:

Adm=40 dB =100. To achieve this gain with resistively loaded amplifier, we use BJT. For Adm = gm RC =40 IC RC , required gain can be obtained with voltage drop of 2.5 V across RC.

For bipolar differential amplifier, Rid =2r, so, r =125 k. μA20

rT

VoC

I



Differential Amplifier Design (Example contd.)Choose IC = 15 A to provide safety margin. So RC =2.5 V/15 A =167 k

Choose RC = 180 k as the nearest value with 5% toleranceand alos to compensate for neglecting ro in the analysis.

VIC of 5V requires collector voltage to be at least 5 V at all times. We also know that vid can be a maximum of ±30 mV for linearity. So ac component of differential output will not be greater than 100(0.03 V)=3V, half of which appears at each collector. Thus dc signal across RC won’t exceed 4 V( 2.5 V dc + 1.5 V ac) and positive power supply must fulfill

Choose VCC =10 V to dive desired margin of 1 V, For symmetrical supplies, VEE = -10 V. Single-ended CMRR of 80 dB needs

Choose current source with IEE

=30 A and REE > 20 M

V94)V5(V4 IC

VCC

V

MΩ7.16)μA15)(V/40(

410CMRR mgEER



Two-stage Prototype of an Op Amp• For higher gain, pnp C-E amplifier is

connected at output of the input stage differential amplifier.

• Virtual ground at emitter node allows input stage to achieve full inverting amplifier gain without needing emitter bypass capacitor.

• Pnp transistor permits direct coupling between stages, allows emitter of pnp to be connected to ac ground and provides required voltage level shift to bring output back to zero.

• Bypass and coupling capacitors are thus eliminated.

Differential amplifier provides desired differential input,CMRR and ground referenced output as the input stage of op amp.



Two-stage Op Amp: DC AnalysisThis circuit requires a resistance in series with emitter of Q3 to stabilize Q-point (as collector current of Q3 is exponentially dependent on base-emitter voltage), at the expense of voltage gain loss.

From dc equivalent circuit, IE1= IE2 = I1 /2. If base current of Q3 is neglected and C-B current gains are one,

As both inputs are zero, output also=0

IS3 is saturation current. For zero offset voltage

BEVCR

1I

CCV

CE2V

CE1V

2

REEVC3

I /CC

VEC3

V

S3

IC3

I

TVEB3

V 1ln

S3IC3

I

F3

C3I

21

I

F

TV

CR 1ln

2



Two-stage Op Amp: AC Analysis (Differential Mode)

Half-circuit can be constructed from ac equivalent circuit in spite of asymmetricity, as voltage variations at collector of Q2 don’t substantially alter transistor current in forward-active operation region.

From small-signal circuit model,

Rm

gvt

A

rC

Rmg

LRm

g

vtA

3c2

vov

2

)3

(2

212

2

idvc2

v

1



Two-stage Op Amp: AC Analysis (Differential Mode contd.)

This can be rewritten as

Base current of Q3 is neglected so, IC2RC=VBE3=0.7 V, IC3R=VEE,

3

322)

3)(

3(

22

21c2

vov

idvc2

v

idv

ov

r

CR

RoC

Rm

gR

mgr

CRm

g

vtA

vtA

dmA

322

340

340

3240

21

33

33221

oCR

CI

CIC

I

RC

IoC

RC

I

oCR

mg

Rm

gRoC

Rm

g

dmA

2

3

3

281

560

CIC

I

o

EEV

dmA

Upper limit onIC2 and I1 is set by maximum dc bias current at input, lower limit on IC3 is set by minimum current to drive total load impedance at output.

12

22

idi/

idv rr

idR R

orRoutR

3



Two-stage Op Amp: AC Analysis (Common Mode)

From ac equivalent circuit, we observe that circuitry beyond collector of Q2 is same as that in differential mode half-circuit. The difference in collector currents causes difference in output voltage.

1221

icv

2

12

221

icv

2

1)1

2(2

2

icv

2c2

iR

mg

mg

R

o

mg

mg

Ro

ro

From ac equivalent circuit for common-mode inputs,

For differential-mode inputs, collector current was

Thus,id

v2

2c2

i mg

12212

21CMRR

1221

2

3

3

1221

2

Rm

gR

mg

cmAdm

A

Rm

gdm

A

rC

R

Ro

Rm

gC

Rm

g



Improving Op Amp Voltage GainOverall amplifier gain decreases rapidly as the quiescent current of second stage decreases. Voltage gain can improve if resistor in second stage is replaced by current source with R2 >> ro3, if R2 is neglected,

This expression can be reduced to

)33

)(3

(2

221 o

rm

grC

Rmg

vtA

vtA

dmA

2

3

3

281

3560

CIC

I

o

AV

dmA

332 or

orRoutR

Output resistance is degraded, amplifier more represents transconductance amplifier than a true low output

resistance voltage amplifier.



Reducing Output Resistance

A C-C stage is added to the prototype to maintain voltage gain but reduce output resistance.

From ac equivalent circuit,

1)1

4(

4

)14

(

3

)3

(32

)3

(2

21

LR

or

LR

ov

A

RCCino

rm

gv

A

rC

Rmg

vA

LRo

rRCCin )1

4(

4

22 rid

R

3

41

4

31

4

1

14

3

4

11

4

4

4

1

CIC

I

o

f

mg

o

or

mg

o

thR

mgoutR

3213

vov

2v

3v

idv

2v

vtA

vtA

vtA

dmA



Three-Stage Bipolar Op Amp Analysis• Problem: Find differential-mode gain, CMRR, input and output

resistances.

• Given data: VCC=VEE=15 V, o1 = o2 = o3 = o4 =100, VA3 =75V, I1 = 100 A, I2 = 500 A, I3 = 5 mA, R1 = 750 k , RL = 2 k, R2 and R3 are infinite.

• Analysis:

k55.4

S2102.240

A55011

mS98.1)(4040

m3g

o33

r

C3I

m3g

F4

3I

2I

F4

E4I

2IB4I

2I

C3I

E2I

F2C2I

m2g

Voltage at node 3 is one base-emitter voltage drop above zero. VEC3=15-0.7=14.3 V.



Three-Stage Bipolar Op Amp Analysis (contd.)

k9.15

5054

mA95.4

k162

F3C3

IC2

I

EB3V

CR

C4I

TV

o4r

E4IF4C4I

C3I

EC3V

A3V

3or

1998.0)1

4(

4

)14

(

3

1980))14

(4

(332

50.3)3

(2

21

LR

or

LR

ov

A

LR

or

or

mg

vA

rC

Rmg

vA

6920321

vtA

vtA

vtA

dmA

kΩ1012

2 ridR kΩ61.1

14

3

4

1

o

or

mgoutR

63.5dB1490

12CMRR R

mg

Overall gain is lower because of lower gain of first stage (since r3 << RC) and lower gain than expected for second stage (as reflected loading of RL is of same order as r3).



CMOS Op Amp Prototype: Circuit

• Differential amplifier (M1 and M2) followed by C-S stage M3 and source follower M4.

• Current sources are used to bias differential input and source follower stages and as load for M3.



CMOS Op Amp Prototype: AC Analysis

LR

mg

LR

mg

DRm

g

f

vtA

vtA

vtA

dmA

41

42

23

321

Since source follower has unity gain,

33

32

3

3

2

2

3

1

22

33

)1(21

TPV

pK

DI

DI

pK

DI

nK

TNV

GSV

GSV

fvtA

vtA

dmA

Design freedom is higher than in bipolar case due to Q-point dependence of f. Operating currents should be reduced and M3 should

have small to achieve higher gain. Input bias current doesn’t restrict ID1 as IG =0.

id

R

4

1

mgoutR

12CMRR R

mg



BiCMOS Amplifiers

• Integrated circuit processes that offer combination of bipolar and MOS transistors or bipolar transistors and JFETs are called BiCMOS and BiFET technologies respectively.

• Input PMOS transistors give high input resistance, can be biased at relatively high input currents, which can improve slew rate.

• Second gain stage uses BJT with superior amplification factor than FET.

• RE increases voltage across RD2 and hence the voltage gain of first stage without reducing amplification factor of Q1.

• Follower stage uses another FET to maximize second-stage gain while maintaining reasonable output resistance.



Op Amp Output Stages

• Output stage is designed to provide low output resistance and relatively high current drive capability.

• Followers: Class-A amplifiers- transistors conduct during full 3600 of signal waveform, conduction angle =3600.

• Push-pull: Class-B- each of the two transistors conducts during 1800of signal wavefrom, conduction angle =1800.

• Class-AB: Characteristics of Class-A and Class-B are combined, most commonly used as output stage in op amps.



Source-Follower: Class-A Output StageFor a source-follower,difference between input and output voltages is fixed and voltage transfer characteristic is as shown. If load resistor is connected to output, total source current:

vMIN = -ISS RL and iS=0, M1cuts off when vI = -ISS RL + VTN.

0L

Rov

SSI

Si

tDDVov sinIf output signal is given by:

Efficiency of amplifier is given by:

%252

2

2

DD

VSS

IL

RDD

V

avPacP

Low efficiency is due to current ISS that constantly flows between the two supplies.



Class-B Push-Pull Output StageImprove efficiency by operating transistors at zero Q-point current eliminating quiescent power dissipation. NMOS transistor is a source-follower for positive input signals and NMOS transistor is a source-follower for

negative input signals.

Since neither transistor conducts when,

output waveform suffers from a dead-zone or crossover distortion.

%5.782

2

2

2

LR

DDV

LR

DDV

avPacP

TNVGS

vTPV



Class-AB Amplifiers

Benefits of Class-B amplifier can be maintained without dead zone by biasing transistors into conduction but at a low quiescent current level (<< peak ac current delivered to load). For each transistor, 1800< conduction angle <3600.

The required bias voltage can be developed as shown.We assume that bias voltage splits equally between gate-source(or base-drain) terminals.

Currents are given by2

22

TNVGGV

nKDI

T

VB

RB

I

SI

CI

2exp



Class-AB Output Stages for Op Amps



Short-Circuit ProtectionHigh current, high power dissipation or direct destruction of base-emitter junction can destroy the BJT if output of a follower circuit is accidentally shorted to ground. Q2 is added to protect the emitter follower.Normally, voltage across R is <0.7 V, Q2 is cutoff. Q2

turns on to shunt extra current away from base of Q1. IE1 is limited to

For complementary output stage, similar current-limiting circuitry is used. In MOSFET complementary output stages, output current is limited to

RRBE

VE1

I /7.0/2

R

nK

GI

TNV

RGS

V

S1I 2

/222



Transformer Coupling: Follower

Transformer coupling is used in amplifiers to achieve high voltage gain and efficiency while delivering power to low impedance loads. Coupling capacitor blocks dc path through primary of transformer.

2v

1v n

1i

2i n LZnZ 2

1

Transformer provides impedance transformation by n2 . From ac equivalent circuit,transistor must drive

Transformer restricts operation to frequencies >dc.

LRnEQ

R 2

n1

vov



Transformer Coupling: Inverting Amplifier and Class-B Output Stage

At dc, transformer is a short circuit, quiescent operating current is supplied through transformer primary. At signal frequency load n2RL is presented to

transistor.

Inductance permits signal voltage to swing symmetrically above and below VDD.

As both quiescent operating currents = 0, emitters can be directly connected to transformer

primary.



Electronic Current Sources: Introduction

• Current through ideal current source is independent of voltage across its terminals and the output resistance is infinite.

• In electronic current sources, current depends on voltage across the terminals and they have a finite output resistance.

Current source

Current sink

Single-transistor current sources operate in only one quadrant of i-v space but realize very high output resistances.



Current Sources: Figure of Merit

is used as a figure of merit for comparing different current sources.

For a given Q-point current, VCS represents the equivalent voltage that will be needed across a resistor to achieve same output resistance as given current source.

For resistor:

For BJT:

For MOSFET:

outRoICSV

111

DSV

DI

DSV

DIorDIoutRoICSV

AV

CEV

AV

CI

CEV

AV

CIorC

IoutRoICSV

EEVRREE

VoutRoICS

V



Higher Output Resistance Sources

Output resistance of the current source can be increased by placing a resistor in series with the emitter or source of the transistor.

For BJT:

AVoCE

VA

VoCSV

AVoCE

VA

VoCSV

ERrRR

ERo

oroutR

)()(21

1

For MOSFET:

3

)1(

SSV

fCSV

SR

fSRmgoroutR



Multiple Output Current Sources

k39.3

21

21

V18.3

21

1

RR

RR

BBR

SSV

RR

R

BBV

k47.01

k7.41

k221

11

15)7.0(

321F

BV

BI

BI

BI

7.0 BVBEVBVEV

Assume equal current gains for all BJTs.

μA48422

μA103kΩ22

15

11

V7.127.012

V12)3390)(321

(18.315

BIFC

I

EV

FBIFC

I

EVB

IB

IB

IBV

mA84.433

BIFC

I



Multiple Output Current Sources (contd.)

Output resistances of the three current sources are given by:

kΩ1773

MΩ48.52

MΩ8.311

211

10017.72

211

1

outR

outR

outR

ER

rRRCI

ER

rRRo

oroutR



Bipolar Transistor Current Source Design Example• Problem: Design a current source with the largest possible output

voltage range that meets the given output resistance specification.

• Given data:VEE = 15 V, Io = 200 A, IEE < 250 A, Rout > 2 M, BJTs available with (o, VA) = (80, 100 V) and (150, 75 V), VB must be as low as possible.

• Assumptions: Active region and small-signal operating conditions. VBE = 0.7 V, VT = 0.025 V, choose Vo = 0 V as representative output value.

Analysis:

V2000)MΩ10)(μA200(

21

1

outRoIAVo

AVooutRoICS

V

oroE

RrRRE

RooroutR



Bipolar Transistor Current Source Design Example (contd.)Both BJTs can satisfy these conditions. But, we choose BJT (150, 75V) with higher oVA product.

Total current < 250 A. As output current is 200 A, maximum of 50 A can be used by base bias network. Current used by base bias network must be 5 to 10 times base current of BJT (1.33 A for BJT with a current gain of 150). So bias network current =20 A.

Large RBB reduces output resistance and output compliance range (increase VBB).Trading increased operating current for wider compliance range, choose bias network current of 40 A.

k375A40

V1521 RR



Bipolar Transistor Current Source Design Example (contd.)• Following set of equations can be used in a spreadsheet analysis

to determine design variables. Primary design variable is VBB which can be used to determine other variables.

F

oIBI

15

k37515

)21

(1

BBV

BBV

RRR 1k375

1)

21(

2RRRRR

21RRBBR

oIBB

RB

IBE

VBB

V

FER

)( BBRBIBEVBBVEEVCE

V

oIT

Vor

oI

CEV

AV

or

ERrRR

ERo

oroutR

21

1



Bipolar Transistor Current Source Design Example (contd.)• From spreadsheet, smallest VBB for which output resistance > 10M with

some safety margin is 4.5 V, resulting output resistance is 10.7M.• Analysis of circuit with 1% resistor values gives Io = 200 A and supply

current = 244 A.• Final current source design is as shown.

• MOSFET current source design can also be analyzed in similar manner.

Documents

Chapter 15 Multistage Amplifiers