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Digital Logic
Digital Logic
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BYU CS/ECEn 124Digital Logic*Success is not the key to
happiness.Happiness is the key to success.If you love what you are
doing, you will be successful.
Digital Logic
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BYU CS/ECEn 124Digital Logic*Topics to CoverThe
TransistorDevices: Inverter, NAND, NOR, DriversDe Morgans
LawTranslationsDecoders, Multiplexors, Adders, PLAsLogical
CompletenessSequential LogicLatchesMemoryFinite State Machine
Digital Logic
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BYU CS/ECEn 124Digital Logic*History of the TransistorAround
1945, Bell Labs scientists discovered that silicon was comprised of
two distinct regions differentiated by the way in which they
favored current flow.The area that favored positive current flow
they named "p" and the area that favored negative current flow they
named "n".The Transistor
Digital Logic
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BYU CS/ECEn 124Digital Logic*The Transistor EffectThe transistor
effect describes the change from a condition of conductivity
(switched on, full current flow) to a condition of insulation
(switched off, no current flow). The Transistor
Digital Logic
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BYU CS/ECEn 124Digital Logic*Digital Logic CircuitsComputers =
large number of simple structuresIntel 4004 = 2,300
transistorsIntel Pentium 4 = 42 million transistorsIntel Core 2 Duo
= 291 million transistorsIntel i7 Bloomfield = 731 million
transistors The Transistor
Digital Logic
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BYU CS/ECEn 124Digital Logic*Moores LawEarly
1900s19471950sMoores Law: The number of transistors per area
doubles every 1.5 - 2 years.1960s1970s1980s2000s1990sThe
Transistor
Digital Logic
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BYU CS/ECEn 124Digital Logic*The MOS TransistorA transistor acts
like a switchconducts current only when "on"MOS = metal-oxide
semiconductor CMOS = complementary MOS with both N and P
transistorscomplementaryOff = open circuitOn = closed circuitThe
Transistor
Digital Logic
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BYU CS/ECEn 124Digital Logic*N typeP typeGate = Ground = 0Field
Effect TransistorThe Transistor
Digital Logic
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BYU CS/ECEn 124Digital Logic*N typeP typeGate = Vcc = 1Field
Effect Transistor OperationThe Transistor
Digital Logic
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BYU CS/ECEn 124Digital Logic*CMOS GatesPullup StructurePulldown
StructureComplementaryWe want complementary pull-up and pull-down
logic: the pull-down is on when the pull-up is off, and
visa-versa.FThe C in CMOSEven in the digital world "EVERYTHING IS
ANALOG"! The Transistor
Digital Logic
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BYU CS/ECEn 124Digital Logic*The InverterDigital Logic
Devices
Digital Logic
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BYU CS/ECEn 124Digital Logic*The NOR Gate (NOT-OR)Digital Logic
Devices
Digital Logic
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BYU CS/ECEn 124Digital Logic*The OR GateHow do you build an OR
gate?Digital Logic Devices
Digital Logic
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BYU CS/ECEn 124Digital Logic*The NAND Gate
(NOT-AND)ba110NANDDigital Logic Devices
Digital Logic
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BYU CS/ECEn 124Digital Logic*The AND GateHow do you build an AND
gate?Digital Logic Devices
Digital Logic
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BYU CS/ECEn 124Digital Logic*Why Inverting Logic?Why cant we
useN transistors to pull up to Vcc, andP transistors to pull down
to ground? BecauseN transistors do not pass good voltage levels for
1sP transistors do not pass good voltage levels for 0sIt just
doesnt work electronically! SoOnly use P transistors in pull-up
structures!Only use N transistors in pull-down structures!
Digital Logic Devices
Digital Logic
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BYU CS/ECEn 124Digital Logic*DriversWhy cant we use CMOS
transistors to connect to a bus?P transistors to pull up to Vcc,
andN transistors to pull down to groundBecause connecting Vcc to
ground lets the magic smoke out!Solution: Tri-state driverDigital
Logic Devices
Digital Logic
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BYU CS/ECEn 124Digital Logic*De Morgans LawTo distribute the
bar, change the operation.NOR SymbolsNAND SymbolsDe Morgans Law
Digital Logic
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BYU CS/ECEn 124Digital Logic*De Morgans ProofDe Morgans Law
ABA + BA + BABA B
Digital Logic
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BYU CS/ECEn 124Digital Logic*Reading Functions from SymbolsThe
output will be low if all of the inputs are high...The output will
be high if any of the inputs are low...a b out0 0 10 1 11 0 11 1
0The output will be high if the first input is low ORthe second
input is high...Translations
Digital Logic
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BYU CS/ECEn 124Digital Logic*You Should Know How to
TranslateLogic EquationsLogic GatesTruth TablesThese are three
different ways of representing logical informationYou can convert
any one of them to any otherTranslations
Digital Logic
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BYU CS/ECEn 124Digital Logic*From Equations to Gatesy = NOT(s)
AND a AND NOT(b)Translations
Digital Logic
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BYU CS/ECEn 124Digital Logic*From Equations to Gatesy = (~s a
~b) + (~s a b)+ (s ~a b)+ (s a b)Translations
Digital Logic
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BYU CS/ECEn 124Digital Logic*From Truth tables to GatesEach row
of truth table is an AND gateEach output column is an OR gates a b
out0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1outWhen
we write s we meanthe inverse of s or s after it hasgone through an
inverter.sabsabsabsabTranslations
Digital Logic
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BYU CS/ECEn 124Digital Logic*From Truth table to EquationsWrite
out truth table a combination of ANDs and ORsequivalent to
gateseasily converted to gatess a b out0 0 0 00 0 1 00 1 0 10 1 1
11 0 0 01 0 1 11 1 0 01 1 1 1out =Translations
Digital Logic
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BYU CS/ECEn 124Digital Logic*From Equations to Truth TablesFor
each AND termfill in the proper row on the truth table
s a b out0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1
1s a b out0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1
1Translations
Digital Logic
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BYU CS/ECEn 124Digital Logic*Laws (basic identities) of Boolean
algebra. Manipulating Logic ExpressionsTranslations
LawORANDIdentityx 0 = xx 1 = xOne/Zerox 1 = 1x 0 = 0Idempotentx
x = xx x = xInversex x = 1x x = 0Commutativex y = y xx y = y
xAssociative(x y) z = x (y z)(x y) z = x (y z)Distributivex (y z) =
(x y) (x z)x (y z) = (x y) (x z)DeMorgans(x y) = x y(x y) = x y
Digital Logic
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Some Special Function Blocks
Digital Logic
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BYU CS/ECEn 124Digital Logic*DecodersDecode the input and
signify its value by raising just one of its outputs.1 if A,B = 001
if A,B = 011 if A,B = 101 if A,B = 11Circuits
Digital Logic
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BYU CS/ECEn 124Digital Logic*DecodersWrite the truth tableA B W
X Y Z0 0 0 1 1 0 1 1 1 0 0 00 1 0 00 0 1 00 0 0 1Circuits
Digital Logic
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BYU CS/ECEn 124Digital Logic*MultiplexorsConnect one of its
inputs to its output according to select signals
Useful for selecting one from a collection of data
inputs.Usually has 2n inputs and n select lines.Circuits
Digital Logic
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BYU CS/ECEn 124Digital Logic*MultiplexorsWrite the truth tableA
simpler wayA B S C
0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 11 0 1 01 1 0 11 1 1
1Circuits
Digital Logic
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BYU CS/ECEn 124Digital Logic*AddersAt each digit position add
together the 2 operands and the carry-inJust like longhand
additionexcept its in binary... c 0110+0101 1011Circuits
Digital Logic
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BYU CS/ECEn 124Digital Logic*Full Adder Module Designa b c cyout
sum0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01
1 1 1 1Circuits
Digital Logic
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BYU CS/ECEn 124Digital Logic*Logical CompletenessWhat is the
minimum set of gate types needed to implement any logic
function?AND gate, OR gate, INVERTERLogical Completeness
Digital Logic
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BYU CS/ECEn 124Digital Logic*Programmable Logic
ArraysProgrammable Logic Array (PLA) can be used to implement any
logic functionTake truth table of any logic functionConvert into
equation (any truth table can be expressed as set of and
expressions ored together)PLA programmed by making/breaking wire
connectionsInputs:Outputs:PLAs
Digital Logic
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BYU CS/ECEn 124Digital Logic*PLA ExampleOut2 = ABC + ABC +
ABCOut3 = ABC + ABCPLAs
Digital Logic
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BYU CS/ECEn 124Digital Logic*Logical CompletenessNAND
INVERTER AND ORNAND (by itself) is logically complete if you can
implement an INVERTER, AND, and OR gate using only NAND
gates.Logical Completeness
Digital Logic
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BYU CS/ECEn 124Digital Logic*Combinational vs. SequentialTwo
types of combination locksCombinationalSuccess depends only on the
values, not the order in which they are set.Sequential Logic
Digital Logic
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BYU CS/ECEn 124Digital Logic*Storage ElementsEverything so far
is called combinationalthe output is strictly a function of the
current inputsReal computing systems need storagefor holding
previously computed valuesfor remembering its place (state) in the
middle of a multi-step operationStorage elements remember what was
stored in them for later retrieval using feedbackSequential
Logic
Digital Logic
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BYU CS/ECEn 124Digital Logic*Bi-Stability = Key to Memory100When
there are 2 stable states - a bi-stable circuitSequential Logic
Digital Logic
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BYU CS/ECEn 124Digital Logic*Signals s and r are active lowthey
change the circuit when they go low
Output q goes high when s goes lowOutput q goes low when r goes
lowOutput q remains the same otherwisesrqqRS
LatchqqsrsameqqsrsameCross-coupled NAND gatesNote the
feedbackSequential Logic
Digital Logic
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BYU CS/ECEn 124Digital Logic*RS Latch Bi-Stable
Circuitqqsrqqsr11101011This is a stable state it will sit like this
foreverThis is also a stable state it will sit like this
foreverSequential Logic
Digital Logic
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BYU CS/ECEn 124Digital Logic*RS Latch
(continued)11qqsrSequential Logic
Digital Logic
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BYU CS/ECEn 124Digital Logic*RS Latch : Next State TableDefines
output as a function of inputs (s and r) and current output (q, its
state)s r q qnext0 0 0 x0 0 1 x0 1 0 10 1 1 11 0 0 01 0 1 01 1 0 q1
1 1 qnot allowedsetresetkeep old stateSequential Logic
Digital Logic
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BYU CS/ECEn 124Digital Logic*Gated D LatchOutput q gets value
from input d only when we is highwe stands for write enable, think
of it as a load signalLATCH SymbolSymbols are
abstractions!Latch
Digital Logic
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BYU CS/ECEn 124Digital Logic*Quiz1.What is a bi-stable
circuit?2.Draw a logic circuit (using N and P type transistors) for
a 3 input NAND gate.3.With a RS NAND latch, why cant R and S be low
at the same time?4.How is Q set with the following latch?
Digital Logic
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BYU CS/ECEn 124Digital Logic*Quiz (Answers)1.What is a bi-stable
circuit?When the circuit has 2 stable states 2.Draw a logic circuit
(using N and P type transistors) for a 3 input NAND gate.
Digital Logic
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BYU CS/ECEn 124Digital Logic*Quiz (Answers)3.With a RS NAND
latch, why cant R and S be low at the same time?This state would
force both outputs to a logic 1, overriding the feedback latching
action.Outputs Q and Q' must have opposite logic levels.Results in
a race condition final state of the latch cannot be determined.
Digital Logic
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BYU CS/ECEn 124Digital Logic*Quiz (Answers)4.How is Q set with
the following latch?Q is set by changing input S from a logic 0 to
a logic 100
Digital Logic
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BYU CS/ECEn 124Digital Logic*RegisterA computer register is a
place to store a collection of bits
Very fast memoryNumbered right to left (LSB on the
right)D-Latchd0q0D-Latchd1q1D-Latchd2q2D-Latchd3q3weREGISTER
SymbolRegisterdqweLatch
Digital Logic
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BYU CS/ECEn 124Digital Logic*MemoryA collection of addressable
locationsAddress selects which location to read from or write toA
memory with n address wires has 2n locations.
The number of data wires in equal the number of data wires
out.
Memory is changed with we is asserted.
q always reflects the contents stored at the addressed memory
location.
Memory can be viewed as a large collection of slower
registers.Memory
Digital Logic
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BYU CS/ECEn 124Digital Logic*Memory Usageaddr value000 1001001
0000010 1111011 1011100 0000101 0011110 1010111 0101Power-Up State
(random bits)addr => 101data => 0000we => 1addr value000
1001001 0000010 1111011 1011100 0000101 0000110 1010111 0101addr
=> 101data => 0000we => 0addr value000 1001001 0000010
1111011 1011100 0000101 0000110 1010111 0101addr => 111data
=> 1100we => 1addr value000 1001001 0000010 1111011 1011100
0000101 0000110 1010111 1100addr => 000data => 0000we =>
1addr value000 0000001 0000010 1111011 1011100 0000101 0000110
1010111 1100addr => 000data => 0110we => 1addr value000
0110001 0000010 1111011 1011100 0000101 0000110 1010111 1100addr
=> 110data => 0110we => 0addr value000 0110001 0000010
1111011 1011100 0000101 0000110 1010111 1100Memory
Digital Logic
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BYU CS/ECEn 124Digital Logic*Building a Memory From
Latches2-to-4Decodera1a000011011RegisterRegisterRegisterRegisterwewewewewriteEnabled
inputq outputThis is a functional view.The key parts are: address
decoder memory cells (registers) output selector (mux)MEMORY
Symboln = 2addressq0q1q2q3Memory
Digital Logic
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BYU CS/ECEn 124Digital Logic*Address SpaceWhen we say a computer
has a 4GB (giga-byte) address space we meanit has enough address
lines to address 232 address locationsKilobyte= 210 or 10241
bytesMegabyte= 220 or 10242 bytesGigabyte= 230 or 10243
bytesTera-byte= 240 or 10244 bytesPeta-byte= 250 or 10245
bytesMemory
Digital Logic
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BYU CS/ECEn 124Digital Logic*A 12-Bit Memory4 words, each 3 bits
wideWord line 00Word line 01Word line 10Word line 11LatchOnly one
word line is high at any given time.Memory
Digital Logic
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BYU CS/ECEn 124Digital Logic*Reading A 12-Bit MemoryEach column
forms a sort of multiplexorOnly one of the AND gates in the column
will be enabled. Thus, they allow one row out of 4 to be selected
for reading.Memory
Digital Logic
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BYU CS/ECEn 124Digital Logic*Writing A 12-Bit Memory4 words,
each 3 bits wideWrite line 00Write line 01Write line 10Write line
11LatchDepending on state of we signal, zero or one write lines
will be high at any given time.Write enable signal and write enable
AND gatesMemory
Digital Logic
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BYU CS/ECEn 124Digital Logic*The MSP430You may not know how it
works, but you know the parts its made from!MemoryProgram
CounterStatus RegisterLots of GatesInstruction
RegisterMultiplexorArithmetic Logic UnitRegister16
16-bitRegistersMemoryMapped I/OBus DriverFinite State Machine
Digital Logic
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START HEREBYU CS/ECEn 124Digital Logic*
Digital Logic
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BYU CS/ECEn 124Digital Logic*Sequential State MachineAnother
type of sequential circuitCombines combinational logic with
storageRemembers state, and changes output (and state) based on
inputs and current state
State MachineCombinationalLogic
CircuitStorageElementsInputsOutputsFinite State Machine
Digital Logic
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BYU CS/ECEn 124Digital Logic*State of a SystemThe state of a
system is a snapshot of all the relevant elements of the system at
the moment the snapshot is taken.Examples:The state of a basketball
game can be represented by the scoreboard (ie. number of points,
time remaining, possession, etc.)The state of a tic-tac-toe game
can be represented by the placement of Xs and Os on the
board.Finite State Machine
Digital Logic
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BYU CS/ECEn 124Digital Logic*Combinational vs. SequentialTwo
types of combination locksCombinationalSuccess depends only on the
values, not the order in which they are set.SequentialSuccess
depends on the sequence of values(e.g, R-13, L-22, R-3).Finite
State Machine
Digital Logic
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BYU CS/ECEn 124Digital Logic*State of Sequential LockOur lock
example has four different states, labeled A-D:A:The lock is not
open, and no relevant operations have been performed.B:The lock is
not open, and the user has completed the R-13 operation.C:The lock
is not open, and the user has completed R-13, followed by
L-22.D:The lock is open.Finite State Machine
Digital Logic
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BYU CS/ECEn 124Digital Logic*State DiagramShows states and
actions that cause a transition between states.Open = 0Open = 0Open
= 0Open = 1Finite State Machine
Digital Logic
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BYU CS/ECEn 124Digital Logic*Finite State MachineA description
of a system with the following components:A finite number of
statesA finite number of external inputsA finite number of external
outputsAn explicit specification of all state transitionsAn
explicit specification of what determines each external output
valueOften described by a state diagram.Inputs trigger state
transitions.Outputs are associated with each state (or with each
transition).Finite State Machine
Digital Logic
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BYU CS/ECEn 124Digital Logic*The ClockFrequently, a clock
circuit triggers transition from one state to the next.
At the beginning of each clock cycle, state machine makes a
transition, based on the current state and the external (or
internal) inputs.Finite State Machine
Digital Logic
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BYU CS/ECEn 124Digital Logic*FSM ImplementationCombinational
logicDetermine outputs and next state.Storage elementsMaintains
state representation.State MachineCombinationalLogic
CircuitStorageElementsInputsOutputsClockFinite State Machine
Digital Logic
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BYU CS/ECEn 124Digital Logic*Storage: Master-Slave FlipflopA
pair of gated D-latches isolates next state from current
state.During 1st phase (clock=1), previously-computed state becomes
current state and is sent to the logic circuit.During 2nd phase
(clock=0), next state, computed by logic circuit, is stored in
Latch A.Finite State Machine
Digital Logic
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Storage: Master-Slave FlipflopBYU CS/ECEn 124Digital
Logic*Finite State MachineHOLDSET/RESET
Digital Logic
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Storage: Master-Slave FlipflopBYU CS/ECEn 124Digital
Logic*Finite State MachineHOLDSET/RESET
Digital Logic
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Another viewBYU CS/ECEn 124Digital Logic*Combinational
LogicMasterSlaveInputLOW
Digital Logic
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Another viewBYU CS/ECEn 124Digital Logic*Combinational
LogicMasterSlaveInputLOW
Digital Logic
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Another viewBYU CS/ECEn 124Digital Logic*Combinational
LogicMasterSlaveInputHIGH
Digital Logic
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Another viewBYU CS/ECEn 124Digital Logic*Combinational
LogicMasterSlaveInputHIGH
Digital Logic
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Another viewBYU CS/ECEn 124Digital Logic*Combinational
LogicMasterSlaveInputHIGH
Digital Logic
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Another viewBYU CS/ECEn 124Digital Logic*Combinational
LogicMasterSlaveInputLOW
Digital Logic
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Another viewBYU CS/ECEn 124Digital Logic*Combinational
LogicMasterSlaveInputLOW
Digital Logic
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BYU CS/ECEn 124Digital Logic*Storage ElementsEach master-slave
flip flop stores one state bit.The number of storage elements (flip
flops) needed is determined by the number of states (and the
representation of each state).Examples:Sequential lock4 states 2
bitsBasketball scoreboard7 bits for each score, 5 bits for minutes,
6 bits for seconds, 1 bit for possession arrow, 1 bit for half,
Blinking traffic sign4 states 2 bitsFinite State Machine
Digital Logic
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BYU CS/ECEn 124Digital Logic*A blinking traffic signNo lights
on1 & 2 on1, 2, 3, & 4 on1, 2, 3, 4, & 5 onRepeat as
long as switch is turned onDANGER MOVE RIGHT12345Finite State
Machine ExampleFinite State Machine
Digital Logic
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BYU CS/ECEn 124Digital Logic*Traffic Sign State DiagramState bit
S1State bit S0Switch onSwitch offOutputsTransition on each clock
cycle.Finite State Machine
Digital Logic
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BYU CS/ECEn 124Digital Logic*Traffic Sign Truth
TablesOutputs(depend only on state: S1S0)Lights 1 and 2Lights 3 and
4Light 5Next State: S1'S0' (depend on state and
input)SwitchWhenever In=0, next state is 00.Finite State
Machine
S1S0ZYX00000011001011011111
InS1S0S1'S0'0XX0010001101101101111100
Digital Logic
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BYU CS/ECEn 124Digital Logic*Traffic Sign LogicFinite State
Machine
Digital Logic
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BYU CS/ECEn 124Digital Logic*From Logic to Data PathThe data
path of a computer is all the logic used to process information.See
the data path of the LC-3 on next slide.Combinational LogicDecoders
-- convert instructions into control signalsMultiplexers -- select
inputs and outputsALU (Arithmetic and Logic Unit) -- operations on
dataSequential LogicState machine -- coordinate control signals and
data movementRegisters and latches -- storage elementsFinite State
Machine
Digital Logic
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STOP HEREBYU CS/ECEn 124Digital Logic*
Digital Logic
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BYU CS/ECEn 124Digital Logic*MSP430 Finite State
MachineDECODE:NOCLK:MOV||EVSRCEVDST:CLK1:MOV,Rd|D,ROX=Rd|STOREEVSRC:CLK1:MOV,Rs|S,ROX=Rs|EVDSTSTORE:CLK1:MOV,Rd|ALU,RWE,RIX=Rd|FETCH...Finite
State Machine
Digital Logic
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BYU CS/ECEn 124Digital Logic*
Digital Logic
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Review
Digital Logic
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BYU CS/ECEn 124Digital Logic*Signals, Logic Operators, Gates
Digital Logic
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BYU CS/ECEn 124Digital Logic*Variations in Gate SymbolsGates
with more than two inputs and/or with inverted signals at input or
output.
Digital Logic
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BYU CS/ECEn 124Digital Logic*Gates as Control ElementsAn AND
gate and a tristate buffer act as controlled switches or valves. An
inverting buffer is logically the same as a NOT gate.
Digital Logic
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BYU CS/ECEn 124Digital Logic*Wired OR and Bus ConnectionsWired
OR allows tying together of several controlled signals.
Digital Logic
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BYU CS/ECEn 124Digital Logic*Boolean Functions / ExpressionsWays
of specifying a logic function
Truth table: 2n row, dont-care in input or output
Logic expression: w (x y z), product-of-sums, sum-of-products,
equivalent expressions
Word statement: Alarm will sound if the door is opened while the
security system is engaged, or when the smoke detector is
triggered
Logic circuit diagram: Synthesis vs analysis
Digital Logic
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BYU CS/ECEn 124Digital Logic*Laws (basic identities) of Boolean
algebra. Manipulating Logic Expressions
Name of lawOR versionAND versionIdentityx 0 = xx 1 = xOne/Zerox
1 = 1x 0 = 0Idempotentx x = xx x = xInversex x = 1x x =
0Commutativex y = y xx y = y xAssociative(x y) z = x (y z)(x y) z =
x (y z)Distributivex (y z) = (x y) (x z)x (y z) = (x y) (x
z)DeMorgans(x y) = x y (x y) = x y
Digital Logic
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BYU CS/ECEn 124Digital Logic*Designing Gate Networks
AND-OR, NAND-NAND, OR-AND, NOR-NOR
Logic optimization: cost, speed, power dissipation
A two-level AND-OR circuit and two equivalent circuits.
Digital Logic
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BYU CS/ECEn 124Digital Logic*BCD-to-Seven-Segment DecoderThe
logic circuit that generates the enable signal for the lowermost
segment (number 3) in a seven-segment display unit.
Digital Logic
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BYU CS/ECEn 124Digital Logic*Useful Combinational Parts
High-level building blocks
Much like prefab parts used in building a house
Arithmetic components will be covered in Part III (adders,
multipliers, ALUs)
Here we cover three useful parts: multiplexers,
decoders/demultiplexers, encoders
Digital Logic
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BYU CS/ECEn 124Digital Logic*MultiplexersMultiplexer (mux), or
selector, allows one of several inputs to be selected and routed to
output depending on the binary value of a set of selection or
address signals provided to it.
Digital Logic
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BYU CS/ECEn 124Digital Logic*Decoders/DemultiplexersA decoder
allows the selection of one of 2a options using an a-bit address as
input. A demultiplexer (demux) is a decoder that only selects an
output if its enable signal is asserted.
Digital Logic
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BYU CS/ECEn 124Digital Logic*EncodersA 2a-to-a encoder outputs
an a-bit binary number equal to the index of the single 1 among its
2a inputs.
Digital Logic
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BYU CS/ECEn 124Digital Logic*Programmable Combinational
Parts
Programmable ROM (PROM)
Programmable array logic (PAL)
Programmable logic array (PLA)
A programmable combinational part can do the job of many gates
or gate networksProgrammed by cutting existing connections (fuses)
or establishing new connections (antifuses)
Digital Logic
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BYU CS/ECEn 124Digital Logic*PROMsProgrammable connections and
their use in a PROM.
Digital Logic
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BYU CS/ECEn 124Digital Logic*PALs and PLAsProgrammable
combinational logic: general structure and two classes known as PAL
and PLA devices. Not shown is PROM with fixed AND array (a decoder)
and programmable OR array.
Digital Logic
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BYU CS/ECEn 124Digital Logic*Latches, Flip-Flops, and
RegistersLatches, flip-flops, and registers.
Digital Logic
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BYU CS/ECEn 124Digital Logic*Latches vs Flip-FlopsOperations of
D latch and negative-edge-triggered D flip-flop.
Digital Logic
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BYU CS/ECEn 124Digital Logic*R/W FFs in the Same
CycleRegister-to-register operation with edge-triggered
flip-flops.
Digital Logic
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BYU CS/ECEn 124Digital Logic*Finite-State MachinesState table
and state diagram for a vending machine coin reception unit.
Digital Logic
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BYU CS/ECEn 124Digital Logic*Register File and FIFORegister file
with random access and FIFO.
Digital Logic
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BYU CS/ECEn 124Digital Logic*SRAMSRAM memory is simply a large,
single-port register file.
Digital Logic
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BYU CS/ECEn 124Digital Logic*Programmable Sequential Parts
Programmable array logic (PAL)
Field-programmable gate array (FPGA)
Both types contain macrocells and interconnects
A programmable sequential part contain gates and memory
elementsProgrammed by cutting existing connections (fuses) or
establishing new connections (antifuses)
Digital Logic
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BYU CS/ECEn 124Digital Logic*From Components to
ApplicationsSubfields or views in computer system engineering.
Digital Logic
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BYU CS/ECEn 124Digital Logic*High- vs Low-Level Programming
Digital Logic
Paul Roper*Paul RoperPaul Roper*Paul RoperPaul Roper*Paul
RoperPaul Roper*Paul RoperPaul Roper*Paul RoperPaul Roper*Paul
Roper0 is the controllling value on a NAND
Low clock is the hold for the latchHigh clock will set or reset
depending on input (11 is set and 10 is reset)
Key:
Clock high: A holds in the high phase and B either sets or
resets (A ignores input)Clock low: B holds in the low phase and A
either sets or resetsPaul Roper*Paul Roper0 is the controllling
value on a NAND
Low clock is the hold for the latchHigh clock will set or reset
depending on input (11 is set and 10 is reset)
Key:
Clock high: A holds in the high phase and B either sets or
resets (A ignores input)Clock low: B holds in the low phase and A
either sets or resetsPaul Roper*Paul Roper0 is the controllling
value on a NAND
Low clock is the hold for the latchHigh clock will set or reset
depending on input (11 is set and 10 is reset)
Key:
Clock high: A holds in the high phase and B either sets or
resets (A ignores input)Clock low: B holds in the low phase and A
either sets or resetsPaul Roper*Paul RoperPaul Roper*Paul Roper
