Chapter 10:Chapter 10:Input / Output DevicesInput / Output Devices

Dr Mohamed MenacerDr Mohamed MenacerTaibah UniversityTaibah University

2007-20082007-2008

Input/Output ProblemsInput/Output Problems

Wide variety of peripheralsWide variety of peripherals Delivering different amounts of dataDelivering different amounts of data At different speedsAt different speeds In different formatsIn different formats

All slower than CPU and RAMAll slower than CPU and RAM

Need I/O modulesNeed I/O modules

Input/Output ModuleInput/Output Module

Interface to CPU and MemoryInterface to CPU and Memory

Interface to one or more peripheralsInterface to one or more peripherals

Generic Model of I/O ModuleGeneric Model of I/O Module

External DevicesExternal Devices

Human readableHuman readable Screen, printer, keyboardScreen, printer, keyboard

Machine readableMachine readable Monitoring and controlMonitoring and control

CommunicationCommunication ModemModem Network Interface Card (NIC)Network Interface Card (NIC)

External Device Block DiagramExternal Device Block Diagram

I/O Module FunctionI/O Module Function

Control & TimingControl & Timing

CPU CommunicationCPU Communication

Device CommunicationDevice Communication

Data BufferingData Buffering

Error DetectionError Detection

I/O StepsI/O Steps

CPU checks I/O module device statusCPU checks I/O module device status

I/O module returns statusI/O module returns status

If ready, CPU requests data transferIf ready, CPU requests data transfer

I/O module gets data from deviceI/O module gets data from device

I/O module transfers data to CPUI/O module transfers data to CPU

Variations for output, DMA, etc.Variations for output, DMA, etc.

I/O Module DiagramI/O Module Diagram

I/O Module DecisionsI/O Module Decisions

Hide or reveal device properties to CPUHide or reveal device properties to CPU

Support multiple or single deviceSupport multiple or single device

Control device functions or leave for CPUControl device functions or leave for CPU

Also O/S decisionsAlso O/S decisions e.g. Unix treats everything it can as a filee.g. Unix treats everything it can as a file

Intel 82C55A Intel 82C55A Programmable Peripheral InterfaceProgrammable Peripheral Interface

Keyboard/Display Interfaces to 82C55AKeyboard/Display Interfaces to 82C55A

Input Output TechniquesInput Output Techniques

ProgrammedProgrammed

Interrupt drivenInterrupt driven

Direct Memory Access (DMA)Direct Memory Access (DMA)

Three Techniques for Input of a Block of DataThree Techniques for Input of a Block of Data

Programmed I/OProgrammed I/O

CPU has direct control over I/OCPU has direct control over I/O Sensing statusSensing status Read/write commandsRead/write commands Transferring dataTransferring data

CPU waits for I/O module to complete CPU waits for I/O module to complete operationoperation

Wastes CPU timeWastes CPU time

Programmed I/O - detailProgrammed I/O - detail

CPU requests I/O operationCPU requests I/O operation

I/O module performs operationI/O module performs operation

I/O module sets status bitsI/O module sets status bits

CPU checks status bits periodicallyCPU checks status bits periodically

I/O module does not inform CPU directlyI/O module does not inform CPU directly

I/O module does not interrupt CPUI/O module does not interrupt CPU

CPU may wait or come back laterCPU may wait or come back later

I/O CommandsI/O Commands

CPU issues addressCPU issues address Identifies module (& device if >1 per module)Identifies module (& device if >1 per module)

CPU issues commandCPU issues command Control - telling module what to doControl - telling module what to do

e.g. spin up diske.g. spin up disk Test - check statusTest - check status

e.g. power? Error?e.g. power? Error? Read/WriteRead/Write

Module transfers data via buffer from/to deviceModule transfers data via buffer from/to device

Addressing I/O DevicesAddressing I/O Devices

Under programmed I/O data transfer is Under programmed I/O data transfer is very like memory access (CPU viewpoint)very like memory access (CPU viewpoint)

Each device given unique identifierEach device given unique identifier

CPU commands contain identifier CPU commands contain identifier (address)(address)

I/O MappingI/O Mapping

Memory mapped I/OMemory mapped I/O Devices and memory share an address spaceDevices and memory share an address space I/O looks just like memory read/writeI/O looks just like memory read/write No special commands for I/ONo special commands for I/O

Large selection of memory access commands availableLarge selection of memory access commands available

Isolated I/OIsolated I/O Separate address spacesSeparate address spaces Need I/O or memory select linesNeed I/O or memory select lines Special commands for I/OSpecial commands for I/O

Limited setLimited set

Memory Mapped and Isolated I/OMemory Mapped and Isolated I/O

Interrupt Driven I/OInterrupt Driven I/O

Overcomes CPU waitingOvercomes CPU waiting

No repeated CPU checking of deviceNo repeated CPU checking of device

I/O module interrupts when readyI/O module interrupts when ready

Interrupt Driven I/OInterrupt Driven I/OBasic OperationBasic Operation

CPU issues read commandCPU issues read command

I/O module gets data from peripheral I/O module gets data from peripheral whilst CPU does other workwhilst CPU does other work

I/O module interrupts CPUI/O module interrupts CPU

CPU requests dataCPU requests data

I/O module transfers dataI/O module transfers data

Simple Simple InterruptInterrupt

ProcessingProcessing

CPU ViewpointCPU Viewpoint

Issue read commandIssue read command

Do other workDo other work

Check for interrupt at end of each Check for interrupt at end of each instruction cycleinstruction cycle

If interrupted:-If interrupted:- Save context (registers)Save context (registers) Process interruptProcess interrupt

Fetch data & storeFetch data & store

Changes in Memory and Registers for an Changes in Memory and Registers for an InterruptInterrupt

Example - PC BusExample - PC Bus

80x86 has one interrupt line80x86 has one interrupt line

8086 based systems use one 8259A 8086 based systems use one 8259A interrupt controllerinterrupt controller

8259A has 8 interrupt lines8259A has 8 interrupt lines

82C59A Interrupt82C59A InterruptControllerController

Sequence of EventsSequence of Events

8259A accepts interrupts8259A accepts interrupts

8259A determines priority8259A determines priority

8259A signals 8086 (raises INTR line)8259A signals 8086 (raises INTR line)

CPU AcknowledgesCPU Acknowledges

8259A puts correct vector on data bus8259A puts correct vector on data bus

CPU processes interruptCPU processes interrupt

Multiple InterruptsMultiple Interrupts

Each interrupt line has a priorityEach interrupt line has a priority

Higher priority lines can interrupt lower Higher priority lines can interrupt lower priority linespriority lines

If bus mastering only current master can If bus mastering only current master can interruptinterrupt

ISA Bus Interrupt SystemISA Bus Interrupt System

ISA bus chains two 8259As togetherISA bus chains two 8259As together

Link is via interrupt 2Link is via interrupt 2

Gives 15 linesGives 15 lines 16 lines less one for link16 lines less one for link

IRQ 9 is used to re-route anything trying to IRQ 9 is used to re-route anything trying to use IRQ 2use IRQ 2 Backwards compatibilityBackwards compatibility

Incorporated in chip setIncorporated in chip set

Multiple Multiple Interrupts Interrupts

using using 82C59A 82C59A InterruptInterrupt

ControllerController

Direct Memory Access (DMA)Direct Memory Access (DMA)

Interrupt driven and programmed I/O Interrupt driven and programmed I/O require active CPU interventionrequire active CPU intervention Transfer rate is limitedTransfer rate is limited CPU is tied upCPU is tied up

DMA is the answerDMA is the answer

DMA FunctionDMA Function

Additional Module (hardware) on busAdditional Module (hardware) on bus

DMA controller takes over from CPU for DMA controller takes over from CPU for I/OI/O

Typical DMA Module DiagramTypical DMA Module Diagram

DMA OperationDMA OperationCPU tells DMA controller:-CPU tells DMA controller:- Read/WriteRead/Write Device addressDevice address Starting address of memory block for dataStarting address of memory block for data Amount of data to be transferredAmount of data to be transferred

CPU carries on with other work (not an interrupt)CPU carries on with other work (not an interrupt)

DMA controller deals with transfer (DMA DMA controller deals with transfer (DMA controller takes over bus for a cycle)controller takes over bus for a cycle)

DMA controller sends interrupt when finishedDMA controller sends interrupt when finished

Slows down CPU but not as much as CPU doing Slows down CPU but not as much as CPU doing transfertransfer

DMA and Interrupt Breakpoints DMA and Interrupt Breakpoints During an Instruction CycleDuring an Instruction Cycle

DMA Configurations (1)DMA Configurations (1)

Single Bus, Detached DMA controllerSingle Bus, Detached DMA controller

Each transfer uses bus twiceEach transfer uses bus twice I/O to DMA then DMA to memoryI/O to DMA then DMA to memory

CPU is suspended twiceCPU is suspended twice

DMA Configurations (2)DMA Configurations (2)

Single Bus, Integrated DMA controllerSingle Bus, Integrated DMA controller

Controller may support >1 deviceController may support >1 device

Each transfer uses bus onceEach transfer uses bus once DMA to memoryDMA to memory

CPU is suspended onceCPU is suspended once

DMA Configurations (3)DMA Configurations (3)

Separate I/O BusSeparate I/O Bus

Bus supports all DMA enabled devicesBus supports all DMA enabled devices

Each transfer uses bus onceEach transfer uses bus once DMA to memoryDMA to memory

CPU is suspended onceCPU is suspended once

Intel 8237A DMA ControllerIntel 8237A DMA ControllerInterfaces to 80x86 family and DRAMInterfaces to 80x86 family and DRAMWhen DMA module needs buses it sends HOLD signal to When DMA module needs buses it sends HOLD signal to processorprocessorCPU responds HLDA (hold acknowledge) CPU responds HLDA (hold acknowledge) DMA module can use busesDMA module can use buses

E.g. transfer data from memory to diskE.g. transfer data from memory to disk1.1. Device requests service of DMA by pulling DREQ (DMA request) Device requests service of DMA by pulling DREQ (DMA request)

highhigh2.2. DMA puts high on HRQ (hold request), DMA puts high on HRQ (hold request), 3.3. CPU finishes present bus cycle (not necessarily present CPU finishes present bus cycle (not necessarily present

instruction) and puts high on HDLA (hold acknowledge). HOLD instruction) and puts high on HDLA (hold acknowledge). HOLD remains active for duration of DMAremains active for duration of DMA

4.4. DMA activates DACK (DMA acknowledge), telling device to start DMA activates DACK (DMA acknowledge), telling device to start transfertransfer

5.5. DMA starts transfer by putting address of first byte on address DMA starts transfer by putting address of first byte on address bus and activating MEMR; it then activates IOW to write to bus and activating MEMR; it then activates IOW to write to peripheral. DMA decrements counter and increments address peripheral. DMA decrements counter and increments address pointer. Repeat until count reaches zeropointer. Repeat until count reaches zero

6.6. DMA deactivates HRQ, giving bus back to CPUDMA deactivates HRQ, giving bus back to CPU

8237 DMA Usage of Systems Bus8237 DMA Usage of Systems Bus

Conclusion: I/O ChannelsConclusion: I/O Channels

I/O devices getting more sophisticatedI/O devices getting more sophisticated

e.g. 3D graphics cardse.g. 3D graphics cards

CPU instructs I/O controller to do transferCPU instructs I/O controller to do transfer

I/O controller does entire transferI/O controller does entire transfer

Improves speedImproves speed Takes load off CPUTakes load off CPU Dedicated processor is fasterDedicated processor is faster