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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 1

Chapter 5Chapter 5

SIP Test ArchitecturesSIP Test Architectures

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 2

What is this chapter about?What is this chapter about?

� Introduce fundamental concepts and various aspects of SIP testing

� Focus on� Specific challenges from the testing point of view

� Known-Good-Die � Solutions for testing a SIP at system level

� Test and access of embedded dies

� Provide overview of SIP assembly and test technology

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 3

SIP Test ArchitecturesSIP Test Architectures� Introduction

� Definition

� SIP examples

� Yield and quality challenges

� Test Strategy

� Bare Die Test� Mechanical probing techniques

� Electrical probing techniques

� Reliability screens

� Functional system test� Path-based testing

� Loopback techniques: DFT and DSP

� Test of Embedded Components� SIP TAP

� Interconnections

� Digital logic and memories

� Analog and RF Components

� MEMS

� Concluding Remarks

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 4

System-in-package (SIP) = any combination of

semiconductors, passives, and interconnects

integrated into a single package

SIP (System-in-Package) is a functional system

or subsystem assembled into a single package

What is an SIP?What is an SIP?

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 5

SIP vs. SIP vs. SoCSoC� SIP is a single package that includes one or more Integrated Circuits and/or

passive devices with multiple interconnections. It provides the option of

combining multiple technologies to form a complete (sub-)system

� SoC is a single Integrated Circuit connected inside a single package

dedicated to a specific application

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 6

SelectionSelection options: SIP vs. options: SIP vs. SoCSoC

Time to Market

Short Long

Production Volume

Low High

Performance /Speed

Low

High

TechnicalMix

Complex

Simple

Favor the useof SoC.

Favor the useof SIP.

Consider FactorsCarefully.

Consider FactorsCarefully.

Factors to Consider:

� Production Volume

� Design & Market Environment

� NRE (Incl. IP Cost)

� Reliability� Die Maturity

� Technologies (RF, Memories…)

Source: Gartner 2006

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 7

SIP vs. SIP vs. SoCSoC: so what?: so what?

SIP and SoC are not competitors,

but partners!

RF FERF TRx

Base-bandMemory

BlueToothTM

PMU

MP3DSCTVoMGPSNFC

RF FERF TRx

Base-bandMemory

BlueToothTMMP3

PMU

DSCTVoMGPSNFC

RF FERF TRx

Base-bandMemory

BlueToothTMMP3

PMU

DSCTVoMGPSNFC

e-CompassWii-like

Health monitor

SIP SoC

SIP

A cell phone…

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 8

CircuitFunctions

ProcessTechno.

Suppliers

Source

Decoder

Tuner

Channel Decoder

QualityLevels

SupplyVoltages

SignalFrequenci

es

SignalLevels

Failure mod./mec

h.

SIP vs. SIP vs. SoCSoCCompared to an SOC, an SIP may have more…Compared to an SOC, an SIP may have more…

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 9

Integratio

n Trend

Passive/Interconnect die

Active Die

SMDs / Components

Discretes SolutionsPCB

MCM SolutionsPCB

Laminate + SMDs SolutionsPCB

Laminate + SMDs + Passive diePCB

Double Flip Chip assemblyPCB

Wafer Level PackagingPCB

SIP PlatformsSIP Platforms

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 10

Leading Applications for SIPs

• Applications include portable consumer products such as

digital camcorders and cameras

• Mobile phone is the volume driver

– Logic and memory combo

– Digital baseband section

– Transceiver section

– RF section

SIP examplesSIP examples

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 11

This device is a credit-card sized digital

camera with audio recording functions,

an integrated MP3 player, 12MB of

internal storage, and an SD or MMC card

slot. Its thickness dimension is only 13.5

mm.

Source:Portelligent

SIP examplesSIP examples

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 12

SIPs show up in portable devices

SIP examplesSIP examples

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 13

SIP examplesSIP examples

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 14

Motorola E1000 UMTS (3G)

SIP examplesSIP examples

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 15

Bluetooth

Radio

SIP examplesSIP examples

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 16

SIP examplesSIP examples

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 17

UAA3587 GSM multiband transceiver

Transceiver die

900 MHz balun

1800 MHz balun Capacitors, PLL filter

5.7mm square, incl.saw line

SIP examplesSIP examples

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 18

Yield and Quality ChallengesYield and Quality Challenges

Die Fabrication

Fci Fdi

Fi

Die Test

Si/Ge/GaAs/...

Fcigo Fdi

go Fcinogo Fdi

nogo

Figo Fi

nogo

go go nogo nogoST

EP

#1: D

ie p

rocess

Die #i

Fc1go Fd1

go

F1go

SiP Assembly

Ac Ad

A

SiP Test

go go nogo nogo

ST

EP

#2: S

iPp

rocess

Fcngo Fdn

go

Fngo

Die #1 Die # n

…..

Carrierprocess

Acgo Adgo Acnogo Adnogo

Ago Anogo

Die Fabrication

Fci Fdi

Fi

Die Test

Si/Ge/GaAs/...

Fcigo Fdi

go Fcinogo Fdi

nogo

Figo Fi

nogo

go go nogo nogoST

EP

#1: D

ie p

rocess

Die #i

Die Fabrication

Fci Fdi

Fi

Fci Fdi

Fi

Die Test

Si/Ge/GaAs/...

Fcigo Fdi

go Fcinogo Fdi

nogo

Figo Fi

nogo

Fcigo Fdi

go Fcinogo Fdi

nogo

Figo Fi

nogo

go go nogo nogogo go nogo nogoST

EP

#1: D

ie p

rocess

ST

EP

#1: D

ie p

rocess

Die #i

Fc1go Fd1

go

F1go

SiP Assembly

Ac Ad

A

SiP Test

go go nogo nogo

ST

EP

#2: S

iPp

rocess

Fcngo Fdn

go

Fngo

Die #1 Die # n

…..

Carrierprocess

Acgo Adgo Acnogo Adnogo

Ago Anogo

Fc1go Fd1

go

F1go

Fc1go Fd1

go

F1go

SiP Assembly

Ac Ad

A

Ac Ad

A

SiP Test

go go nogo nogogo go nogo nogo

ST

EP

#2: S

iPp

rocess

ST

EP

#2: S

iPp

rocess

Fcngo Fdn

go

Fngo

Fcngo Fdn

go

Fngo

Die #1 Die # n

…..

Carrierprocess

Acgo Adgo Acnogo Adnogo

Ago Anogo

Acgo Adgo Acnogo Adnogo

Ago Anogo

Defect level :

DLi= Fd

igo / F

igo = Fd

igo / (Fc

igo + Fd

igo)

YSIP

= 100 [ P1

× P2× … × P

n] × P

s× P

intQ × P

w

With Pi= 1 - DL

i

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 19

Yield and Quality ChallengesYield and Quality Challenges

YSIP = 100 [ P1 × P2× … × Pn] × Ps × PintQ × Pw

SIP

Die1 Substrate

Die2 Interconnects

Die Placement

Final yield= Multi-Die quality x Assembly quality

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 20

Yield and Quality ChallengesYield and Quality Challenges

In this example, with DL = 20000 ppm (i.o. 4100 ppm),SIP yield becomes 95.33%

DLi (ppm) Pi (%)

Substrate 600 99.94

Die 1 4100 99.59

Die 2 35500 97.45

Die 3 1200 99.88

YSIP 96.87

PCB

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 21

System-level Test:• Quality level

• Yield

at a reasonable

• Test cost!

Fab of X

&

PCM Test

Fab of B

Fab of A

&

PCM Test

SiP

Packaging.

Die X

Wafer Test

Die B

Die A

Wafer Test

SiP

Final Test

D

E

L

I

V

E

R

Y

Fab of X

&

PCM Test

Fab of B

Fab of A

&

PCM Test

SiP

Packaging.

Die X

Wafer Test

Die B

Die A

Wafer Test

Die X

Wafer Test

Die B

Die A

Wafer Test

SiP

Final Test

D

E

L

I

V

E

R

Y

A Complex Test FlowA Complex Test Flow……

System-level Test:• DfT

• Fast Diagnosis

and…

• Known-Good-Dies!

Passive Substrate

Analog/RF

Digital or Mixed-mode

Wafer Test Final Test

Known

Good

Dies!

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 22

KGD Definition:(from a test perspective)

• Good enough to meet, at die level, at least the

same quality level as a packaged IC

• Implies that :

• KGD test = WT + FT of a packaged die!!

KnownKnown--GoodGood--DieDie

A challenge for…

RFHigh-speed, high-res. Mixed-SignalHigh pin-count digital (with small pad sizes)

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 23

Chip A

Chip B

Chip C

Today:

+ Test of PCB+ Interconnects+ Passives

+ Functional

Test

Test

Test

Test cost = 3U Test cost = 4U

Future (w SIP):

- Test of PCB- Interconnects- Passives (almost 0!)= Functional

Test cost < 3U Test cost << 4U

With a Higher

Coverage!

SIP Test VisionSIP Test Vision

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 24

SIP Test ArchitecturesSIP Test Architectures� Introduction

� Definition

� SIP examples

� Yield and quality challenges

� Test Strategy

� Bare Die Test� Mechanical probing techniques

� Electrical probing techniques

� Reliability screens

� Functional system test� Path-based testing

� Loopback techniques: DFT and DSP

� Test of Embedded Components� SIP TAP

� Interconnections

� Digital logic and memories

� Analog and RF Components

� MEMS

� Concluding Remarks

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 25

Bare Die TestingBare Die Testing

� Objective = KGD quality

Effort

Quality

KGD

because of probing limits

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 26

RF Probing ChallengesRF Probing Challenges

Bonding: 1-3mm

Leadframe: mm size

Package: Wire bonding length

Probe tips: 3-5mm

Total Probe length: 10-15mm

Die under probes: Needle length

Rule of thumb: 10mm represent 10nH serial inductance�impossible to test some devices @freq, or difficult correlation process!

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 27

Thin film technologies Thin film technologies

for RF probingfor RF probing

Contact bumps

Membrane

Microstriptransmission line

Ground plane

Carrier PCB Membrane

Forced-delivery

mechanism

Contact bumps

Terminations

and bypasses

Carrier PCB Membrane

Forced-delivery

mechanism

Contact bumps

Terminations

and bypasses

40um-60um

Thin film, Μr 25um

40um-60um

Thin film, Μr 25um

40um-60um

Thin film, Μr 25um

Rule of thumb:

0.05mm represents less than 0.5nH serial inductance (typical 0.2nH specified)

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 28

•Springs for solder bumps

•Cantilevers for

contact pads

•Length < 600 µm

•Width < 60µm

•Thickness ~ 10 µm

MEMS technologies for RF probingMEMS technologies for RF probing

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 29

Alternative / Indirect Test MethodsAlternative / Indirect Test Methods

IDD R

L = 1 nH

CLKIN

VOSC

CLKOUT

(Reference Clock Signal)

Package

CLPF

RLP

F

(VDD Test Pattern)

DUT

VCLK

• Power supply sweep• I-V Signatures• Multiple observation points• Simple method

• “black-box” methodology

• No functional testing• Short test time

Signature-based Testing

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 30

NonNon--contact die testingcontact die testing

Non-contact wafer probing eliminatesscrubbing, while reducing the test cost,

thanks to massive parallelism

Pro

ber

Tes

ter

Signal

Distribution

Signal

Transfer

Intelligent

Test

Circuits

Parametric

Test

Circuits

Tx/Rx

Tx/Rx

Tx/Rx

Tx/Rx

Tx/Rx

Power

Tx/Rx

Tx/Rx

Tx/Rx

Tx/Rx

Tx/Rx

App

lication

Circu

its

Probe Card Device Under Test

Pro

ber

Tes

ter

Signal

Distribution

Signal

Transfer

Intelligent

Test

Circuits

Parametric

Test

Circuits

Tx/Rx

Tx/Rx

Tx/Rx

Tx/Rx

Tx/Rx

Power

Signal

Distribution

Signal

Transfer

Intelligent

Test

Circuits

Parametric

Test

Circuits

Tx/RxTx/Rx

Tx/RxTx/Rx

Tx/RxTx/Rx

Tx/RxTx/Rx

Tx/RxTx/Rx

Power

Tx/Rx

Tx/Rx

Tx/Rx

Tx/Rx

Tx/Rx

Tx/RxTx/Rx

Tx/RxTx/Rx

Tx/RxTx/Rx

Tx/RxTx/Rx

Tx/RxTx/Rx

App

lication

Circu

its

Probe Card Device Under Test

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 31

SIP Test ArchitecturesSIP Test Architectures� Introduction

� Definition

� SIP examples

� Yield and quality challenges

� Test Strategy

� Bare Die Test� Mechanical probing techniques

� Electrical probing techniques

� Reliability screens

� Functional system test� Path-based testing

� Loopback techniques: DFT and DSP

� Test of Embedded Components� SIP TAP

� Interconnections

� Digital logic and memories

� Analog and RF Components

� MEMS

� Concluding Remarks

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 32

Test at the System LevelTest at the System LevelSIP testing requires a greater diversity of ATE resources than SoC and leads

to large disparities in test times and resource utilization among die

Solutions:

� Insert in multiple testers (temporary acceptable, but not cost-effective!!!)

� Better scheduling of test resources to allow independent, simultaneous test of each accessible die in SIP (temporary acceptable, but not cost-effective!!!)

� BIST / DFT / DSP: still emerging in many areas!!!

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 33

So, what to do?

Intermediate Test Points may affect

signal integrity and leads to longer test

times

System Function Testing IssuesSystem Function Testing Issues

TX

RX

D

A

D

A

LNA

PA

AGC

BufDSP

core

TX-FEM Transceiver Baseband

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 34

TX

RX

D

A

D

A

LNA

PA

AGC

BufDSP

core

TX-FEM Transceiver Baseband

Test Rx and Test Rx and TxTx paths independentlypaths independently

Ref: “Seamless test of Digital Components in M/S paths”, S. Ref: “Seamless test of Digital Components in M/S paths”, S. OzevOzev et al.et al.

DSP

DSP

Modulated

RF

ModulatedRF

Pro:Pro:

- close to the application conditions- two-pass test = reduced test time- reduced risk of signal degradation

Contra:Contra:

- expensive ATE- quality of contacts critical

- diagnosis??

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 35

Test Rx and Test Rx and TxTx paths together (paths together (loopbackloopback))

Ref: “Wafer level RF Test and Ref: “Wafer level RF Test and DfTDfT for VCO Modulating Transceiver Architectures”, S. for VCO Modulating Transceiver Architectures”, S. OzevOzev, et al., et al.

DSP

DSP

Pro:Pro:

- low-cost (no?) ATE

- benefit from passive substrate- test simulation- easier BIST implementation

Contra:Contra:

- need DFT (not a simple short-circuit!)- correlation with lab measurements

- mgt of yield / test escapes- diagnosis??

TX

RX

D

A

D

A

LNA

PA

AGC

BufDSP

core

TX-FEM Transceiver Baseband

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 36

LoopbackLoopback startsstarts atat the the beginningbeginning

DAC

Base-

Band

DSP

LNA

LO

LP

FilterADC

Down-

Converter

Up-Converter

PALP

Filter

Phase/Frequency divider

BP Filter

Offsetmixer

External

LO

TA DAC

Base-

Band

DSP

LNA

LO

LP

FilterADC

Down-

Converter

Up-Converter

PAPALP

Filter

Phase/Frequency divider

BP Filter

Offsetmixer

External

LO

TA

G. Srinivasan, et al.VTS 2006

External loopback

DAC

Base-

Band

DSP

DA/ADtest loop

RF Filter

&

DiplexerLNA

LO

LP

FilterADC

Down-Converter

Up-Converter

PA

LPFilter

TATest

Test

DAC

Base-

Band

DSP

DAC

Base-

Band

DSP

DA/ADtest loop

RF Filter

&

DiplexerLNA

LO

LP

FilterADC

Down-Converter

Up-Converter

PA

LPFilter

TATest

Test

J. Dabrowski, J.G. BayonISDFTVS 2004

Internal loopback

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 37

SIP Test ArchitecturesSIP Test Architectures� Introduction

� Definition

� SIP examples

� Yield and quality challenges

� Test Strategy

� Bare Die Test� Mechanical probing techniques

� Electrical probing techniques

� Reliability screens

� Functional system test� Path-based testing

� Loopback techniques: DFT and DSP

� Test of Embedded Components� SIP TAP

� Interconnections

� Digital logic and memories

� Analog and RF Components

� MEMS

� Concluding Remarks

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 38

Die Access: SIP Test Access PortDie Access: SIP Test Access Port

Star Configuration(Intermediate Tests)

Ring Configuration(End-user test)

TDI

TCK

TMS

TDO

10

die1

TDI

TCK

TMS

TDO

die2

TDI

TCK

TMS

TDOdie3

10

10

1

0

1

0

1

0

1

0

R/S = 1

TDO

TDI

TCK

TMS1

TMS2

TMS3

TDO

TDI

TCK

TMS1

TMS2

TMS3

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

1010

TDI

TCK

TMS

TDO

die2

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDOdie3

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO1010

1

0

1

0

1

0

1

0

1

0

1

0

SiP

TA

P

Die2

Die3

Die4

Die1 TDI

TCK

TMS

TDO

10

die1

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

die2

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDOdie3

10

10

1

0

1

0

1

0

1

0

R/S = 1

TDO

TDI

TCK

TMS1

TMS2

TMS3

TDO

TDI

TCK

TMS1

TMS2

TMS3

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

1010

TDI

TCK

TMS

TDO

die2

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDOdie3

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO1010

1

0

1

0

1

0

1

0

1

0

1

0

SiP

TA

P

Die2

Die3

Die4

Die1TDI

TCK

TMS

TDO

10

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

10

10

1

0

1

0

1

0

1

0

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

1010

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO1010

1

0

1

0

1

0

1

0

1

0

1

0

Die2

Die3

Die4

R/S = 0

TDO

TDI

TCK

TMS1

TMS2

TMS3

TDO

TDI

TCK

TMS1

TMS2

TMS3SiP

TA

P

Die1 TDI

TCK

TMS

TDO

10

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

10

10

1

0

1

0

1

0

1

0

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

1010

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

TMS

TDO1010

1

0

1

0

1

0

1

0

1

0

1

0

Die2

Die3

Die4

R/S = 0

TDO

TDI

TCK

TMS1

TMS2

TMS3

TDO

TDI

TCK

TMS1

TMS2

TMS3SiP

TA

P

Die1

R/S = 0

TDO

TDI

TCK

TMS1

TMS2

TMS3

TDO

TDI

TCK

TMS1

TMS2

TMS3SiP

TA

P

Die1

Die

TDI

TMSTCK

TDO

Die

TDI

TMSTCK

TDO

Die

TDI

TMSTCK

TDO

BYPASS BYPASS BYPASSBYPASS BYPASS BYPASS

Die

TDI

TMSTCK

TDO

Die

TDI

TMSTCK

TDO

Die

TDI

TMSTCK

TDO

DEVICE_ID DEVICE_ID DEVICE_IDDEVICE_ID DEVICE_ID DEVICE_ID

Solution for end-user: SIP-TAP

F.de Jong, A. Biewenga

[ITC 2006]

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 39

InterconnectionsInterconnections

Die2Analog/MS

Die2Analog/MS

Die 3Digital

Die 3DigitalDie1

Digital

Die1Digital

Step Instruction Die 1 Instruction Die 3 Test vector

1 Reset Reset

2 PRELOAD PRELOAD

3 EXTEST EXTEST

4 EXTEST EXTEST

Vector #1

Vector #2

5 Reset Reset

Exploitationof boundary-scan resources

Specific test strategy forintermediate testing

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 40

Digital and Memory DiesDigital and Memory Dies

Die 4RF

Die2Analog/MS

Die 3Digital

Die 4RF

Die 4RF

Die2Analog/MS

Die2Analog/MS

Die 3Digital

Die 3Digital

Controllable through the SIP-TAP

Transparent mode

Maximum exploitationof boundary-scan resources

Ideally require DFT in each die

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 41

MS and RF DiesMS and RF Dies

� Challenges:� Cost reduction of the required test

equipment

� Test of embedded dies because of

difficulty to access these dies after SIP

assembly.

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 42

MS and RF Dies: MS and RF Dies: cost reductioncost reduction

Analog Network of Converters:

• DSP-based methods / algorithms, the contribution of the non-linearity of each converter is discriminated.

• The converters may be re-used as embedded instruments in the loop!

V. Kerzerho, et al. [ETS 2006]D

AC

3

ADC4

DA

C1

DAC4

AD

C3

ADC1

AD

C2

RF Part Digital part 2

Analog Part 1

Analog Part 2

Analog Part 1

Digital part 3 Digital

part 4

Digital

part 1

ANC

DA

C3

ADC4

DA

C1

DAC4

AD

C3

ADC1ADC1

AD

C2

RF Part Digital part 2

Analog Part 1

Analog Part 2

Analog Part 1

Digital part 3 Digital

part 4

Digital

part 1

ANCANCΣ

I 1 I 2 I 3..INO1O2 O3 …OM

0 1 1 0 11 0 0 1 01 0 1 0 11 1 1 0 0

ADC10 1 1 0 11 0 0 1 01 0 1 0 11 1 1 0 0

DAC2

0 1 1 0 11 0 0 1 01 0 1 0 11 1 1 0 0

DAC3

0 1 1 0 11 0 0 1 01 0 1 0 11 1 1 0 0

DACn

0 1 1 0 11 0 0 1 01 0 1 0 11 1 1 0 0

ADC20 1 1 0 11 0 0 1 01 0 1 0 11 1 1 0 0

ADC30 1 1 0 11 0 0 1 01 0 1 0 11 1 1 0 0

ADCm0 1 1 0 11 0 0 1 01 0 1 0 11 1 1 0 0

ANC

DAC1

Σ

I 1 I 2 I 3..INO1O2 O3 …OM

0 1 1 0 11 0 0 1 01 0 1 0 11 1 1 0 0

ADC10 1 1 0 11 0 0 1 01 0 1 0 11 1 1 0 0

DAC2

0 1 1 0 11 0 0 1 01 0 1 0 11 1 1 0 0

DAC3

0 1 1 0 11 0 0 1 01 0 1 0 11 1 1 0 0

DACn

0 1 1 0 11 0 0 1 01 0 1 0 11 1 1 0 0

ADC20 1 1 0 11 0 0 1 01 0 1 0 11 1 1 0 0

ADC30 1 1 0 11 0 0 1 01 0 1 0 11 1 1 0 0

ADCm0 1 1 0 11 0 0 1 01 0 1 0 11 1 1 0 0

ANC

DAC1

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 43

MS and RF Dies: MS and RF Dies: accessaccess

Boundary Scan cell

Boundary Scan Path

Instruction

Identification

BypassBypass

Die Core

SoutSin

TDO

TDI

IN1 OUT1

OUT2

OUT3

OUT4

IN2

IN3

IN4

TCK

TMS

interne Scan

TA

P C

on

tro

lle

r

TRST

Test AccessPort (TAP)

Analog Test

Access Port

(ATAP)

Analog I/O

Digital I/O

Boundary Scanpath

Internal analogbus

ABM

DBM

MS Core

TBIC

AB1

AB2

MUX

TAP Controller

Bypass Reg.

instruction Reg.

Add. Register

CONTROLLER

AT2

AT1

TDO

TCK

TMS

TDI

ABM ABM

DBM DBM

ABMABM

DBMDBM

MS Core

TBIC

AB1

AB2

MUX

TAP Controller

Bypass Reg.

instruction Reg.

Add. Register

CONTROLLER

AT2

AT1

TDO

TCK

TMS

TDI

ABMABM ABMABM

DBMDBM DBMDBM

Compliant digital die with IEEE 1149.1 Compliant MS die with IEEE 1149.4

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 44

New challenges because of MEMS New challenges because of MEMS

packagingpackaging

LiTaO3LiTaO3

Assembly enabling an electrical contact and sealing

Assembly:

Thermo-compression

Polymer pattern on PICSPICS substrate

LiTaO3 substrate SAW filter

Cavity

Assembly enabling an electrical contact and sealing

Assembly enabling an electrical contact and sealing

Assembly:

Thermo-compression

Assembly:

Thermo-compression

Polymer pattern on PICSPICS substrate

LiTaO3 substrate SAW filter

Cavity

Polymer pattern on PICSPICS substrate

LiTaO3 substrate SAW filter

Cavity

PICS substrate

SAW

filter

Gold stud-bump

Polymer seal ring

1mm1mm

Source: LIRMM

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 45

Test of Embedded MEMSTest of Embedded MEMS

Testing the cavity sealing

Cross-section view of a porous Si Top view of a porous Si

A moisture sensor is added

Embedded MEMS

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System-on-Chip Test Architectures Ch. 5 – SIP Test Architectures - P. 46

Concluding RemarksConcluding Remarks

� SIP offers many solutions for the miniaturization

of heterogeneous electronic systems

� Known-good-die and assembly are very critical

to achieve high yield and quality levels

� Test of embedded dies is a challenge too

� Many solutions for a cost-effective system test

are emerging