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Magnetic memories:from magnetic storage
to MRAM and magnetic logic
Claude CHAPPERT, CNRSDépartement "Nanospintronique"
Institut d'Electronique FondamentaleUniversité Paris Sud, Orsay, FRANCE
WIND
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 2
Back to the basics
hr
21: ±s
Electrons carry a charge electronics
… and a spin
-
+
-
+
-
+
-
+
-
+
-
+
transfer of information storage
quantum mechanics: projection of angular momentum
dipolar magnetic moment sgm Bs
r
h
r μ−=
2
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 3
Back to the basics
Electrons carry a charge electronics
e-
lmrsmr
magnetic moments
… and a spin magnetism
-
+
-
+
-
+
-
+
-
+
-
+
transfer of information storage
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 4
Back to the basics
Electrons carry a charge electronics
e-
lmrsmr
“localized” atomic magnetic moments
magnetic storage
… and a spin magnetism
-
+
-
+
-
+
-
+
-
+
-
+
transfer of information storage
3
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 5
Outlook
- the basics of magnetic recording
- the basics of spin electronics
- the magnetic tunnel junction
- the principle of the “magnetic random access memory” or MRAM
- “spin angular momentum transfer” and the “Spin-RAM”
- towards magnetic logic chips
- beyond MRAM and Spin-RAM in solid state magnetic mass storage
- beyond MRAM and Spin-RAM in “spin logic”
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 6
Basics: magnetic energies for storage
“localized” atomic magnetic moment picture + basic magnetic energies
Exchange interaction
"magnetization" M in ferromagnets= magnetic moment per unit volume
Magnetic anisotropy energy
tends to keep parallel the atomic moments
total energy changes with the orientation of M
-90° 0° 90° 180° 270°
TkVKE
B>>=Δ
magnetic storage of the information
"0" "1"VM=μr
4
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 7
Basics : exchange interaction and magnetization
I
HOerstedt
Zeeman energy: interaction with a magnetic field
MHVErr
⋅−=
coil
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 8
Basics : exchange interaction and magnetization
Zeeman energy: interaction with a magnetic field
MHVErr
⋅−=
coil
+ Magnetic anisotropy energy: preserves orientation of magnetization after writing
5
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 9
Magnetic recording
1953: Magnetic core memory 1956: First HDD - IBM RAMAC
1898: V. Poulsen’s Drum Telegraphone
1928-35s: Magnetic tape:F. Pfleumer / BASF-AEG
1933: Ring type headE. Schuller
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 10
The Landau-Lifshitz-Gilbert (LLG) equation
Speed: the natural dynamics of the magnetization
( )effHMdtMd rrr
×−= 0μγ
Heff
M
⎟⎟⎠
⎞⎜⎜⎝
⎛×+
dtMdM
M
rr
rα
f0 = 28 MHz / mT ( = 2.8 GHz / kOe )
Damped precession of the magnetization M around its equilibrium axis
Precession frequency: f = f0 Heff
Effective field Heff : all the magnetic energies
damping torque
6
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 11
Precessional dynamics in thermally activated reversal
Néel - Brown reversal =thermally activated precessional behavior within the energy well
attempt frequency function of α , KU , …
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 12
Non volatility: thermally excited switching
τt
eP−
=
long term stability of the magnetic storage :spontaneous reversal of the magnetization due to thermal activation
Néel – Brown modelprobability P for no reversal
after a time t :
( )TkE B/exp0 Δ= τττ0 ~ 1 nskBT = thermal energyT = temperature
VKE =Δ
ex : stability on 10 years = 3 108 s1-P = 10-6 KV ~ 54 kBT1-P = 10-12 KV ~ 68 kBT"soft" error
The "magnetic non volatility"
7
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 13
The necessary compromise in magnetic recording
increase recording density
redu
cebit v
olum
e V
reducew
ritingpow
er
thermal stability :ΔE = K V
increase K
writing :Hwriting ~ K
reduce KX
Research / Innovation
+ reading : sensitivity, speed
-90° 0° 90° 180° 270°
TkVKE
B>>=Δ
"0" "1"
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 14
Storing : scalability of solid state magnetic recording
-90° 0° 90° 180° 270°
TkVKE B60≈=Δ
"0" "1"
10-9 soft error rate in 10 years
today's best : FePt (L10) 2 nm
5.4 nm
non volatility :
A potential for non volatile « nano »- spin electronics… but Hswitching ~ 12 Teslas !
field induced writing impossiblespin transfer writing requires high currentsprecession speed ~ 33 GHz !!!!
8
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 15A “bridge” between magnetic storage and electronics ?
1988: a major step into “Spin Electronics”
1988: The giant magnetoresistance (GMR)in magnetic multilayers
~ 80%
Fe/Crmultilayers
FeCrFe
R/R(H=0)
1988: GMR discovered simultaneously by Fert et al. (Orsay) and Grünberg et al. (Jülich)
NOBEL 2007
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 16
Outlook
- the basics of magnetic recording
- the basics of spin electronics
- the magnetic tunnel junction
- the principle of the “magnetic random access memory” or MRAM
- “spin angular momentum transfer” and the “Spin-RAM”
- towards magnetic logic chips
- beyond MRAM and Spin-RAM in solid state magnetic mass storage
- beyond MRAM and Spin-RAM in “spin logic”
9
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 17
The foundation of spin electronics
"spin flip" scattering event
<> : mean free path λrelaxation time τ
spin diffusion length ∑ =sf
sf
τ
λλ0
: spin mean free pathsfsdl λλ∝
weak spin flip scattering rate ( lsd >> λ ) "two channels" conduction model
R
electrons traveling inside conductors
normal metals
or
R↑
R↓
R↑
R↓ferromagnetic metals:
spin dependent λ
N. Mott, Adv. Phys 13, 325 (1964)Fert+Campbell, PRL 1967
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 18
The foundation of spin electronics
To directly « see » the « two-channel » conduction, one must make a material with internal structuration at the same scale as the λ↑ et λ↓mean free path:
the spin valve
F ferromagnetic layer
F ferromagneticlayer
NM non magnetic layer (Cu, ..)
λ↑ > ecouches > λ↓“nano” input:
10
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 19
Giant magnetoresistance in multilayers
I
parallel configuration antiparallel configurationRP < RAP
λ↑, λ↓ >> tlayers (a few nm )• λ↓ << λ↑ ρ↓ >> ρ↑
( )↓↑
↓↑+= ρρ
ρρρP( )
4↓↑ += ρρρAP
Also: spin dependant "interface" scattering, reflection, …
F
FNM
F
FNM
“nano” input !!!!
1988: Fert et al. (Orsay) and Grünberg et al. (Jülich)
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 20
I"free" ferromagnetic layer (NiFe, CoFe,..)
"pinned" ferromagnetic layer
metallic (Cu) interlayer
θ
current in plane(CIP)
A first useful device : the "spin valve"
R = R0 – ΔR/2 cos (θ) ΔR/R↑↑ ~ 6 à 20 %
B. Dieny et al., PRB 1991
A convenient, compact, high sensitivity magnetic sensor !
… but low resistance, low signal amplitudeplanar geometry
not well adapted to solid state electronics
11
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 21
Outlook
- the basics of magnetic recording
- the basics of spin electronics
- the magnetic tunnel junction
- the principle of the “magnetic random access memory” or MRAM
- “spin angular momentum transfer” and the “Spin-RAM”
- towards magnetic logic chips
- beyond MRAM and Spin-RAM in solid state magnetic mass storage
- beyond MRAM and Spin-RAM in “spin logic”
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 22
The tunnel junction
Metal 1
Metal 2
eVEF
0EF
M1 M2
insulator
insulating barrier (Al2O3, …)
transmission by tunnel effect through a very thin (~1nm) barrier
electron spin is not affected by the tunneling
12
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 23
The magnetic tunnel junction
Ferromagnetic metal 1
Ferromagnetic metal 2
tunnel barrier (Al2O3, …)
Jullière,Phys. Lett. A54 225 (1975)
parallel state antiparallel state
eVEF
0EF
F1 F2
insulator
eVEF
0EF
F1 F2
insulator
spin dependant tunneling, MR = (RAP-RP) / RP >> 1
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 24
The magnetic tunnel junction
)()()()(
FF
FF
ENENENEN
P↓↑
↓↑
+−
=21
21
12
PPPP
RRTMRAP +
=Δ
=
Jullière,Phys. Lett. A54225 (1975)
parallel state antiparallel state
EF
eVEF
eV
Ferromagnetic metal 1
Ferromagnetic metal 2
tunnel barrier (Al2O3, …)
13
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 25
Coherent tunneling through single crystal MgO tunnel junctions
S. Yuasa et al. Nature Mat. 3, 868 (2004)
giant ΔR/R : 250% at 20K186% at 293 K
(also: Parkin et al., Nat. Mat 3 (2004)
origin: different attenuation for spin up and spin down electrons due to symmetry matching between metal and MgO states: up to 6000% predicted ! [Butler et al, PRB63 (2001); Mathon et al., PRB 63 (2001) ; Butler & Gupta, Nat. Mat. 3, 845 (2004) ; Zhang et al., PRB 172407 (2004)]
Fe(001)
MgO(001)
Fe(001)
H (Oe)
RA
(kΩ
.µm
2 )
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 26
The magnetic tunnel junction M. Jullières, 1975J. Moodera, 1995
"free" ferromagnetic layer (NiFe, FeCo, FeCoB,…)
"pinned" ferromagnetic layer (NiFe, FeCo, FeCoB, …)
tunnel barrier (ex: Al2O3, MgO ) ~ 1 nm thick
ΔR/R↑↑ > 600 % @ RT !!!I
(MgO single crystal tunnel barrier)
practical value: ΔR/R ~ 100-180 % for RA ~ 3-50 Ω.µm2
A "vertical", high signal device for high density electronics !
14
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 27
Outlook
- the basics of magnetic recording
- the basics of spin electronics
- the magnetic tunnel junction
- the principle of the “magnetic random access memory” or MRAM
- “spin angular momentum transfer” and the “Spin-RAM”
- towards magnetic logic chips
- beyond MRAM and Spin-RAM in solid state magnetic mass storage
- beyond MRAM and Spin-RAM in “spin logic”
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 28
The magnetic RAM (M-RAM)
"0"
"1"
Principle :- store binary information on arrays of magnetic tunnel junctionsconnected by conducting lines, - that serve to address each cell individually for reading and writing
+
"cross point" architecture
Magnetic Random Access Memory (M-RAM) (IBM, NVE, … > 1996)
15
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 29
The magnetic RAM: practical implementation
"0"
"1"
+
"cross point" architecture
Transistor
practical MRAM cell:"1T1MTJ" architecture for “reading”
incomplete integration of the writing function :needs magnetic field created by independent line for writing
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 30
MRAM: writing / Stoner-Wohlfarth scheme
H X (bit line)
HY(digit line)
HK
HK
M
OR …
16
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 31
Magnetic RAM : "Savtchenko" toggle writing mode
F1
F2Ru
• free layer = synthetic antiferromagnet• current lines at 45 deg. of easy axis
toggle switching mode
B. N. Engel et al., IEEE Trans. Magn. 41, 132 (2005)
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 32
Magnetic RAM : "Savtchenko" toggle writing mode
• excellent immunity to program errors(cf Korenivski, APL 86 (2005))
• 4 Mbits Freescale demo :- 0.18 µm CMOS- ~47 F2 cell size- 25 ns read/write cycle time- 3.3 V
(Andre et al., IEEE JSSC 40, 301 (2005))
But : high currents (several mA) needed for writing !!!
17
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 33
Magnetic RAM : reducing Iwriting
channeling the magnetic field using magnetic "cladding"
Sending a current in a conducting line is not a very efficient way of creating a magnetic field on a nano-element !!!!
gain of a factor of ~2 on the field/current rationlimits the stray field on half-addressed cells
I
other "tricks" can help gain additional factors, up to ????
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 34
Freescale: 1rst MRAM product in 2006
Named "Product of the Year" [Electronics Products Magazine, Jan. 2007]
Above CMOS technology
in 2007 : achieved army specifications automotive applicationsNEW in Nov. 2008: - spin off company EVERSPIN
- new products, target : battery backed SRAM
4 Mbit standalone memoryToggle switching reliability, speed (30ns), cyclability
18
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 35
"Field induced magnetic switching" : downscaling prospect
F
field induced switching :• requires a current in a conducting line• electromigration limit 107 A/cm2 ~ 100 mA/µm2
@ constant j : available Hwrite decreases ~ as F
Ito ensure required non volatility (Neel's model)
energy barrier KV >40 kBT , if V ↓ as F2, then K ↑ ~ 1/F2
0.00
2.00
4.00
6.00
8.00
10.00
12.00
14.00
16.00
18.00
0 20 40 60 80 100F (nm)
I (m
A)
Imax (electromigration limit)I for switching - W= (4/3) FI for switching - W= 2 F
realistic estimation for 2 different width W of
magnetic element:W = 4/3 F
and 2 F
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 36
A "conventional" answer: the thermally assisted writing in TAS-MRAM
From a "0" ….. … to a "1"
"0" state
OFF ON
Heat Field cool
OFF
"1" state
OFF
Switch
ON
Word line
MTJ
addressingtransistor
From a "0" ….. … to a "1"
"0" state
OFF
"0" state
OFF ON
Heat
ON
Heat Field cool
OFF
Field cool
OFF
"1" state
OFF
"1" state
OFF
Switch
ON
Switch
ON
Word line
MTJ
addressingtransistor
Altis Semicoductors, Quimonda: demo at IEDM Dec 2006 with 2 bits/cell
Exchange biasedstorage layer
is SAF/AF multilayer
high TB
low TBbarrier
19
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 37
CMOS integration of TAS-MRAM
0
100
200
300
400
500
600
0 20 40 60 80 100
F (nm)
pow
er (µ
W)
required writing power for bit dia.=(4/3)F
available power with Wt=(4/3)F
available power with Wt= 3 F
becomes more favorable when F decreasescondition much relaxed by using bipolar transistor (cf PC RAM)issues remaining:
- match thermal stability with heat sensitivity in the cell- still needed: a magnetic field from a conducting line
required switching current for MTJ width WMTJ= 4/3 F
available current for 2 transistor widths:WT = 3 F
WT = 4/3 F
analytical model for 2ns pulse and 140K temperature rise
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 38
Outlook
- the basics of magnetic recording
- the basics of spin electronics
- the magnetic tunnel junction
- the principle of the “magnetic random access memory” or MRAM
- “spin angular momentum transfer” and the “Spin-RAM”
- towards magnetic logic chips
- beyond MRAM and Spin-RAM in solid state magnetic mass storage
- beyond MRAM and Spin-RAM in “spin logic”
20
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 39
J. C. Slonczewski, JMMM 159, L1 (1996)L. Berger, PRB 54, 9353 (1996)
The Spin Transfer Torque mechanism
the incoming electronsloose their transverse spin angular momentum to the magnetization M of the ferromagnetic layer
+conservation of total angular momentum
torque applied on M
switching beyond a threshold Jc in current density : scalable
e-
transversecomponent
~1 nm
ferromagneticlayer F2
in the ferromagnetic layer: exchange interaction between e- spin and M
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 40
Writing: Spin Transfer Torque switching
sd exchangeinteraction
F1 thicklayer
F2 thinlayer
e-
e-
J. C. Slonczewski, JMMM 159, L1 (1996)
Writing “0”
Writing “1”
Writing by a bipolar current density with Jc+ and Jc
-
21
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 41
Magnetization switching by spin transferin MgO tunnel junctions
J. Hayakawa et al., Jap.JAP 44, L1267 (2005)
ex. of good compromise:TMR ~ 80% for Tanneal ~ 300°C
<JC> ~ 8 105 A/cm2
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 42
spin torque MRAM by SONY
SONY, IEDM Conference, Dec. 2005
A way towards very high density, fast MRAM, with potential for downscaling down to 20nm or less !
A true "solid state" integration of R/W and magnetic media !
22
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 43
From conventional MRAM…to "spin transfer" MRAM
• can we reach high operation speed ? • will it be reliable ?
Demo chips of « Spin »-RAM:SONY, IEDM Dec. 2005 HITACHI, ISSCC March 2007)
simple “ integrated ” architecture, above CMOS technology, “ high “ density ( <16 F2 ), potential for downscaling down to 20nm “ fast ” (40-100 ns) M-RAM: main advantage of M-RAM
versus other NVM RAM….)
Freescales’s MRAM (2006)
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 44
the Landau-Lifshitz-Gilbert (LLG) equation
( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛×+×−=
dtMdM
MHM
dtMd
eff
rr
rrr
rαμγ 0
Heff
M
Precession of the magnetization and spin transfer
( )pMMjG rrr××−
+ the "spin transfer torque"
friction torque (damping)
"negative friction" torque induced by spin transfer
f0 ~ 2.8 GHz / kOe
p
≠ 0 only if M and p are non colinear
switching threshold Jc :~ when negative friction
overcomesdamping
23
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 45
Macrospin dynamics of spin transfer writing
M
pmY
mZ
filmplane
thermal excitation spreads the initial orientation
( )pMMjG rrr××−
= 0 if M and p are colinear
+
wide distribution of switching time
Devolder et al., PRB75, 64402 (2007)
J.Sun, PRB 62, 570 (2000)The case of a platelet magnetized in plane:
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 46
Field(Energy-gradient driven switching)
Spin-Transfer Torque(friction-gradient driven switching)
enhancedfriction
« negative »friction
Switching by spin-transfer torque vs field
24
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 47
Routes towards fast spin transfer writing
Thermally assisted spin transfer switching :
• J ~ Jc
• tpulse ~ 10 – 100 ns (cf demos)
enhancedfriction
« negative »friction
Precessional spin transfer switching :
• J > Jc
• tpulse ≤ 1 ns
• control thermal fluctuations non zero initial torque
- T. Devolder et al., APL 88, 152502 (2006) + PRB 75, 064402-1,5 (2007) + PRB 75, 224430-1,10 (2007) + PRL100, 057206 (2008)- Ito et al., APL89, 252509 (2006)- Serrano-Guisan et al., PRL101 (2008) 087201; Garzon et al., PRB78, R180401 (2008)- etc..
M
p
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 48
STT MRAM main configurations
free layer
fixed layer(reference)
tunnel barrier
2nd tunnel barrier
spin polarizingfixed layer
(a) (b) (c)
free layer
fixed layer(reference)
tunnel barrier
2nd tunnel barrier
spin polarizingfixed layer
(a) (b) (c)
© Y. Suzuki
M
p
mX
mY
mZ
filmplane
25
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 49
CMOS integration of spin–RAM: writing
24.724.020.221.618.9Rn = Vn/Id,sat for Wt=F (kΩ)20.2424.9634.6537.0547.7
Max current (µA) at 25°C for transistor width Wt=F
0.50.60.70.80.9Nominal voltage (Vn)2232456590Node (F in nm)
20162013201020072004LOW POWER-NMOS Year
compatibility with ITRS roadmap
bipolar use of the NMOS transistor
RMTJ
VDD
(NMOStransistor)
Vd
Id
(MTJ)
Vs
Vg
RMTJ
GND
Vs
Id
Vd
Vg
VDDGND
RMTJ
VDD
(NMOStransistor)
Vd
Id
(MTJ)
Vs
Vg
RMTJ
GND
Vs
Id
Vd
Vg
VDDGND
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 50
CMOS integration of STT MRAM
RMTJ
VDD
(NMOStransistor)
Vd
Id
(MTJ)
Vs
Vg
RMTJ
GND
Vs
Id
Vd
Vg
VDDGND
RMTJ
VDD
(NMOStransistor)
Vd
Id
(MTJ)
Vs
Vg
RMTJ
GND
Vs
Id
Vd
Vg
VDDGND
requires a "bipolar" use of the NMOS transistor
large variation of resistance during the write process (Sony)
within ITRS 2003 roadmap
in planemagn.
26
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 51
CMOS integration of STT MRAM
⎟⎠⎞
⎜⎝⎛ +⎟
⎠⎞
⎜⎝⎛=≈ K
SSFONaSW HMMtejj 0
0//)( 2
2 μμη
αh
approximate switching current density for in plane magnetization
thermal stabilityfactor
in plane shape anisotropy
>>
current density should not depend much on size !!!!
in planemagn.
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 52
IWR (SONY, IEDM 2005)
IWR (lab's best, 2006)
transistor's limit
Scalability of Spin-RAM : writing
spin transfer writing
(4/3) F (min)
2 nm
transistor width: (4/3) F for high density memory
R↑↑ ~ Rtransistor / 2
magnetic element:
tunnel junction :
RA ~ 1-20 Ω.µm2, within reach also good for reading
writing speed:~ 20-40 ns
in planemagn.
27
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 53
CMOS integration of STT MRAM
approximate switching current density for out of plane magnetization
thermal stabilityfactor
available current for 2 transistor widths:WT = 3 F
WT = 4/3 F
more favorable than in plane case, if similar values of α/η are obtained
out of planemagn.
( )effAONbSW HMtejj 0)(
2 μη
α⎟⎠⎞
⎜⎝⎛=≈ ⊥h
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
160.0
0 20 40 60 80 100
F (nm)
curr
ent I
(µA
)
Isw - alpha=0.01Isw - alpha=0.1It,max for Wt= 4/3 FIt,max for Wt= 3 F
required switching current for MTJ width WMTJ= 4/3 F
α = 0.1
α = 0.01
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 54
Perpendicular STT RAM
Toshiba Develops MRAM Device, Opening Way to Gb CapacityNikkei Electronics Asia, November 7, 2007
TbCo alloy (?)
with TMR ~ 100% and jC ~ 3. 106 A/cm2
28
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 55
Summary: Spin - RAM specifications
20 nm ?130 nmScalability
>> NAND
~SRAM
embedded RAM
>> NAND<< SRAM
Position vs CMOS
~ ns~ 40 ns (2.7 ns)Speed
~ infinite1015Endurance
> 10 yearsNon volatility
Above CMOSTechnology
< 16 F225 – 80 F2Cell size
PredictedProducts / Demos
Logi
c ci
rcui
ts ?
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 56
Outlook
- the basics of magnetic recording
- the basics of spin electronics
- the principle of the “magnetic random access memory” or MRAM
- “spin angular momentum transfer” and the “Spin-RAM”
- towards magnetic logic chips
- beyond MRAM and Spin-RAM in solid state magnetic mass storage
- beyond MRAM and Spin-RAM in “spin logic”
29
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 57
CMOS Logic Circuits
Telecom Automobile
Medical ……
•Low power (near zero static power)•High density (45nm, 2007)•High Speed (>Some GHz)•……
Audio/video
Military/Aerospace
ASIC
Application-Specific Integrated Circuit
•High mask cost (1.4M$/Mask @ 90nm)•Long delay to correct a bug•Long time to market
+ smart cards: no internal power, cheap, robust
LEAKAGE CURRENTS
CMOS logic circuits: every where … and problems
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 58
Programmable logic devices
a
b
s
111
001
010
000
sba
ASIC Programmable Logic
a=Adr 0
b=Adr 1
s
111
010
001
000
SRAM
config.:EEPROM,
Flash
LUT: Look Up Table
30
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 59
Low standby Power Programmable logic devices
100% 61% 0%14%
Active Inactive
Non volatile, multi-core logic:are powered only the core that need to operate others preserve state and start « instantly » when powered on
Towards a magnetic FPGA
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
“switches” and “logic blocs” (CLB) are made:non volatileprogrammable
by Spin- MRAM elements
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 60
FPGA
I/O
I/O
FPGA Logic Circuits
SRAM
Static RAM based FPGA •High computing speed•Infinite programming endurance
•Long latency at each start or restart•High standby power (>30% for 90nm) •Data loss in case of power failure•Uneasy dynamical reconfiguration
CMOS intrinsic memorizing constraint: Data Volatility
Flash
Configuration
High speed
transceiver
I/OI/O
Look Up Table
SRAM
Input
Flip-Flop
Output
Configurable logic block (CLB)
Clk
31
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 61
FPGA
I/O
I/O
Non volatile FPGA Logic Circuits
Flash
Configuration
High speed
transceiver
I/OI/O
Look Up Table
SRAM
Input
Flip-Flop
Output
Configurable logic block (CLB)
Clk
Black & Das, JAP87, 6674(2000)
NVM
NVM
replace Flash and SRAM by a non volatile memory (NVM)directly embedded inside the look up table
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 62
FPGA
I/O
I/O
Flash
Configuration
High speed
transceiver
I/OI/O
Look Up Table
SRAM
Input
Flip-Flop
Output
Configurable logic block (CLB)
Clk
replace Flash and SRAM by a non volatile memory (NVM)directly embedded inside the look up table
NVM
replace the standard Flip-Flop by a non volatile one
NVM
Non volatile FPGA Logic Circuits
NVM
32
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 63
Spin-RAM based Non-volatile Flip Flop
STREP MAGLOGW. Zhao, E. Belhaire (IEF), V. Javerliac, B. Dieny (SPINTEC)P. Mazoyer, F. Jacquet (ST Microelectronics)
master slave flip-flop based on spin transfer switching
non volatile,instant on/off record all intermediate calc. steps
if :- CMOS compatible IWR- writing speed atprocessor's rate (~3 GHz)
e-MRAM could enter the CPU !!!
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 64
Sense Amplifier
<100ps
MTJ model (V.Javerliac et al.,MMM,2006)+ STMicroelectronics 90nm design kit
Wp=0.12um
Wn=0.12um
TMR=80%
R(0)=8.9KΩRAP RP
Out
Fast sensing of MRAM status for logic circuits
W. Zhao, IEF, PhD March 2008Electrical simulation
Black & Das, JAP87, 6674(2000)
~ non volatile SRAMfast reading possiblewriting ?
33
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 65
Mixed CMOS-Tunnel junctions logic
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 66
Outlook
- the basics of magnetic recording
- the basics of spin electronics
- the magnetic tunnel junction
- the principle of the “magnetic random access memory” or MRAM
- “spin angular momentum transfer” and the “Spin-RAM”
- towards magnetic logic chips
- beyond MRAM and Spin-RAM in solid state magnetic mass storage
- beyond MRAM and Spin-RAM in “spin logic”
34
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 67
Another promising scientific breakthrough:current induced domain wall motion
thin wall
thick wall
electrons
DW vr
DW vrelectrons
transfer of spin angular momentum
Berger (’84,’92)Tatara & Kohno (2004)
transfer of momentum
(Grollier, APL 2004Vernier, EuroPhys. 2005Thiaville, cond-mat 407628,…)
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 68
Current induced domain wall propagation: downscaling prospect
F
writing current :Ex: w = F = 90 nm, t = 10 nm, jC= 106 A/cm2 IWR ~ 9 µA(standard transistor @ F= 90 nm : IMAX ~ 0.5 mA/µm )(?) scaling of the writing current density vs non volatile DW trapping ???
to ensure required non volatility (Neel's model)energy barrier KV > x kBT , if V ↓ as F2, then K ↑ ~ 1/F2
Tunnel barrier
e-
R↑↑
e-
R↑↓
current induced writing of a domain wall based M-RAM :
35
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 69
One proposition of "Solid State Hard Disk"
Shiftable magnetic shift register and method of using the sameS.S.P. ParkinUS patent 6,834,005B1of Dec. 21, 2004
same data organization as in HD,but no moving part
fast access time !domain wall speed: up to ~100m.s
high data rates !
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 70
A new approach to magnetic storage
Shiftable magnetic shift register and method of using the sameS.S.P. Parkin - US patent 6,834,005B1 pub. Dec. 21, 2004
Submicrometer Ferromagnetic NOT Gate and Shift Register. Allwood, D. A. et al. Science 296, 2003 (2002)
Multiple layer magnetic logic memory device Cowburn, R.P. & Allwood, D.A.. UK patent GB2430318A (2007)
Information is stored in a magnetic strip, as contiguous magnetization domains.
Domains are made to migrate synchronously from programming head to reading head with either an external magnetic field or a current injected in the strip (spin transfer effect).
read headwrite head
DW propagation
wafer
magnetic stripe
36
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 71
Russel Cowburn et al.
D. Allwood et al., Science 309 (2005) 1688
storage ring (shift register with one input)
3D storage
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 72
Spin electronics today:a giant move towards integration …
Spin-RAM, SONY, IEEE 2005
Longitudinal Hard Disk recordingWith spin valve head (1997)
Size ~ 100µm, separate R/W heads and media… but first spin electronics device !
size < 100nmfull « integration »
37
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 73
1988
: GMR disc
overed
1991
: "sp
in valve
"
1997
: product,
SV HD read
head (IB
M)
1990 2000 2010
2005
: product,
TMR HD read
head (Sea
gate)
1995
: "prac
tical"
TMR
2006
: product,
MRAM (F
reesc
ale)
… in a short span of time
1996
-2000
: "sp
in transfe
r" pred
icted
/observe
d
) 201
0: sp
in-RAM product
??? (RENESAS, N
EC, SONY,
Samsu
ng, CROCUS, …
)
10 years
?10 years
WIND/IMST - Memory tutorial - IMEC - 26 Nov 2008 74
Perspective: a new paradigm for “spintronics”
electron: charge + spin
magnetization
Mspin dependent transport in multilayers
controlling magnetization by “currents”(w or w/o charges)
mesoscopicspintronics
from uniformly magnetized nanostructures to non colinear magnetization structures (vortex, domain walls, …)
• spin dependant quantum transport• coherence and Quantum Information ?
materials, hybrid stacks nanotechnologies, devices
“nano”architectures, device integration
+ phase cohérence
a wide field for research !