Chap2 Lect06 Rc Model

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Principles of VLSI Design CMPE 413Capacitance and Resistance Model

Capacitance

Any two conductors separated by an insulator form a parallel-plate capacitor.

Gate capacitance is very important as it creates channel charge necessary for operation.

Source and Drain have capacitance to bodyAcross reverse-biased diodes

Calleddiffusion capacitance because it is associated with source/drain diffusion.

Gate capacitance

Approximate channel as connected to

source

.

Cpermicron is typically 2fF/m.

n+ n+

p-type body

W

L

tox

SiO2gate oxide

(good insulator, ox

= 3.90)

polysilicongate

Cgs

ox

WL tox

Cox

WL= =

Cpermicron

= W


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Diffusion Capacitance

Csb, Cdb

Undesirable, called parasitic capacitance.

Capacitance depends on area and perimeter

Use small diffusion nodes

Comparable to Cg for

contacted diffusion

Half of Cg for uncon-

tacted diffusion.

Varies with process


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Gate Capacitance Details

The gate capacitance can be decomposed into several parts:

One part contributes to the channel charge.

A second part is due to the topological structure of the transistor.

MOS Structure Capacitances, Overlap:

Lateral diffusion: source and drain diffusion extend under the oxide by an amount xd.

The effective channel length (Leff) is less than the drawn length L by 2*xd.This gives rise to a linear, fixed capacitance called overlap capacitance.

Since xd is technology dependent, it is usually combined with Cox.

poly

drainsource xd

xd

L

n+n+

W

Poly

n+n+Leff

tox

CgsO

CgdO

Cox

xd

W CO

W= = =


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Gate Capacitance Details

Channel Charge

The gate-to-channel capacitance is composed of three components, Cgs, Cgd and Cgb.

Each of these is non-linear and dependent on the region of operation.

Estimates or average values are often used

Linear: Cgb ~=0 since the inversion region shields the bulk electrode from the gate.

Saturation: Cgb and Cgd is ~= 0 since the channel is pinched off.

Operation Region Cgb Cgs Cgd

Cutoff CoxWLeff 0 0

Linear 0 CoxWLeff/2 CoxWLeff/2

Saturation 0 (2/3)CoxWLeff 0


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Diffusion Capacitance Details

Junction or Diffusion Capacitances

This component is caused by the reverse-biased source-bulk and drain-bulkpn-junctions.

This capacitance isnon-linearand decreases as reverse-bias is increased.

Bottom-plate junction

Depletion region capacitance is

Bottom

sidewall

W

LS

xj

channel

ND

sidewall

channel-stop

implant NA+

Cbottom

Cj

WLS

=


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Cjis the junction capacitance per unit area.

where, Cj0 is the junction capacitance at zero bias and is highly process dependent.

Mj is the junction grading coefficient, typically between 0.5 and 0.33 depending on

the abruptness of the diffusion junction.

0 is the built-in potential that depends on doping levels given by

where, T is the thermal voltage.

NA and ND are doping levels of the body and source diffusion region.

Ni is the intrinsic carrier concentration in undoped silicon.

Cj

Cj0

1Vsb

0

---------+

Mj

=

0

T

NA

ND

Ni2

-----------------

ln=


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Side-Wall Capacitance

Formed by the source region with doping ND and the p+channel-stop implant with doping

NA+.

Since the channel-stop doping is usually higher than the substrate, this results in a higher

unit capacitance:

C'jsw is similar to Cj but with different coefficients.Mj = 0.33 to 0.5.Note that the channel side is not included in the calculation. Some SPICE models have an

extra parameter to account for this junction.

xjis usually technology dependent and combined with C'jsw as Cjsw.

Total diffusion/junction capacitance is:

Csw

Cjsw

xj

W 2 LS

+( )=

Cdiff

Cbottom

Csw

+ Cj

AREA Cjsw

PERIMETER+= =

Cdiff

CjL

SW= C

jsw2L

SW+( )+


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MOS Capacitance Model

Capacitive Device Model

The previous model can be summarized as:

The dynamic performance of digital circuits is directly proportional to these capacitances!

G

B

DS

CGS CGD

CDBCSB CGB

CGS = Cgs + CgsO

CGD = Cgd + CgdO

CGB = CgbCSB = CSdiff

CDB = CDdiff


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Source-Drain Resistance

Scaling causes junctions to be shallowerand contact openings to be smaller.

This increases the parasitic resistance in series with the source and drain regions:

This resistance can be expressed as:

The series resistance degrades device performance by decreasing drain current.

One option is to cover drain and source regions with a low-resistivity material such as tita-

nium or tungsten.

This process is calledsilicidation, and is used in reducing poly resistance as well.

G

S D

RS RDW

LD

Draincontact

Drain

GateVGS,eff

RS D,

LS D,W

--------------R RC

+=

RC

Contact Resistance=

R Sheet resistance 50 1k( )=

LS,D = length of source/drain region.


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Capacitance Example

Given:

tox

20nm=

L 1.2um=

W 1.8um=

LD

LS

3.6um= =

xd

0.15um=

Cj0

3 104

F m2

=

Cjsw0 8 10 10

F m=

Determine the zero-bias value of all relevant capacitances.

Gate capacitance, Cox, per unit area is derived as:

ox tox

3.5 102 fF um

203

10 um----------------------------------------------

1.75 fF um

2

= =

Total gate capacitance Cg is:

Cg

WLCox

1.8um 1.2um 1.75 fF um2

3.78fF= = =

Overlap capacitance is:C

GSOC

GDOWx

dC

ox0.47fF= = =

Subtracting out overlap capacitance yields Cgb under zero-bias:

C

gb

C

ox

WL

eff

3.78 2 0.47 2.84fF= = =

Cox =


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Capacitance Example

In this example, diffusion capacitance dominates gate capacitance (3.78fF versus

9.2fF).

Note that this is the worst case condition. Increasing reverse bias reduces diffusion

capacitance (by about 50%).

Also note that side-wall dominates diffusion. Advanced processes use SiO2 to isolate

devices (trench isolation) instead of NA+ implant.

Diffusion capacitance is the sum of bottom:

Cj0

LD

W 31

10 fF um2

3.6um 1.8um 1.95fF= =

Plus side-wall (under zero-bias):

Cjsw0

2LD

W+( ) 81

10 2 3.6um 1.8um+( ) 7.2fF= =

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Chap2 Lect06 Rc Model