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BASIC ELECTRICAL AND ELECTRONICS ENGINEERING LAB MANUAL Subject Code : 17CA02309 Regulations : CREC – R17 Class : III Semester (CSE) CHADALAWADA RAMANAMMA ENGINEERING COLLEGE (AUTONOMOUS) Chadalawada Nagar, Renigunta Road, Tirupati – 517 506 Department of Electrical and Electronics Engineering

CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

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Page 1: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

BASIC ELECTRICAL AND ELECTRONICS ENGINEERING LAB MANUAL

Subject Code : 17CA02309

Regulations : CREC – R17

Class : III Semester (CSE)

CHADALAWADA RAMANAMMA ENGINEERING COLLEGE

(AUTONOMOUS) Chadalawada Nagar, Renigunta Road, Tirupati – 517 506

Department of Electrical and Electronics Engineering

Page 2: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

BASIC ELECTRICAL AND ELECTRONIC ENGINEERING LAB

II year I Semester: CSE

Course Code Category Hours / Week Credits Maximum Marks

17CA02309 Foundation L T P C CIA SEE TOTAL

- - 3 2 30 70 100

Contact Classes: Nil Tutorial Classes: Nil Practical Classes:

57

Total Classes: 57

OBJECTIVES: The student has to learn about:

Practical verification of Superposition and Thevenin’s theorem

Experimental determination of O.C. and S.C. parameters of two – port network

Swinburne’s Test on DC Shunt Machine and Predetermination of Efficiency of a Given DC

Shunt Machine (i) while working as a Motor and (ii) while working as a Generator

Brake Test on DC Shunt Motor and determination of Performance Characteristics

OC & SC Tests on Single-Phase Transformer and Predetermination of Efficiency and

Regulation at any given load and Power Factor.

PART- A : ELECTRICAL LAB

Expt. 1 Verification of Superposition Theorem.

Expt. 2 Verification of Thevenin’s Theorem.

Expt. 3 Determination of Open circuit and Short circuit parameters

Expt. 4 Swinburne’s Test on DC Shunt Machine (Predetermination of Efficiency of a Given DC Shunt

Machine Working as Motor and Generator).

Expt. 5 Brake Test on DC Shunt Motor. Determination of Performance Characteristics.

Expt. 6 OC & SC Tests on Single-Phase Transformer (Predetermination of Efficiency and Regulation at

Given Power Factors).

PART – B

ELECTRONICS LABORATORY

Expt. 7 P-N Junction Diode and Zener Diode Volt-Ampere Characteristics.

Expt. 8 Bipolar Junction Transistor in CB Configuration-Input and Output

Characteristics, Computation of α.

Expt. 9 Half-Wave Rectifier- a) Without Filter b) With Capacitor Filter.

Expt. 10 Full-Wave Rectifier- a) Without Filter b) With Capacitor Filter.

Expt. 11 Bipolar Junction Transistor in CE Configuration-Input and Output

Page 3: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

Characteristics, Computation of β

Out comes: At the end of the course the student should be able to

Practically verify Superposition and Thevenin’s theorem.

Experimentally determine the O.C. and S.C. parameters of two-port network.

Conduct Swinburne’s Test on DC Shunt Machine and Predetermine the Efficiency of a given DC Shunt

Machine (i) while working as a Motor and (ii) while working as a Generator

Conduct Brake Test on DC Shunt Motor and determine the Performance Characteristics

Conduct OC & SC Tests on Single-Phase Transformer and Predetermine the Efficiency and Regulation

at any given load and Power Factor.

Page 4: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

Exp - 1

VERIFICATION OF SUPERPOSITION THEOREM

AIM: To verify the superposition theorem.

GIVEN CIRCUIT:

STATEMENT:

Super Position Theorem:

In any linear, bilateral, multi source network the response in any element is equal to the

algebraic sum of the responses obtained by each source acting separately while all other

sources are set equal to zero.

APPARATUS:

S. No Name of the apparatus Range Type Quantity

1 Dual channel regulated

power supply (0 – 30) V/2A digital 01No

2 Ammeter (0 – 200m) A MC 01No

3 Resistors

100

150

200

Carbon

Composition

01No

01No

01No

4 Experi mental board - - 01No

5 Connecting wires - - Required number

CIRCUIT DIAGRAM:

Page 5: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

WhenV1&V2 source acting(To find I):-

WhenV1 source acting(To find I1):-

WhenV2 source acting(To find I2):-

Theory:-

Page 6: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

Superposition theorem:-

The superposition theorem states that in a linear bilateral network consisting N number of

sources each branch current is the algebraic sum of N currents through ( branch voltage), each of

which is determined by considering one source at a time and removing all other sources. In

removing the sources, voltage sources are short circuited or replaced by resistances equal to their

internal resistances for no ideal sources, while the ideal current sources are open circuited.

PROCEDURE:

1. Connect the circuit as per the fig (1).

2. Adjust the output voltage of sources X and Y to appropriate values (Say 30V and20V

respectively).

3. Note down the response (current, IL) through the branch of interest i.e. AB ammeter

reading.

4. Now set the source Y (20V) to 0V.

5. Note down the response (current, ILl) through the branch AB (ammeter reading).

6. Now set the source X (20V) to 0V and source Y to 20V.

7. Note down the response (current, ILll) through the branch AB (ammeter reading).

8. Reduce the output voltage of the sources X and Y to 0V and switch off the supply.

9. Disconnect the circuit.

TABULAR FORMS:

Tabular Column:

Fig(1)

S. No Applied voltage

(V1) Volt

Applied voltage

(V2) Volt

Current

IL

(mA)

Fig(2)

Page 7: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

S. No Applied voltage

(V1) Volt

Current

IL

(mA)

Fig(3)

S. No Applied voltage

(V2) Volt

Current

IL

(mA)

PRECAUTIONS:

1. Initially keep the RPS output voltage knob in zero volt position.

2. Set the ammeter pointer at zero position.

3. Take the readings without parallax error.

4. Avoid loose connections.

5.Avoid short circuit of RPS output terminals.

Result:

CONCLUSION:

1. The given circuit is linear, since the response is algebraic sum of the individual responses.

2. Superposition theorem is not valid for power responses.

S.No Load current Theoretical Values Practical Values

1 When Both sources are acting, IL

2 When only source X is acting, ILl

3 When only source Y is acting, ILll 11

LI

Page 8: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

Exp - 2

VERIFICATION OF THEVENIN’S THEOREM

AIM: To verify Thevenin’s for GIVEN CIRCUIT:

STATEMENTS:

Thevenin’s theorem

It states that any linear, active network with two open terminals can be replaced by an equivalent

circuit consisting of Thevenin’s equivalent voltage source Vth in series with Thevenin’s equivalent

resistance Rth. Where Vth is the open circuit voltage across the two terminals and Rth is the

resistance seen from the same two terminals.

APPARATUS:

S. No Name of the apparatus Range Type Quantity

1 Regulated power supply (0 – 30)V/2A Digital 01

2 Voltmeter (0-30)V MC 01

3 Ammeter (0-2000m)A MC 01

4 Resistors

100Ω

150Ω

200Ω

Carbon

Composition

02

01

01

5 Experimental board --- --- 01

6 Connecting wires --- ---- Required number

Page 9: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

CIRCUIT DIAGRAMS:-

TO FIND IL:

FIG(1)

TO FIND VTH:

FIG(2)

Theory:

The venin’s theorem:

The values of VTh and RTh are determined as mentioned in thevenin’s theorem.

Once the thevenin equivalent circuit is obtained, then current through any load resistance RL

connected across AB is given by, I =

Thevenin’s theorem is applied to d.c. circuits as stated below.

Any network having terminals A and B can be replaced by a single source of e.m.f.

VTh in series with a source resistance RRh.

Page 10: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

(i) The e.m.f the voltage obtained across the terminals A and B with load, if any removed i.e.,

it is open circuited voltage between terminals A and B.

(ii) The resistance RTh is the resistance of the network measured between the terminals A and B

with load removed and sources of e.m.f replaced by their internal resistances. Ideal

voltage sources are replaced with short circuits and ideal current sources are replaced

with open circuits.

To find VTh, the load resistor ‘RL’ is disconnected, then VTh = Χ R3

To find RTh,

RTh = R2 +

Thevenin’s theorem is also called as “Helmoltz theorem”

IN = Χ =

Procedure:

Thevenin’s Theorem

1. Connect the circuit as per fig (1)

2. Adjust the output voltage of the regulated power supply to an appropriate value (Say 30V).

3. Note down the response (current, IL) through the branch of interest i.e. AB (ammeter

reading).

4. Reduce the output voltage of the regulated power supply to 0V and switch-off the supply.

5. Disconnect the circuit and connect as per the fig (2).

6. Adjust the output voltage of the regulated power supply to 30V.

7. Note down the voltage across the load terminals AB (Voltmeter reading) that gives Vth.

8. Reduce the output voltage of the regulated power supply to 0V and switch-off the supply.

9. Disconnect the circuit and connect as per the fig (3).

10. Adjust the output voltage of the regulated power supply to an appropriate value (Say V =

30V).

11. Note down the current (I) supplied by the source (ammeter reading).

Page 11: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

12. The ratio of V and I gives the Rth.

13. Reduce the output voltage of the regulated power supply to 0V and switch-off the supply.

14. Disconnect the circuit and connect as per the fig (4).

15. Adjust the output voltage of the regulated power supply to 30V

16. Note down the response (current, IN) through the branch AB (ammeter reading).

17. Reduce the output voltage of the regulated power supply to 0V and switch-off the supply.

18. Disconnect the circuit.

Tabulation for Thevinen’s theorem:

THEORITICAL VALUES PRACTICAL VALUES

RTH=RL=

IL=

Vth=

RTH=RL=

IL=

Vth=

Result:-

Parameter

Thevenin’s theorem

Theoretical

Values

Practical

Values

Vth

Rth

Load current

Page 12: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

Exp - 3

DETERMINATION OF OPEN CIRCUIT AND SHORT CIRCUIT PARAMETERS

AIM:

To determine open circuit impedance parameters (Z) and short circuit admittance

parameters (Y) of the given two port network.

.

GIVEN CIRCUIT:

APPARATUS:

S. No Name of the apparatus Range Type Quantity

1 Regulated power supply (0 – 30) V/2A digital 01

2 Voltmeters (0-30) V MC 01

3 Ammeters (0-200m) A MC 01

4 Resistors

330

470

630

Carbon

Composition

01

01

01

5 Experi mental board - - 01

6 Connecting wires - - Required

Number

Page 13: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

CIRCUIT DIAGRAMS:

BASIC CIRCUIT

WHEN V1=0

WHEN I1=0

WHEN V2=0

WHEN I2=0

Page 14: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

THEORY:

A port is normally referred to a pair of terminals of a network though which we can

have access to network of calculating current in any part of network. Frequently the problem is

move restried in nature and may be that of calculating the response at a terminal pair designated an

input when excitation is applied at another terminal pair designated as input terminals. It is a

problem of terminal through which it is accessible, is called “Two Port Network.“

If we relate the voltage of one port to the current of the same port, we get driving

point immitance. On the other hand, if we relate the voltage of one port to the current at another

port, we get transfer immittance. Immitance is a general term used to represent either the

impudance or the admittance of a network.

We will consider a general two-port network composed of linear, bilateral elements

and no independent sources. Dependent sources are permitted. It is represented as a black box with

two accessible terminals pairs as shown in. The voltage and current at port -1 are V1 and I1 and at

port =II are V2 and I2. The position of V1 and V2 and the directions of I1 and I2 are customarily

selected. out of four variables, I1I1V2 and I2 only two are independent. The other two are expressed

in terms of the independent variable of network parameters.

Procedure:

1. Connections are made as per the circuit diagram.

2. Open the port – I i.e, I1=0 find the values of I1,I2, V1.

3. Short circuits the port V2 =0 find the values of V2,I1, I2.

4. Repeat steps 2,3 for port – II and find the values of V1,I1,I2 and V2,I1,I2 respectively.

5. Find all the parameters of two port networks I,e, Z,Y, ABCD, AI BI CI DI, h, g parameters

from the above data.

PRECAUTIONS:

1. Initially keep the RPS output voltage knob in zero volt position.

2. Set the ammeter pointer to zero position.

3. Take the readings without parallax error.

4. Avoid loose connections.

5. Do not short-circuit the RPS output terminals.

Page 15: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

TABULAR FORMS:

Theoratical Values

V1

(volts)

I1

(mA)

V2

(mA)

I2

(mA)

V1=0

I1=0

V2=0

I2=0

Practical values

V1

(volts)

I1

(mA)

V2

(mA)

I2

(mA)

V1=0

I1=0

V2=0

I2=0

Theoretical calculations:

1. When I1 = 0 (i.e.,) When port is open circuited:

RL =

V2 =

Page 16: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

I2= =

V1 = I2.R =

2. When port -2 is open circuited (I2=0):

V1 =

Rt =

I1 = =

V2 =

3. When port -1 is short circuited ( V1=0):

V2 =

Rt =

I2 = =

I1 = I2

4. When port –II is short – circuited (V2 = 0 ) :

V1 =

Rt =

I1 = V1/Rt =

I2 =

Theoretical calculations for parameters:

Z-parameters:

Z11 = / I2=0 =

Z12 = / I1=0 =

Z21 = / I2=0 =

Z22 = / I1=0 =

Y – Parameters

Y11 = / V2=0 =

Y12 = / V1=0 =

Y21 = / V2= 0 =

Y22 = / V1= 0 =

Result:

S. No Parameter Theoretical Values Practical Values

1 Z11

2 Z12

3 Z21

Page 17: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

4 Z22

5 Y11

6 Y12

7 Y21

8 Y22

Page 18: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

Exp-4

SWINBURNE’S TEST

AIM : To predetermine the performance of a D.C Shunt machine as a Motor and Generator.

NAME PLATE DETAILS : Volts : 220 HP: 3hp

Amps : 12 Extn. Type : shunt

RPM : 1500 Volts : 220

KW: 2.25 Amps : 0.8

APPARATUS : Voltmeter (0-250V,MC)

Ammeters (0-2A,MC) – 2

Rheostat (200, 1.7A)

Tachometer

SPST switch

CIRCUIT DIAGRAM:

PROCEDURE:

1. Make the connections as per the circuit diagram.

2. Keep the field rheostat in minimum resistance position and then close switch ‘S’.

3. Give the supply to the motor and start it with the help of the starter.

4. Run the motor on no load. By varying the field rheostat, bring the motor to its rated speed

and open the switch ‘S’.

5. Tabulate the readings of all the meters.

+

-

220V, DC supply

A + -

V

+

-

L Z A

A

AA Z

ZZ

200,

1.7A

(0-2A)

MC

(0-250V) MC

3A

3A

A +

-

-

(0-2A)

MC

S

Page 19: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

TABULAR COLUMN:

S.No If (A) Io(A) VL (V)

CALCULATIONS:

Vm*Io = Total losses on no load (No load Input),Wo

= Stray losses + Field cu losses + No load armature cu losses

= Constant losses + No load armature cu losses

Constant losses, Wc = No load Input- No load armature cu losses

Wc =Wo-Wcu=(Vm*Io) – (IO – If )2 * Ra ;

* Ra = armature resistance

Let “ I “ be full load current of the machine

V = Rated voltage.

D.C. machine as a generator :

Output of the generator = V * I

Armature current = I + If

Armature cu loss = (I +If )2 * Ra

Total losses = Constant losses + Armature cu losses

= Wc + (I +If )2 * Ra

Input to generator = Output + Losses

= (V * I) + Wc + (I +If )2 * Ra

% Efficiency = (Output/Input ) * 100

= (V * I) / ((V * I) + Wc + (I +If )2 * Ra)

Efficiency at any fraction of the full load current , (X*I) is

% Efficiency = ((X * V * I) / ((X * V * I)+Wc +(X * I +If )2 * Ra) )* 100

* Where X is Fraction of the load

TABULAR COLUMN :

S.No Load (X) Load Current

(A)

Armature CU

Loss (W)

Total

Losses (W)

Output

(W)

Input (W) %

Page 20: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

1 ¼

2 ½

3 ¾

4 1

D.C. machine as a motor :

Input to the motor = V * I

Armature current = I - If

Armature cu loss = (I – If )2 * Ra

Total losses = Constant losses + Amature cu losses

= Wc + (I - If )2 * Ra

Output = Input - Losses = (V * I) - (Wc + (I - If )2 * Ra )

% Efficiency = (Output/Input ) * 100

= ((V * I) - (Wc + (I - If )2 * Ra)/(V * I)

Efficiency at any fraction of the full load current , xI is

% Efficiency = (((X * V * I)+WE -(X* I - If )2 * Ra) /(X * V * I)) * 100

TABULAR COLUMN:

S.No Load (X) Load Current

(A)

Armature CU

Loss (W)

Total

Losses (W)

Output

(W)

Input (W) %

1 ¼

2 ½

3 ¾

4 1

Circuit Diagram for determination of Armature Resistance:

0-3A, MC

5A

5A

+

-

220V, DC supply

A

+ A

200,

1.7A

+ -

Page 21: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

TABULAR COLUMN:

S.NO. Voltage Va (V) Current Ia (Amps) Ra(cold)=Va/Ia , Ω

Ra (hot) = 1.2 * average of Ra (cold)

MODEL GRAPH:

RESULTS:

Page 22: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

Exp-5

BRAKE TEST ON D.C. SHUNT MOTOR

AIM: To plot the performance curves of a D.C Shunt motor by conducting actual load test.

NAME PLATE DETAILS : Volts : 220 HP : 3hp

Amps : 12 Extn. Type : shunt

RPM : 1500 Volts : 220

KW : 2.25 Amps : 0.8

APPARATUS : Ammeter (0-15A,MC)

Voltmeter (0-250V,MC)

Rheostat (200,1.7A)

Tachometer

CIRCUIT DIAGRAM:

S1 S2

PROCEDURE:

1. Make the connections as per the circuit diagram.

2. Keep the field Rheostat at minimum resistance position.

3. Give the supply to the motor and start it with the help of the starter.

4. Vary the field Rheostat & bring the motor to its rated speed.

5. Load the brake drum of the motor in steps until motor draws the rated current.

ZZ

+

-

220V, DC supply

A + -

V

+

-

L Z A

A

AA Z

200

1.7A

(0-

15A)

MC

(0-250V) MC

15A

15A

Page 23: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

6. At each step, tabulate the readings of voltmeter, ammeter, load on the brake drum and

speed of the motor.

TABULAR COLUMN:

Vm

(volt)

Im

(amp)

Load

W=(S1~S2)

Kg

Speed

N

(rpm)

Input(IP)

(Watts)

Vm*Im

Torque

(N-m)

9.81*W*R

Output

(Watt)

(2ΠNT)/60

Efficiency

OP/IP

CALCULATIONS:

VM = voltage input to the motor ( volts)

IM = motor current ( amp)

W = (S1 ~ S2) = load on the brake drum ( kgs)

N = speed of the motor ( rpm )

Input to the motor = VM * IM watts

Torque, T = W * R kg-mt. (where, R is radius of the brake drum)

= 9.81 * W * R nw-mt.

Output = (2ΠNT)/60 watts , where T is in N-M ;

B.H.P = Output/ 746 h.p

% Efficiency = (output/input ) * 100

MODEL GRAPH:

Output (watts)

%

I/P

torque

speed

Page 24: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

Exp-6

OPEN CIRCUIT & SHORT CIRCUIT TESTS ON 1- TRANSFORMER

AIM: To pre–determine the efficiency and voltage regulation of a 1- transformer by conducting

open circuit & short circuit tests.

NAME PLATE DETAILS: Dimmerstat Transformer

Voltage : 230V Pr. Voltage : 115V

Max. load : 15A Sec. Voltage : 230V

Max. kVA : 4.05 Single phase , 50Hz

I/P : 230V Capacity : 1kVA

O/P : 0 – 270V

APPARATUS : Voltmeters ((0-150V,MI),(0-75V,MI))

Ammeters ((0-500mA,MI), (0-5A,MI))

Wattmeter’s ((150V, 1A, LPF),(75V,5A,UPF))

1- Variac

CIRCUIT DIAGRAMS:

(0-500mA)

MI

(150V,1A,LPF)

P

N

1,230V,50Hz

AC Supply

1A

1A

A -

V

M L

C V

(0-150V)

MI

115V 230V 1KVA

230V/(0-270V) 4.05 KVA

O.C TEST

P

N

1,230V,50Hz

AC Supply

supply

5A

5A

A -

V

M L

C V

(0-5A), MI

(0-75V)

MI

(75V,5A,UPF)

230V 115V 1KVA

230V/(0-270V) 4.05KVA

S.C. TEST

Page 25: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

PROCEDURE:

Open circuit test ( to be conducted on L.V. side ) :

1. Make the connections as per circuit diagram.

2. Set the dimmerstat to zero output position. Switch on the supply.

3. Apply the rated voltage on the L.V. side by adjusting the dimmerstat.

4. Tabulate the readings of all the meters.

Short circuit test ( to be conducted on H.V. side ) :

1. Make the connections as per circuit diagram.

2. Set the dimmerstat to zero output position. Switch on the supply.

3. Pass the rated current on the H.V. side by adjusting the dimmerstat.

4. Tabulate the readings of all the meters.

CALCULATIONS:

Open circuit test

IO = open circuit current , mA

VO = open circuit voltage, Volts

WO = open circuit power, Watts

WO = VO * IO * cosO , Watts

where , cosO = No load power factor.

cosO = WO/(VO * IO)

Iw = working current = IO * cos O

Im = magnetizing current = IO * sin O

Rm = VO/Iw

Xm = VO/Im

Short circuit test

ISC = short circuit current, Amps

VSC = voltage applied in the short circuit test, Volts

WSC = power consumed in short circuit test, Watts

Page 26: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

WSC = VSC * ISC * cosSC , Watts

cosSC = WSC/(VSC * ISC)

ZO2 = VSC /ISC

RO2 = ZO2 * cosSC

XO2 = ZO2 * sinSC

RO1 = RO2/K2 ; XO1 = XO2/K

2

where,K = tranformation ratio= V2/V1

EQUIVALENT CIRCUIT:

EFFICIENCY CALCULATIONS :

WO = power in O.C test = iron losses (no-load cu losses are negligible)

WSC = full load cu loss

ISC = full load current = I2

Copper losses at any fraction (X) of full load = X2 * WSC

Here, I2 = Rated Full load current

V2 = Rated Secondary Voltage

Output = V2 * I2 * cos2 assume cos2 = 0.8

Input = Output + losses

= V2 * I2 * cos2 + WO + X2 WSC

% Efficiency at any fraction (X) of load

= ((XV2I2 cos2)/(XV2I2cos2+ WO +X2 WSC))* 100

% Regulation = ((I2 Ro2 cos2 + I2 Xo2 sin2 )/ V2)*100

+ve for lagging power factor

Rm Xm

R01 X01

V1 V21

Page 27: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

-ve for leading power factor

TABULAR COLUMN:

Load

Current

=XI2

(amps)

Total losses =

Wo+X2Wsc, Watts

Output=

XV2I2cos2

Watts

Input=

Output+

losses

Watts

Efficiency =

Output/Input

Regulation

MODEL GRAPH :

RESULTS:

Output (watts)

efficiency Regulation

Page 28: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

PART – B

ELECTRONICS LABORATORY

Exp-7

PN DIODE CHARACTERISTICS

AIM:

1. To plot Volt-Ampere Characteristics of Germanium P-N Junction Diode.

2. To find cut-in Voltage for Germanium P-N Junction diode.

3. To find static and dynamic resistances in both forward and reverse biased conditions of

Germanium P-N Junction diode.

APPARATUS:

S.No Name of the Apparatus Range Quantity

1 Diodes IN 4007 (Germanium) 1

2 Resistors 1KΩ, 100Ω 1

3 Regulated Power Supply (0-30)V DC 1

4 Bread Board 1

5 Digital Ammeter (0-200)μA/(0-200)mA 1

6 Digital Voltmeter (0-20)V DC 1

7 Connecting Wires As Required

THEORY:-

A p-n junction diode conducts only in one direction. The V-I characteristics of the diode

are curve between voltage across the diode and current through the diode. When external voltage is

zero, circuit is open and the potential barrier does not allow the current to flow. Therefore, the

circuit current is zero. When P-type (Anode is connected to +ve terminal and n- type (cathode) is

connected to –ve terminal of the supply voltage, is known as forward bias. The potential barrier is

reduced when diode is in the forward biased condition. At some forward voltage, the potential

barrier altogether eliminated and current starts flowing through the diode and also in the circuit.

The diode is said to be in ON state. The current increases with increasing forward voltage.

When N-type (cathode) is connected to +ve terminal and P-type (Anode) is

connected to –ve terminal of the supply voltage is known as reverse bias and the potential barrier

Page 29: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

across the junction increases. Therefore, the junction resistance becomes very high and a very

small current (reverse saturation current) flows in the circuit. The diode is said to be in OFF state.

The reverse bias current due to minority charge carriers.

CIRCUIT DIAGRAM:

(i) FORWARD BIAS:

(ii) REVERSE BIAS:

Page 30: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

V-I CHARACTERISTICS:

PROCEDURE:

(i) FORWARD BIAS:

1. Connections are made as per the circuit diagram.

2. For forward bias, the RPS +ve is connected to the anode of the diode and RPS –ve is connected

to the cathode of the diode,

3. Switch ON the power supply and increases the input voltage (supply voltage) in Steps.

4. Note down the corresponding current flowing through the diode and voltage across the diode for

each and every step of the input voltage.

5. The readings of voltage and current are tabulated.

6. Graph is plotted between voltage on x-axis and current on y-axis.

Page 31: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

OBSERVATIONS:

S.No. Applied voltage

(volts)

Voltage across

Diode (volts)

Current through Diode (mA)

PROCEDURE:

(ii) REVERSE BIAS:

1. Connections are made as per the circuit diagram.

2. For reverse bias, the RPS +ve is connected to the cathode of the diode and RPS –ve is

connected to the anode of the diode.

3. Switch ON the power supply and increase the input voltage (supply voltage) in Steps.

4. Note down the corresponding current flowing through the diode and voltage across the diode for

each and every step of the input voltage.

5. The readings of voltage and current are tabulated.

6. The Graph is plotted between voltage on x-axis and current on y-axis.

OBSERVATIONS:

S.No. Applied voltage

(volts)

Voltage across

Diode (volts)

Current through Diode (µA)

Page 32: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

PRECAUTIONS:

1. While doing the experiment do not exceed the ratings of the diode. This may lead to

damage the diode.

2. Connect voltmeter and Ammeter in correct polarities as shown in the circuit diagram.

3. Do not switch ON the power supply unless you have checked the circuit connections as per

the circuit diagram.

CALCULATIONS:

1. Cut-in Voltage of ‘Ge’ diode is ___________________________

2. Forward Bias:

3. Reverse Bias:

RESULT: The Forward and Reverse Bias characteristics for a p-n diode are observed. The cut-in

voltage, static and dynamic resistances in both forward and reverse biased conditions for

Germanium P-N Junction diode are found.

i) The Cut-in voltage of ‘Ge’ Diode is____________________

ii) The Static forward resistance of ‘Ge’ Diode is___________________

iii) The Dynamic forward resistance of ‘Ge’ Diode is_________________

iv) The Static reverse resistance of ‘Ge’ Diode is___________________

v) The Dynamic reverse resistance of ‘Ge’ Diode is_________________

VIVA QUESTIONS:

1. Define depletion region of a diode?

2. What is meant by transition & space charge capacitance of a diode?

3. Is the V-I relationship of a diode Linear or Exponential?

Page 33: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

4. Define cut-in voltage of a diode and specify the values for Si and Ge diodes?

5. What are the applications of a p-n diode?

6. Draw the ideal characteristics of P-N junction diode?

7. What is the diode equation?

8. What is PIV?

9. What is the break down voltage?

10. What is the effect of temperature on PN junction diodes?

Page 34: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

Exp-8

ZENER DIODE CHARACTERISTICS AND VOLTAGE REGULATOR

AIM:

1. To observe and draw the V-I characteristics and Voltage regulator characteristics of a

Zener diode.

2. To find the Zener Break down voltage in reverse biased condition.

3. To find the Static and Dynamic resistances of Zener diode in both forward

and reverse biased conditions.

APPARATUS:

S.No Name of the Apparatus Range Quantity

1 Zener Diode (IN 4735A) 1

2 Resistors 1KΩ, 10KΩ 1

3 Regulated Power Supply (0-30)V DC 1

4 Bread Board 1

5 Digital Ammeter (0-200)mA 1

6 Digital Voltmeter (0-20)V DC 1

7 Connecting Wires As Required

CIRCUIT DIAGRAM:

(i) V-I CHARACTERISTICS:

Page 35: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

(ii) ZENER DIODE AS VOLTAGE REGULATOR:

THEORY:

A zener diode is heavily doped p-n junction diode, specially made to operate in

the break down region. A p-n junction diode normally does not conduct when reverse biased. But

if the reverse bias is increased, at a particular voltage it starts conducting heavily. This voltage is

called Break down Voltage. High current through the diode can permanently damage the device

To avoid high current, we connect a resistor in series with zener diode. Once the

diode starts conducting it maintains almost constant voltage across the terminals what ever may

be the current through it, i.e., it has very low dynamic resistance. It is used in voltage regulators.

PROCEDURE:

Page 36: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

(i) V-I CHARACTERISTICS:

1. Connections are made as per the circuit diagram.

2. The Regulated power supply voltage is increased in steps.

3. The zener current (lz), and the zener voltage (Vz.) are observed and then noted in the

tabular form.

4. A graph is plotted between zener current (Iz) on y-axis and zener voltage (Vz) on x-axis.

(ii) ZENER DIODE AS VOLTAGE REGULATOR:

1. Connections are made as per the circuit diagram.

2. The Regulated power supply voltage is increased in steps.

3. The voltage across the diode (Vz.) remains almost constant although the current through

the diode increases. This voltage serves as reference voltage.

4. The zener current (lz), and the zener voltage (Vz.) are observed and then noted in the

tabular form.

4. A graph is plotted between zener current (Iz) on y-axis and zener voltage (Vz) on x-axis.

OBSERVATIONS:

(i) V-I CHARACTERISTICS:

S.No Zener Voltage (VZ)

(volts)

Zener Current (IZ) (mA)

Page 37: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

(ii) ZENER DIODE AS VOLTAGE REGULATOR:

S.No Zener Voltage (VZ)

(volts)

Zener Current (IZ) (mA)

V-I & VOLTAGE REGULATOR CHARACTERISTICS:

PRECAUTIONS:

1. While doing the experiment do not exceed the ratings of the zener diode. This may lead to

damage the diode.

Page 38: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

2. Connect voltmeter and Ammeter in correct polarities as shown in the circuit diagram.

3. Do not switch ON the power supply unless you have checked the circuit connections as per the

circuit diagram.

CALCULATIONS:

1. Zener Break down Voltage is ___________________________

2. Forward Bias:

3. Reverse Bias:

RESULT: The V-I characteristics and Voltage regulator characteristics of a zener diode are

observed.

The Zener Break down voltage in reverse biased condition, Static and Dynamic resistances of

Zener diode in both forward and reverse biased conditions are calculated.

i) The Zener Break down voltage is_____________________

ii) The Static foward resistance of Zener Diode is___________________

iii) The Dynamic forward resistance of Zener Diode is_________________

iv) The Static reverse resistance of Zener Diode is___________________

v) The Dynamic reverse resistance of Zener Diode is_________________

VIVA QUESTIONS:

1. What type of temperature Coefficient does the zener diode have?

2. If the impurity concentration is increased, how the depletion width effected?

3. Does the dynamic impendence of a zener diode vary?

4. Explain briefly about avalanche and zener breakdowns?

5. Draw the zener equivalent circuit?

6. Differentiate between line regulation & load regulation?

Page 39: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

7. In which region zener diode can be used as a regulator?

8. How the breakdown voltage of a particular diode can be controlled?

9. What type of temperature coefficient does the Avalanche breakdown has?

10. By what type of charge carriers the current flows in zener and avalanche breakdown diodes?

Page 40: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

Exp-9

HALF WAVE RECTIFIER

AIM:

1.To obtain the load regulation and ripple factor of a half-wave rectifier by using

(a). without Filter

(b). with Filter

2. To observe the input and output waveforms of a half-wave rectifier.

APPARATUS:

S.No Name of the Apparatus Range Quantity

1 Diodes IN 4007 (Si) 1

2 Decade Resistance Box (1KΩ -10 KΩ) 1

3 Transformer 230 V AC 1

4 Capacitor 100µF 1

5 Bread Board

6 Digital Voltmeter (0-20)V (AC & DC) 2

7 Connecting Wires As Required

THEORY:

During positive half-cycle of the input voltage, the diode D1 is in forward bias and

conducts through the load resistor R1. Hence the current produces an output voltage across the

load resistor R1, which has the same shape as the +ve half cycle of the input voltage.

During the negative half-cycle of the input voltage, the diode is reverse biased and there

is no current through the circuit. i.e, the voltage across R1 is zero. The net result is that only the

+ve half cycle of the input voltage appears across the load. The average value of the half wave

rectified o/p voltage is the value measured on dc voltmeter.

For practical circuits, transformer coupling is usually provided for two reasons.

1. The voltage can be stepped-up or stepped-down, as needed.

2. The ac source is electrically isolated from the rectifier. Thus preventing shock hazards

in the secondary circuit.

Page 41: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

CIRCUIT DIAGRAM:

(a) WITHOUT FILTER:

(b) WITH FILTER:

Page 42: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. Connect the primary side of the transformer to ac mains and the secondary side to the

rectifier input.

3. By using the multimeter, measure the ac input voltage of the rectifier and, ac and dc

voltage at the output of the rectifier.

4. Find the theoretical value of dc voltage by using the formula,

Vdc=Vm/П

Where, Vm=2Vrms, (Vrms=output ac voltage.)

Now, the Ripple factor is calculated by using the formula

Γ = ac output voltage (Vac)/dc output voltage (Vdc)

5. By increasing the value of the resistance from 1 KΩ to 10KΩ, the voltage across the load

(VL) and current (IL) flowing through the load are measured.

6. Draw a graph between load voltage (VL) and load current (IL) by taking VL on X-axis and

IL on y-axis.

7. From the value of no-load voltage (VNL) , the % regulation is to be calculated from the

theoretical calculations given below.

Page 43: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

INPUT AND OUTPUT WAVEFORMS:

THEORETICAL CALCULATIONS FOR RIPPLE FACTOR & % REGULATION:

(a) WITH OUT FILTER:

For a Half-Wave Rectifier,

Vrms=Vm/2

Page 44: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

Vdc=Vm/П

Therefore, Ripple factor Γ=√ (Vrms/ Vdc )2 -1 = 1.21

% regulation = [(VNL-VFL)/VFL]*100

(b) WITH FILTER:

Ripple factor for a Half-Wave Rectifier is Γ=1/ (2√3 fRC).

Where f =50Hz

C =100µF

R=(1-10)KΩ

Therefore, for 1KΩ, Ripple factor, Γ = 0.0577

% regulation = [(VNL-VFL)/VFL]*100

OBSERVATIONS:

(a) WITH OUT FILTER:

VNL =______V

S.No

Load

Resistance

(KΩ)

Vac(v)

Vdc(v)

Γ= Vac/ Vdc

% Regulation

Page 45: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

(b) WITH FILTER:

VNL =______V

S.No

Load

Resistance

(KΩ)

Vac(v)

Vdc(v)

Γ= Vac/ Vdc

% Regulation

PRECAUTIONS:

1. The primary and secondary sides of the transformer should be carefully identified.

2. The polarities of the diode should be carefully identified.

3. While determining the % regulation, first Full load should be applied and then it should be

decremented in steps.

RESULT:

The Ripple factor and the % regulation for the Half-Wave Rectifier with and without filters are

calculated.

1. The Ripple factor of Half-Wave Rectifier without filter is _____________________

2. The Ripple factor of Half-Wave Rectifier with filter is _____________________

3. The % Regulation of Half-Wave Rectifier without filter is _____________________

4. The % Regulation of Half-Wave Rectifier with filter is _____________________

Page 46: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

Exp-10

FULL WAVE RECTIFIER

AIM:

1. To obtain the load regulation and ripple factor of a full-wave rectifier by using

(a). without Filter

(b). with Filter

2. To observe the input and output waveforms of a full-wave rectifier.

APPARATUS:

S.No Name of the Apparatus Range Quantity

1 Diodes IN 4007 (Si) 2

2 Decade Resistance Box (1KΩ-10 KΩ) 1

3 Transformer 230 V AC 1

4 Capacitor 100µF 1

5 Bread Board

6 Digital Voltmeter (0-20)V (AC & DC) 2

7 Connecting Wires As Required

THEORY:

The circuit of a center-tapped full wave rectifier uses two diodes D1&D2. During

positive half cycle of secondary voltage (input voltage), the diode D1 is forward biased and D2is

reverse biased.

The diode D1 conducts and current flows through load resistor RL. During negative half

cycle, diode D2 becomes forward biased and D1 reverse biased. Now, D2 conducts and current

flows through the load resistor RL in the same direction. There is a continuous current flow

through the load resistor RL, during both the half cycles and will get unidirectional current as

show in the model graph. The difference between full wave and half wave rectification is that a

full wave rectifier allows unidirectional (one way) current to the load during the entire 360

degrees of the input signal and half-wave rectifier allows this only during one half cycle (180

degree).

Page 47: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

CIRCUIT DIAGRAM:

(a) WITHOUT FILTER:

(b) WITH FILTER:

Page 48: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. Connect the primary side of the transformer to ac mains and the secondary side to the

rectifier input.

3. By using the multimeter, measure the ac input voltage of the rectifier and, ac and dc

voltage at the output of the rectifier.

4. Find the theoretical value of dc voltage by using the formula,

Vdc=2Vm/П

Where, Vm= √2Vrms, (Vrms=output ac voltage.)

5. Now, the Ripple factor is calculated by using the formula

Γ = ac output voltage (Vac)/dc output voltage (Vdc)

6. By increasing the value of the resistance from 1 KΩ to 10KΩ, the voltage across the load

(VL) and current (IL) flowing through the load are measured.

7. Draw a graph between load voltage (VL) and load current (IL) by taking VL on X-axis and

IL on y-axis.

8. From the value of no-load voltage (VNL), the % regulation is to be calculated from the

theoretical calculations given below.

Page 49: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

INPUT AND OUTPUT WAVEFORMS:

Page 50: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

THEORETICAL CALCULATIONS FOR RIPPLE FACTOR & % REGULATION:

(a) WITHOUT FILTER:

For a Full-Wave Rectifier,

Vrms=Vm/√2

Vdc=2Vm/П

Therefore, Ripple factor Γ=√ (Vrms/ Vdc )2 -1 = 0.482

% regulation = [(VNL-VFL)/VFL]*100

(b) WITH FILTER:

Ripple factor for a Full-Wave Rectifier is Γ=1/ (2√3 fRC).

Where f =50Hz

C =100µF

R= (1-10) KΩ

Therefore, for 1KΩ, Ripple factor, Γ = 0.0577

% regulation = [(VNL-VFL)/VFL]*100

OBSERVATIONS:

(a) WITH OUT FILTER:

VNL =______V

S.No

Load

Resistance

(KΩ)

Vac(v)

Vdc(v)

Γ= Vac/ Vdc

% Regulation

Page 51: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

(b) WITH FILTER:

VNL =______V

S.No

Load

Resistance

(KΩ)

Vac(v)

Vdc(v)

Γ= Vac/ Vdc

% Regulation

PRECAUTIONS:

1. The primary and secondary sides of the transformer should be carefully identified.

2. The polarities of the diode should be carefully identified.

3. While determining the % regulation, first Full load should be applied and then it should be

decremented in steps.

RESULT:

The Ripple factor and the % regulation for the Full-Wave Rectifier with and without filters are

calculated.

1. The Ripple factor of Full-Wave Rectifier without filter is _____________________

2. The Ripple factor of Full-Wave Rectifier with filter is _____________________

3. The % Regulation of Full-Wave Rectifier without filter is _____________________

4. The % Regulation of Full-Wave Rectifier with filter is _____________________

Page 52: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

VIVA QUESTIONS:

1. What is the PIV of Half wave rectifier?

2. What is the efficiency of half wave rectifier?

3. What is a rectifier?

4. What is the difference between the half wave rectifier and full wave Rectifier?

5. What is the output frequency of Bridge Rectifier?

6. What are the ripples?

7. What is the function of a filter?

8. What is TUF?

9. What is the average value of output voltage for a HWR?

10. What is the peak factor?

Page 53: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

Exp-11

TRANSISTOR CE CHARACTERISTICS

AIM:

1. To draw the input and output characteristics of transistor connected in CE

Configuration

2. To find Input Resistance (Ri), Output Resistance (Ro) and Current amplification

Factor (β) of the given transistor.

APPARATUS:

S.No Name of the Apparatus Range Quantity

1 Transistor (BC-107) 1

2 Resistors 1KΩ, 470Ω 1

3 Regulated Power Supply (0-30)V DC 1

4 Bread Board 1

5 Digital Ammeters (0-200)μA/(0-200)mA 2

6 Digital Voltmeters (0-20)V DC 2

7 Connecting Wires As Required

THEORY:

A transistor is a three terminal device. The terminals are emitter, base, collector. In

common emitter configuration, input voltage is applied between base and emitter terminals and

out put is taken across the collector and emitter terminals. Therefore the emitter terminal is

common to both input and output.

The input characteristics resemble that of a forward biased diode curve. This is

expected since the Base-Emitter junction of the transistor is forward biased. As compared to CB

arrangement IB increases less rapidly with VBE. Therefore input resistance of CE circuit is higher

than that of CB circuit.

The output characteristics are drawn between Ic and VCE at constant IB. the collector

current varies with VCE unto few volts only. After this the collector current becomes almost

constant, and independent of VCE. The value of VCE up to which the collector current changes

with V CE is known as Knee voltage. The transistor always operated in the region above Knee

Page 54: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

voltage, IC is always constant and is approximately equal to IB. The current amplification factor

of CE configuration is given by β = ΔIC/ΔIB

CIRCUIT DIAGRAM:

PROCEDURE:

(i) INPUT CHARACTERSTICS:

1. Connect the circuit as per the circuit diagram.

2. For plotting the input characteristics the output voltage VCE is kept constant at 1V and for

different values of VBE, note down the values of IB.

3. Repeat the above step by keeping VCE at 2V and 3V.

4. Tabulate all the readings.

5. Plot the graph between VBE on x-axis and IB on y-axis for constant VCE.

(ii) OUTPUT CHARACTERSTICS:

1. Connect the circuit as per the circuit diagram.

2. For plotting the output characteristics the input current IB is kept constant at 50μA and for

different values of VCE, note down the values of IC.

3. Repeat the above step by keeping IB at 75μA and 100μA.

4. Tabulate the all the readings.

5. Plot the graph between VCE on x-axis and IC on y-axis for constant IB.

Page 55: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

OBSERVATIONS:

(i) INPUT CHARACTERISTICS:

S.No

VCE = 1V VCE = 2V VCE = 3V

VBE (V) IB (μA) VBE (V) IB (μA) VBE (V) IB (μA)

(ii) OUTPUT CHARACTERISTICS:

S.No

IB = 50 μA IB = 75 μA IB = 100 μA

VCE (V) IC (mA) VCE (V) IC( mA) VCE(V) IC (mA)

Page 56: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

MODEL GRAPH:

(i) INPUT CHARACTERISTICS:

(ii) OUTPUT CHARACTERISTICS:

Page 57: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

PRECAUTIONS:

1. While doing the experiment do not exceed the ratings of the transistor. This may lead

to damage the transistor.

2. Connect voltmeter and Ammeter in correct polarities as shown in the circuit diagram.

3. Do not switch ON the power supply unless you have checked the circuit connections

as per the circuit diagram.

4. Make sure while selecting the emitter, base and collector terminals of the transistor.

CALCULATIONS:

1. Input resistance: To obtain input resistance find ΔVBE and ΔIB at constant VCE on one

of the input characteristics. Then

Ri = ΔVBE / ΔIB (VCE constant)

2. Output resistance: To obtain output resistance, find ΔIC and ΔVCE at constant IB.

Ro = ΔVCE / ΔIC (IB constant)

3. The current amplification factor of CE configuration is given by

β = ΔIC/ΔIB

Page 58: CHADALAWADA RAMANAMMA ENGINEERING COLLEGE LAB...PART- A : ELECTRICAL LAB Expt. 1 Verification of Superposition Theorem. Expt. 2 Verification of Thevenin’s Theorem. Expt. 3 Determination

RESULT: The input and output characteristics of a transistor in CE configuration are drawn.

The Input (Ri) and Output resistances (Ro) and of a given transistor are calculated.

1. The Input resistance (Ri) of a given Transistor is______________

2. The Output resistance (Ro) of a given Transistor is____________

3. The Current amplification factor is_________________________

VIVA QUESTIONS:

1. What is the range of for the transistor?

2. What are the input and output impedances of CE configuration?

3. Identify various regions in the output characteristics?

4. What is the relation between and ?

5. Define current gain in CE configuration?

6. What is the phase relation between input and output?

7. Draw diagram of CE configuration for PNP transistor?

8. What is the power gain of CE configuration?

9. What are the applications of CE configuration?