Ch3b- 2 EE/CS/CPE 3760 - Computer Organization Seattle Pacific University There is logic to it andRd, Rs, RtRd

Ch3b- 2EE/CS/CPE 3760 - Computer OrganizationSeattle Pacific University

There is logic to itand Rd, Rs, Rt Rd <-- Rs • Rtor Rd, Rs, Rt Rd <-- Rs Rt

AND, OR are bitwise logic operations

0010 0011 0111 0110 1010 1111 0000 1101 OR 1001 1010 1000 0101 0001 1011 1010 0011

Example: Set bit 7 of $s9 to ‘1’ (Don’t mess with the other 31 bits)

ori $s9, $s9, 0x0080 0x0080 = 0000 0000 1000 0000

Example: Clear bit 14 of $t3 to ‘0’

andi $t3, $t3, 0xBFFF 0xBFFF = 1011 1111 1111 1111

Note: Bit numberingstarts at zero.

Note: Bit numberingstarts at zero.

1011 1011 1111 0111 1011 1111 1010 1111


Shifty InstructionsShift instructions scoot all the bits in a register over

sll $s3, $t2, 1 # $s3 <-- $t2 shifted left 1 bit

0010 0011 0111 0110 1010 1111 0000 1101$t2

0100 0110 1110 1101 0101 1110 0001 101 $s3

Old MSB: Bit-bucketedOld MSB: Bit-bucketed

New LSB: ZeroNew LSB: Zero

srl $t3, $s4, 5 # $t3 <-- $s4 right shifted 5 bits

0

Opcode RS RT RD ShAmt Function R-Type InstructionR-Type Instruction

0


Using Shifts1. You need only the 2nd byte of a 4-byte word

srl $t1, $t1, 8

0010 0011 0111 0110 1010 1111 0000 1101$t1

0000 0000 0010 0011 0111 0110 1010 1111$t1

andi $t1, $t1, 0x00FF

0000 0000 0000 0000 0000 0000 1010 1111$t1

2. You want to multiply $t3 by 8 (note: 8 equals 23)

0000 0000 0000 0000 0000 0000 0000 0101$t3

sll $t3, $t3, 3 # move 3 places to the left

0000 0000 0000 0000 0000 0000 0010 1000$t3

(equals 5)

(equals 40)

To access only part of a word, we need the bits on the RHS

8

0000 0000 0000 0000 0000 0000 1111 1111Note - extended with 16 0’s

Must isolate only the 8 bits on RHS


Arithmetic and Logic Unit

• The ALU is at the heart of the CPU

• Does math and logic

• The ALU is primarily involved in R-type instructions

• Perform an operation on two registers and produce a result

• Where is the operation specified?

• The instruction type specifies the operation

• The ALU will have to be controlled by the instruction opcode


Constructing an ALU - Logic Operations

0

1

A

B

Operation

Result

2-to-1 Mux

If Operation = 0, Result = A • BIf Operation = 1, Result = A B

Start out by supporting AND and OR operations

AB

A+B

Two operands, two results.We need only one result...

The Operation input comes from logic that looks at the opcode


Half Adder

Ai 0 0 1 1

Sum 0 1 1 0

CarryOut0 0 0 1

1

Bi 0

0 1

Sum = Ai Bi Ai Bi

= Ai Bi

CarryOut = Ai Bi

CarryOut

Sum A i

B i

+

A half adder adds two bits, A and Band produces a Sum and CarryOut

Sum

CarryOut

A i

B i

Problem: We often need to add two bits and a CarryIn...


Full Adder

B

AB00 01 11 10

0

1

A

Cin

Cout

0

0

0

1

1

1

0

1

B

AB00 01 11 10

0

1

A

Cin

Sum

0

1

1

0

0

1

1

0

Cout = Sum = A B Cin

+B1

A1

Sum

CarryOut

CarryIn

A full adder adds two bits, A and B, and a CarryIn and produces a Sum and CarryOut

A B Cin Cout Sum

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

BCin ACinAB


Adding to our ALU

CarryIn

CarryOut

ALUA

B

Cout

Cin

ResultCin

Cout

Op (2 bits)

Operation Function00 A • B01 A B10 A + B

Operation Function00 A • B01 A B10 A + B

+

(Op is now 2 bits)

Add an Adder

Connect CarryIn (from previous bit) and CarryOut (to next bit)

Expand Mux to 3-to-1 (Op is now 2 bits)

0

1

Operation

Result

A

B2

0

1

Ch3b- 10

EE/CS/CPE 3760 - Computer OrganizationSeattle Pacific University

Putting it all together Cin

A0

B0

Result0ALU0

Cin

Cout

Operation

A1

B1

Result1ALU1

Cin

Cout

A2

B2

Result2ALU2

Cin

Cout

A31

B31

Result31ALU31

Cin

Cout

Cout

• Connect to common Operation controls

• Now we can do 32-bit AND and OR operations

• Stack 32 of our 1-bit ALU’s together

• Each one gets one bit from A and one from B

• Connect Cout’s to Cin’s

• Now, 32-bit adds will work

• Note: Carry will ripple through the stages, one at a time• Ripple-Carry Adder

Ch3b- 11


Subtracting

0

1B

0

1

A

Operation

Result

+ 2

CarryIn

CarryOut

BInvert

For subtraction: Set CarryIn of LSB to 1,

Set BInvert to 1

For subtraction: Set CarryIn of LSB to 1,

Set BInvert to 1

• Add an inverter, and a signal BInvert to get B

• Now, how about that +1?

• CarryIn to LSB is unused (always zero)

• Set it to 1!

• Subtraction just sets BInvert and Cin to 1

B

• Our ALU can add now, but what about subtraction?

• To compute A - B, we can instead compute A + (-B)• In 2’s complement, -B = B + 1

Set to 1 for LSB

Ch3b- 12


Support for SLT

• A<B is equivalent to (A - B) < 0

• Subtract B from A

• If the result is negative, then set LSB of Result to ‘1’, all others to ‘0’

• The result is negative if the MSB after the subtraction is ‘1’ (Two’s complement)

Result

0

1

A

Operation

+ 2B

CarryIn

CarryOut

0

1

BInvert

Less

We’re going to have to do something differentfor the MSB and the LSB

We’re going to have to do something differentfor the MSB and the LSB

• We need to support the SLT operation

• Set Result to 0000 0000 0000 0000 0000 0000 0000 0001 if A <B

0

1

2

3

Less will be ‘0’ for bits 1-31, special for bit 0

Ch3b- 13


That tricky MSB• To properly execute the

SLT, we need to Set the LSB if the MSB is ‘1’

• (After a subtraction)

OverFlow

Set

0

1

A

Operation

Result

+ 2B

CarryIn

CarryOut

0

1

BInvert

3Less

MSB OnlyMSB Only

• Can’t use the ‘Result’ of the MSB

• Op will set the Mux to the ‘Less’ Field

• Bring out the adder output directly: ‘Set’

• Also, we need to check for overflow

• Overflow if Cin to MSB is different from Cout of MSB

Ch3b- 14


Cin Operation

Cout

• Our new and improved 32-bit ALU

The Whole Thing BInvert

0ALU31

Result31CinA31B31

Cout

LessOverFlow

Set

• Add the BInvert control to each bit

• Connect ‘Set’ output of MSB to ‘Less’ Input of LSB

• Set the LSB during SLT when negative

• Output OverFlow from MSB

ALU0

A0B0 Result0

Cin

LessCout

0B2 ALU2

Result2

CinA2

LessCout

0ALU1

Result1

A1B1

Cout

Less

Cin

• Connect ‘0’ to all the Less inputs except LSB

Ch3b- 15


One LastChange

Zero

A

B

ZeroResultOverFlow

Operation

Cout

Result2

Result1

Cin Operation

Cout

BInvert

0OverFlow

Set

0

0

ALU31

Result31Cin

A31B31

Cout

Less

ALU0

A0B0

Result0Cin

LessCout

B2 ALU2

CinA2

LessCout

ALU1

A1B1

Cout

Less

Cin

We need to add a checkto see if the result is zero

Ch3b- 16


ALU FunctionsFunction BInv Op Carryin Result

And 0 00 0 R = A • BOr 0 01 0 R = A BAdd 0 10 0 R = A + BSubtract 1 10 1 R = A - BSLT 1 11 1 R = 1 if A < B

0 if A B

Function BInv Op Carryin Result

And 0 00 0 R = A • BOr 0 01 0 R = A BAdd 0 10 0 R = A + BSubtract 1 10 1 R = A - BSLT 1 11 1 R = 1 if A < B

0 if A B

0

1

A

Operation

Result

+ 2B

CarryIn

CarryOut

0

1

BInvert

3Less

We also have zero-detect for BEQ,BNE (use subtract).

We also have zero-detect for BEQ,BNE (use subtract).

Skipping over Shift operations...Skipping over Shift operations...

Note: Adding would be a lot faster if we didn’t use a ripple-carry adder...

Note: Adding would be a lot faster if we didn’t use a ripple-carry adder...

Since Binvert and Carryin are always the same, we can combine them in to a single signal subtract

Since Binvert and Carryin are always the same, we can combine them in to a single signal subtract

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Ch3b- 2 EE/CS/CPE 3760 - Computer Organization Seattle Pacific University There is logic to it andRd, Rs, RtRd