Ch3 Lec3 Sameer Akram

8/7/2019 Ch3 Lec3 Sameer Akram

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Lecture 3 on Chapter 3

A Top-Level View of Computer

Function and Interconnection

by Sameer Akram


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Interconnection Structures

Computer set of components or modules of threebasic types (Processor, I/O, Memory) thatcommunicate with each other.

All the units must be connected.

The collection of paths connecting the variousmodules is called the Interconnection Structure.

Different type of connection for different type of

unit Memory

Input/Output

CPU


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Computer Modules


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Memory Connection

Receives and sends data

Receives addresses (of locations)

Receives control signals

Read

Write


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Input/Output Connection(1)

Output Receive data from computer

Send data to peripheral

Input

Receive data from peripheral

Send data to computer


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Input/Output Connection(2)

Receive control signals from computer

Send control signals to peripherals

e.g. spin disk

Receive addresses from computer

e.g. port number to identify peripheral

Port: Interface to an external device is referredto as port. Each port is assigned a uniqueaddress/number.

Send interrupt signals (control)


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CPU Connection

Reads instruction and data

Writes out data (after processing)

Sends control signals to other units

Receives (& acts on) interrupts


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Buses

There are a number of possible interconnection systems Memory to Processor

Processor to Memory

I/O to Processor

Processor to I/O I/O to or from Memory: For these two cases, an I/O

module is allowed to exchange data directly withmemory, without going through the processor, usingdirect memory access (DMA)

Single and multiple BUS structures are most common

Unibus (DEC-PDP)


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Bus

A communication pathway connecting two or moredevices.

Shared Transmission Medium

Usually Broadcast: Multiple devices connect to the

bus and a signal transmitted by any one device isavailable for reception by all other devices attachedto the bus.

Often grouped

A number of channels in one bus

e.g. 32 bit data bus is 32 separate single bitchannels


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System Bus

A Bus that connects major computer components(processor, I/O, memory) is called a System Bus.

Most common computer interconnection structuresare based on the use of one or more system buses.

A System Bus consists, typically, of from about 50to hundreds of separate lines. Each line is assigneda particular meaning or function.

On any bus the lines can be classified into three

functional groups Data

Address

Control


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Address Bus

Identify the source or destination of data.

e.g. CPU needs to read an instruction (data) from agiven location in memory

Address bus width determines maximum memorycapacity of system

e.g. 8080 has 16 bit address bus giving 64kaddress space


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Control Bus

Control Lines are used to control the access to andthe use of the data and address lines.

Because Data and Address Lines are shared by allcomponents; there must be a means of controlling

their use. Control and timing information

Memory Read / Write signal

I/O Read / Write signal

Transfer ACK

Bus request

Interrupt request

Clock signals


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Control Bus

Typical Control Lines include the following signals: Memory Read

Memory Write

I/O Read

I/O Write Transfer ACK

Bus request

Bus grant

Interrupt request Interrupt ACK

Clock signals: used to synchronize operations.

Reset: Initializes all modules.


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Bus Interconnection Scheme


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What do Buses look like?

What do buses look like?

Parallel lines on circuit boards

Ribbon cables

Strip connectors on mother boards

e.g. PCI

Sets of wires


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Single Bus Problems

Lots of devices on one bus leads to: Propagation delays

Long data paths mean that co-ordination ofbus use can adversely affect performance

If aggregate data transfer approaches buscapacity

Most systems use multiple buses to overcome

these problems


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Multiple Buses

Traditional (ISA) (with cache)


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High Performance Bus [Mezzanine Architecture]


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Elements ofBus Design

Bus Type Dedicated

Multiplexed

Method of Arbitration

Centralized Distributed

Timing

Synchronous

Asynchronous Bus Width

Address

Data


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Elements ofBus Design

Data Transfer Type

Read

Write

Read-modify-write Read-after-write

Block


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Bus Types

DedicatedA dedicated bus line is permanently assigned either

to one function or to a physical subset of computercomponents.

An example of functional dedication is the use ofseparate dedicated data and address lines.

However it is not essential.


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Bus Types

Multiplexed Bus Type [Time Multiplexing]Address and Data information may be transmitted

over the same set of lines using an Address ValidControl Line.

At the beginning of a data transfer, the address isplaced on the bus and the Address Valid line isactivated.

At this point each module has a specified period oftime to copy the address and determine if it is the

addressed module. The address is then removed from the bus, and the

same bus connections are used for the subsequentread or write data transfer.

This method is known as Time Multiplexing.


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Bus Types

Multiplexed[Time Multiplexing]

Advantages

Fewer lines

Saves space and cost

Disadvantages More complex control

Potential reduction in performance; Becausecertain events that share the same lines cannot

take place in parallel.


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Bus Arbitration

More than one module may need control of the bus. For example, CPU and DMA controller

An I/O module may need to read or write directly tomemory, without sending data to the processor.

Because only one module can control bus at one time,some method of arbitration is needed.

Arbitration may

Centralized

Distributed


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Centralised Arbitration

Single hardware device controlling bus access controllogic

Bus Controller

Arbiter

May be part of CPU or separate.

Responsible for allocating time on Bus.


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Distributed Arbitration

No central controller

Each module may claim the bus.

Control logic exist on all modules.

Modules act together to share the bus.

With both methods of arbitration, the purpose is todesignate one device, either processor or an I/O

module, as master. The master may then initiate a datatransfer with some other device, which acts as slave forthis particular exchange.


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Timing

Timing : Co-ordination of events on bus Synchronous

Events determined by clock signals

Control Bus includes clock line upon which a clock

transmits a regular sequence of alternating 1s and 0sof equal duration.

A single 1-0 transmission is referred to as a clockcycle or bus cycle and defines a time slot.

All devices can read clock line.

Usually sync on leading edge

Usually a single cycle for an event


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Synchronous Timing Diagram


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Synchronous Timing Diagram

Processor places a memory address on the address linesduring the first clock cycle and may assert status lines.

Once the address lines have been stabilized, theprocessor issues an address enable signal.

For a read operation, the processor issues a readcommand at the start of the second cycle.

A memory module recognizes the address and after adelay of one cycle, places the data on the data lines.

For a write operation, the processor puts the data onthe data lines, at the start of second cycle and issues awrite command after the data lines have been stabilized.

The memory module copies the information from thedata lines during the third clock cycle.


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Asynchronous Timing Read Diagram


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Asynchronous Timing Read Diagram

With Asynchronous Timing, the occurrence of one eventon a bus follows and depends on the occurrence of aprevious event.

Processor places address and status signals on the bus.

After pausing for these signals to stabilize, it issues aread command, indicating the presence of valid addressand control signals.

The appropriate memory decodes the address andresponds by placing the data on the data line.

The memory module asserts acknowledge line to signalthe processor that the data are available.

Once the master has read the data from the data lines,it deasserts the read signal.


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Asynchronous Timing Write Diagram


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Asynchronous Timing Write Diagram

In this case, the master places data on the data line atthe same time that it puts signals on the status andaddress lines.

The memory module responds to the write command bycopying the data from the data lines and then asserting

the acknowledge line. Then master drops the write signal and the memory

module drops the acknowledge signal.


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Bus Width

The wider the data bus, the greater the number of bitstransferred at one time.

The wider the address bus, the greater the range oflocations that can be referenced.


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Data Transfer Type

Data Transfer Type

Read

Write

Read-modify-write Read-after-write

Block


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PCI Bus

Peripheral Component Interconnection. Can function as a mezzanine or peripheral bus.

Intel released to public domain in 1990.

PCI delivers better system performance forhigh-speed I/O subsystems [Graphic Display

Adapters, Network Interface Cards, DiskControllers etc]

Current Version PCI 2.2 32 or 64 bit

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Ch3 Lec3 Sameer Akram