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Introduction - Chapter 1

Text Book:

Silicon VLSI Technology,

Modeling. . , . . ,and P. B. Griffin

SILICON VLSI TECHNOLOGY

Fundamentals, Practice and Modeling

By Plummer, Deal & Griffin

© 2000 by Prentice Hall

Upper Saddle River NJ

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INTRODUCTION - Chapter 1

,

the technologies used to manufacture ICs.

• We will place a special emphasis on computer

simulation tools to help understand these processes.

• some technology areas than in others, but in all areasthey have made tremendous progress in recent






years.

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• an n egra e c rcu s.• Progress due to: Feature size reduction - 0.7X/3 years (Moore’s Law).

Increasing chip size - ≈ 16% per year.

“Creativit ” in im lementin functions.






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Semiconductor Progress

, ,

layer depth, layer-to-layer tolerances), power peractive component, operating voltage

• Increasing: chip size, wafer size, circuit density,, ,

• cycle






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Device Scaling Over Time

100µm

Feature Size

Cell dimensions10µmEra of Simple Scaling

1µm

0.1µm130 nm in 2002

Scaling + Innovation

(ITRS)

10nm Transition Region18 nm in 2018

Invention

0.1nm

1nm Quantum Effects Dominate

Atomic Dimensions

• The era of “easy” scaling is over. We are now in a period where

technology and device innovations are required. Beyond 2020, new

1960 1980 2000 2020 2040 Year






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currently unknown inventions will be required.

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Year of Production 1998 2000 2002 2004 2007 2010 2013 2016 2018

Technology Node (half pitch) 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 18 nmMPU Printed Gate Length 100 nm 70 nm 53 nm 35 nm 25 nm 18 nm 13 nm 10 nm

DRAM Bits/Chip (Sampling) 256M 512M 1G 4G 16G 32G 64G 128G 128G

MPU Transistors/Chip (x106) 550 1100 2200 4400 8800 14,000

Min Su l Volta e volts 1.8-2.5 1.5-1.8 1.2-1.5 0.9-1.2 0.8-1.1 0.7-1-0 06-0.9 0.5-0.8 0.5-0.7

ITRS at http://public.itrs.net/ (2003 version + 2004 update) – on class website.

• Assumes CMOS technolo dominates over entire roadma .• 2 year cycle moving to 3 years (scaling + innovation now required).

• 1990 IBM demo of Å scale “lithography”.• Technology appears to be capable of making structures much smaller than

SILICON VLSI TECHNOLOGYFundamentals, Practice and Modeling




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currently known device limits.

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Intel – From Sand to Silicon

• http://www.intel.com/pressroom/kits/chipmaking/

–





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Linewidth vs. Fab Cost

10000

)

Fab Cost ($M)

Linewidth (nm)

100

1000

F a b

C o s t ( $ M

L i n e

w i d t h ( u m

1

10

.

100mm 150mm 200mm 300mm 450mm

1975 1980 1985 1990 1995 2000 2005 2010 2015 2020 2025

.

Advantages and Challenges Associated with the Introduction of 450mm Wafers :A position paper report

submitted b the ITRS Startin Materials Sub-TWG June 2005.





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http://public.itrs.net/papers.html

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Moore’s LawOn April 19, 1965 Electronics Magazine published a paper

by Gordon Moore in which he made a prediction about the

semicon uctor in ustry t at as ecome t e stu o egen .

“The number of transistors incorporated in a chip

will a roximatel double ever 24 months.”

Known as Moore's Law, his prediction has enabled

widespread proliferation of technology worldwide, and todayas ecome s or an or rap ec no og ca c ange.





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http://www.intel.com/pressroom/kits/events/moores_law_40th/index.htm?iid=tech_mooreslaw+body_presskit

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Historical Perspective

• Invention of the bipolar

transistor - 1947, Bell Labs.

• Shockley’s “creative failure”

methodology

N

P

N

P

N N

• Grown junction transistor

technology of the 1950s

N

PN NP





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N

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• Bardeen, Brattain and Shockley

– Point Contact Transistor in 1947 at Bell Laboratory

– Followed by the bipolar transistor

•

– J ack Kilby demonstrated in 1958

• Texas Instruments–

• Fairchild Semiconductor





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Physical Devices

• an po ar uncton rans stors

• Field Effect Transistors (FET)

– - -

– J unction FET (J FET)

• Others:– PN J unction

– Resistor

– Ca acito

– Photo-Diode and Photo-Transistor





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N

In

N

In • Alloy junction technology

of the 1950s.

NNP

P

N P N

N

P

N

N

• Double diffused transistor

technology of the 1950s.

PN

N

P





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N P

Si O2

N

P N

-

Fairchild, late 1950s).

• First “passivated” junctions.

P

N

N





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Photolitho ra h• Basic lithography process

– A l hotoresist

– Patterned exposure– Remove photoresist regions

Light–

– Strip remaining photoresist

Photoresist

Mask

Substrate

Film deposition Photoresist application

Deposited Film

Exposure

Etch mask





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Development Etching Resist removal

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Planar Integrated Circuit

• Patterning of multiple photoresist patterns andprocessing steps create a planar integrated circuit

– P regions

– N regions

– Metal Contact Holes Analog BJT

– Metal Pattern

Vsource Ground

Emitter

Base

Collector

P N PNP

Resistor Resistor





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N

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Planar Digital IC

• Complimentary Metal-Oxide-Semiconductor (CMOS)

– N-channel MOS Field Effect Transistors NMOS

– -

Mask Layers:

P-well

N-well

P+

N+

PNP+ P+ N+ N+

Gate

Contact

L1

L1-L2 via

P WellN Well

PMOS NMOS

L2-L3 via

L3 Thickness

Substrate: >500 um





P 17

Active Layer: < 1 um

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Multiple Metal Layers

• Metal Planarizationrequre or mu pe

metal layers– Metal De osition

– Patterning

– Fill Dielectric

–

– Contact vias

– Contact Deposition





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19

Silicon Technology Leadership and the New Scaling Paradigm

Mark Bohr, Intel Senior Fellow, Logic Technology Development

April 18, 2007

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Computer Simulation Tools (TCAD)

•

manufacturing can now be simulated.• Simulation is now used for:

– Designing new processes and devices.

– Exploring the limits of semiconductor devices and

technology (R&D).

– “Centering” manufacturing processes.

– Solving manufacturing problems (what-if?)





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• Simulation of an

advanced local

oxidation process.

photoresist exposure.





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BASIC DEVICE PHYSICS





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Challenges For The Future• Having a “roadmap” suggests that the future is well defined and there are

.

• The truth is that there are enormous technical hurdles to actually achievingthe forecasts of the roadmap. Scaling is no longer enough.

• 3 stages for future development:

“Technology Performance Boosters” Invention

c e

PolyGate

SidewallSpacer

Gate

Gate

• Spin-based devices

Substrate

Silicide

RchanSource Drain

S/D Ext S/D Ext

e e c r c

???• o ecu ar ev ces

• Rapid single flux quantum

• Quantum cellular automata

• Resonant tunneling devices

• Single electron devices

Materials/process innovations Beyond Si CMOS





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Device innovations

IN 5-15 YEARS

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Broader Impact of Silicon Technology

Tip on Stage Individual Actuator Part of 12 x 12 arrayCornell University

-1.0

-0.5

.-0.75V

-1.5V

-

1.25

V

-1V

- .

Source Drain

-2.0

-1.5

I d s

( A )

-2.25V

-2V

-1.75V

Gate

-3.0x10-6

- .

-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0

-2.5V Stanford, Cornell

• Many other applications e.g. MEMs and many new device structures e.g. carbo





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Dnano u e ev ces, a use as c s con ec no ogy or a r ca on.

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Summary of Key Ideas

• ICs are widely regarded as one of the key components of the information age.

• Basic inventions between 1945 and 1970 laid the foundation for today's

silicon industry.

• For more than 40 years, "Moore's Law" (a doubling of chip complexity every

2-3 years) has held true.

•

power consumption, high performance and flexible design options. Future

projections suggest these trends will continue at least 15 more years.

• Silicon technology has become a basic “toolset” for many areas of science and

engineering.

•

design for many years. CAD tools are now being used for technology design.

• Chapter 1 also contains some review information on semiconductor materials





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sem con uc or ev ces. ese op cs w e use u n a er c ap ers o e ex .

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