Centero VN220 HW Integration Application Note

8/11/2019 Centero VN220 HW Integration Application Note

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08-00023-01 Proprietary & ConfidentialNIVIS LLC

VersaNode 220 Hardware Integration

Application Note

Version1.2

Date: April 1, 2011


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08-00023-01 VN220 Hardware Integration Application Note v.1.2 2/46

Proprietary & ConfidentialNIVIS LLC

Table of Contents

1. Introduction ................................................................................................................................... 3

1.1 Purpose and Audience ................................................................................................................... 3

2. Pin-out and Interface Summary .................................................................................................... 4

3. VL10 Application .......................................................................................................................... 15

3.1 VL10 HART Modem Interface ...................................................................................................... 15

3.2 VL10 4-20 mA Input Connectivity ................................................................................................ 17

3.3 Additional VN220 Interfaces on the VL10 ................................................................................... 19

4. VS220 Application ........................................................................................................................ 24

4.1 VS220 HART Modem Interface .................................................................................................... 24

4.2 VS220 4-20 mA Input Connectivity .............................................................................................. 26

4.3 VS220 Input Power Options ........................................................................................................ 28

4.4 UART1 Alternate Connectivity ..................................................................................................... 29

4.5 Additional Interfaces on the VS220 ............................................................................................. 30

5. VN220 Power Supply Considerations .......................................................................................... 375.1 Maximum Ratings ........................................................................................................................ 37

5.2 Normal Operating Conditions ...................................................................................................... 37

6. VN220 Layout Information and Mechanical Drawings ................................................................ 38

7. Appendix A. VL10 HART Loop Board Reference Schematic ........................................................ 41

8. Appendix B. VS220 HART Development Board Reference Schematic ........................................ 43

9. Appendix C. Nivis HART Modem Daughter Board Reference Schematic .................................... 46


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1. Introduction

1.1 Purpose and Audience

The purpose of this document is to define the VN220 radio modems connectivity on Nivis dataacquisition boards and to provide the necessary data to achieve hardware integration of the VN220 and

these data acquisition boards with customer application processors. The document also provides

reference design information for customers who wish to purchase the VN220 separately from the Nivis

development kit in order to develop a different application.

By definition the VN220 is a wireless modem that is pre-loaded with the Nivis WirelessHART stack.


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2. Pin-out and Interface Summary

The following section presents the pin assignments of the VN220 as used on the VL10 and VS220 boards,

which are part of the Nivis HART development kit.

An external processing entity can communicate with the VN220 using a variety of methods depending

on the application. The UART1 port is used for serial firmware upload, and in some applications, it is

used to talk to the HART modem.

The VN220 is used in two applications in the Nivis HART development kit: the VL10 and the VS220. Nivis

VL10 is designed specifically for WirelessHART applications and enables customers to connect a variety

of 4-20mA devices in order to transmit temperature or other sensor data using the WirelessHART

standard to the customers Gateway. The VS220 is a development board designed specifically for

WirelessHART developers to enable fast product integration and development for industrial wireless

solutions.

Figure 1 shows the VN220 pin assignments. Table 1 shows the pin descriptions for the VL10 application,

and Table 2 shows the pin descriptions for the VS220 application.

Note: For minimum battery consumption, all unused GPIOs should be left unconnected.

Figure 1. VN220 Pin Assignments


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Table 1. Pin Definitions for VN220

No. Name Description Type Dir Comments

1 UART2-RTS UART2 Request to Send DIG I

Standard UART communication with flow

control. Connect this to UART RTS of application

processor.

2 UART2-CTS UART2 Clear to Send DIG O


control. Connect this to UART CTS of application

processor.

3 UART2-RXD UART2 Receive Data DIG I


control. Connect this to UART-TXD of application

processor.

4 UART2-TXD UART2 Transmit Data DIG O


control. Connect this UART-RXD of application

processor.

5 UART1-RTS UART1 Request to Send DIG I/OOptional connection to firmware load interface

or to HART Modem.

6 UART1-CTS UART1 Clear to Send DIG I/O Not used.

7 UART1-RXD UART1 Receive Data DIG I Standard UART communication.

8 UART1-TXD UART1 Transmit Data DIG O Standard UART communication.

9 I2C-SDA I2C bus DATA DIG I/O Not used.

10 I2C-SCL I2C bus CLOCK DIG I/O Not used.

11 TMR1 Timer 1 I/O DIG O

Turns the HART Modem on (0) or off (1). Note

that the auxiliary HART Carrier detector isalways on.

12 TMR0 Timer 0 I/O DIG I/O Not used.

13 SPI-SCK SPI Clock DIG O Standard SPI Communication.

14 SPI-MOSI SPI Data Out DIG O Standard SPI Communication.

15 SPI-MISO SPI Data In DIG I Standard SPI Communication.

16 SPI-SS SPI Slave Select DIG O Standard SPI Communication.

17 GND Ground N/A N/A Connect to Ground pin.

18 KBI0 Keyboard interface pin 0 DIG O Controls the red STATUS LED (D1).

19 RTC-FOUT 32768Hz RTC clock out DIG O Not Used

20 KBI6 Keyboard interface pin 6 DIG I

Used for Display Status button. Holding this pin

low for 1 second enables the STATUS LED for the

next 10 seconds.

21 KBI5 Keyboard interface pin 5 DIG I Power fail monitor input.


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22 GND Ground N/A N/A




26 RTC-INT-B Keyboard interface pin 7 DIG I

Wakeup input from the auxiliary HART Carrier

detector. Detects presence of a carrier on the

line using a very low power circuit (always on).


Boot switch input from SW5. If switch SW5 is

placed at position 1, the VN220 will see a logic

HIGH, and the ISA100 stack will be loaded. If

switch SW5 is at position 2, the VN220 will see a

logic LOW, the Wireless HART stack will be

loaded, and the board will boot from Flash Area

4.

28 KBI2 Keyboard interface pin 2 DIG O

Controls output enable of USB level translator.

The VN220 controls whether UART1 lines are

connected to the USB interface (Note2).


RDY_RADIO line. This signal is active low and is

used by the VN220 to indicate a ready-to-

receive state. It will be generated as a response

to the Application CPU WKU signal.


WKU_RADIO line. This signal is active high and is

used by the Application CPU to wake up the

VN220 CPU from hibernation and to signal theintention to communicate with the modem.

Keeping this line active will block the modem

from entering the low power mode (sleep).


32 ADC3 ADC pin 3 DIG I

Modem carrier detect signalthis is a valid

HART carrier detect signal from the HART

modem chip.

33 ADC2 ADC pin 2 DIG I/O Not used.



36ADC2-

VREFHADC2 reference, high pin Analog I

Set ADC2-VREFH to Low and ADC2-VREFL to

High and power the VN220 for a few seconds to

erase the flash. After erasing the f lash, set the

ADC2-VREFH to High and ADC2-VREFL to Low.

WARNING: this operation will erase the Nivis

Bootloader and all manufacturing and


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non-volatile data!

37ADC2-

VREFLADC2 reference, low pin Analog I See the comments for ADC2-VREFH


39 VCC Supply voltage N/A N/AConnect this pin to regulated power supply VCC.

(+3V < Vcc


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Table 2. Pin Definitions for VL10 Application


1 UART2-RTS UART2 Request to Send DIG O

Digital output from the VN220 used for HART

Modem UART communication. 1-Modem

receive, 0-Modem transmit (Note1).

2 UART2-CTS UART2 Clear to Send DIG I/O Not Used (Note1).


Digital data output of the HART modems

demodulator and an input to the VN220s

UART2 RX line (Note1).


Digital data input to the HART modems

modulator and an output from the VN220s

UART2 TX line (Note1).

5 UART1-RTS UART1 Request to Send DIG IStandard UART communication with flow

control.

6 UART1-CTS UART1 Clear to Send DIG OStandard UART communication with flow

control.


Standard UART communication. Used for

upgrading the firmware of the VN220. TTL

RS232 level shifters should be employed when

connecting to RS232 port.


Standard UART communication. Used for

upgrading the firmware of the VN220. TTL

RS232 level shifters should be employed when

connecting to RS232 port.

9 I2C-SDA I2C bus DATA DIG I/O Communicates with A-D Converter.

10 I2C-SCL I2C bus CLOCK DIG I/O Communicates with A-D Converter.

11 TMR1 Timer 1 I/O DIG I/O Not used.

12 TMR0 Timer 0 I/O DIG I/O Not Used

13 SPI-SCK SPI Clock DIG I/O Not Used.

14 SPI-MOSI SPI Data Out DIG I/O Not Used

15 SPI-MISO SPI Data In DIG I/O Not Used

16 SPI-SS SPI Slave Select DIG I/O Not Used




that the auxiliary HART Carrier detector is

always on.



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next 10 seconds.






26 RTC-INT-BRTC wake-up interrupt /

Keyboard interface pin 7DIG I Not Used

27 KBI1 Keyboard interface pin 1 DIG O Not Used








32 ADC3 ADC pin 3 DIG I Not Used

33 ADC2 ADC pin 2 DIG O

Used for power conservationwhen in logical 0

turns off the 2.5V reference and the amplifier

for the A-D converter.

34 ADC1 ADC pin 1 DIG O Controls STATUS LED.




modem chip.

36ADC2-








non-volatile data!

37ADC2-

VREFLADC2 reference, low pin Analog I See the comments for ADC2-VREFH.


39 VCC Supply voltage N/A N/A Connect this pin to regulated power supply VCC.


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(+3V < Vcc


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Table 3. Pin Definitions for VS220 Application


1 UART2-RTS UART2 Request to Send DIG I


control. Supports communication using the Nivis

Simple API. Connect this to UART RTS of the

application processor.

2 UART2-CTS UART2 Clear to Send DIG O


control. Supports communication using the Nivis

Simple API. Connect this to UART CTS of the

application processor.



control. Connect this to UART-TXD of application

processor. Supports communication using the

Nivis Simple API.



control. Connect this UART-RXD of application

processor. Supports communication using the

Nivis Simple API.

5 UART1-RTS UART1 Request to Send DIG I/OOptional connection to firmware load interface

(USB or J14), or to HART Modem (Note2).

6 UART1-CTS UART1 Clear to Send DIG O Temp/Humidity Sensor interface (CLK out).

7 UART1-RXD UART1 Receive Data DIG I Standard UART communication (Note 2).

8 UART1-TXD UART1 Transmit Data DIG O Standard UART communication (Note 2).

9 I2C-SDA I2C bus DATA DIG I/OCommunicates with external A-D Converter

(Data I/O).

10 I2C-SCL I2C bus CLOCK DIG OCommunicates with external A-D Converter

(Clk out).



that the auxiliary HART Carrier detector is

always on.


Used for power conservationwhen in logical 0

turns off the 2.5V reference and the amplifier

for the A-D converter.

13 SPI-SCK SPI Clock DIG O

Connects to standard 10 pin header for SPI

communication using Nivis API.

14 SPI-MOSI SPI Data Out DIG OConnects to standard 10 pin header for SPI


15 SPI-MISO SPI Data In DIG IConnects to standard 10 pin header for SPI


16 SPI-SS SPI Slave Select DIG O Connects to standard 10 pin header for SPI


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18 KBI0 Keyboard interface pin 0 DIG O Controls the red STATUS LED (D1).





next 10 seconds.






26 RTC-INT-B Keyboard interface pin 7 DIG I





Boot switch input from SW5. If switch SW5 is

placed at position 1, the VN220 will see a logic

HIGH, and the ISA100 stack will be loaded. If

switch SW5 is at position 2, the VN220 will see a

logic LOW, the Wireless HART stack will be

loaded, and the board will boot from Flash Area

4.


Controls output enable of USB level translator.

The VN220 controls whether UART1 lines are

connected to the USB interface (Note2).


RDY_RADIO line. This signal is active low and is

used by the VN220 to indicate a ready-to-

receive state. It will be generated as a response

to the Application CPU WKU signal.


WKU_RADIO line. This signal is active high and is

used by the Application CPU to wake up the

VN220 CPU from hibernation and to signal the

intention to communicate with the modem.

Keeping this line active will block the modem

from entering the low power mode (sleep).





modem chip.


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33 ADC2 ADC pin 2 DIG OUsed for power conservationwhen in logical 0

turns off the Temp/Humidity sensor.

34 ADC1 ADC pin 1 DIG O Controls the green D3 LED.

35 ADC0 ADC pin 0 DIG I/O Temp/Humidity Sensor interface (Data I/O).

36ADC2-








non-volatile data!

37ADC2-

VREFLADC2 reference, low pin Analog I See the comments for ADC2-VREFH


39 VCC Supply voltage N/A N/AConnect this pin to regulated power supply VCC.

(+3V < Vcc


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Note 2: On the VS220 board, the WirelessHART stack normally uses UART1 to communicate with the

HART Modem (KBI2 is automatically set to 0, and J12, J16, J17, J18, J19 and J20 jumpers must be

populated (the RTS signal communicates the direction of dataflow to the HART Modem). Occasionally

the user can decide to make a serial firmware loading through USB or J14 connector, using the dedicated

Nivis PC application. For serial firmware loading through the USB interface or through J14, first populate

only the following jumpers: J10, J12 and J21 before powering on the board. During boot and firmware

loading, KBI2 is automatically set to 1, while RTS is not used. If connector J14 is used instead of USB port

for firmware loading, TTL RS232 level shifters must be employed when connecting to the PCs RS232

port.


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3. VL10 Application

The Nivis VL10 is designed specifically for WirelessHART applications and enables customers to connect

a variety of 4-20mA devices in order to read and transmit temperature or other sensor data using the

WirelessHART standard to the users Gateway. The Nivis VL10 has several interfaces that are useful tothe user.

The Nivis VL10 uses the VN220 radio, which contains an MC13224 processor running a Nivis certifiable

WirelessHART stack. It also includes a HART Maintenance Port (FSK interface) on the HART Modem

daughter card.

3.1 VL10 HART Modem Interface

The WirelessHART stack residing on the VN220 radio only supports the FSK interface (HART Modem) as a

Maintenance Port as described by the WirelessHART specification from the HART foundation.

The Maintenance Port impedance is 500 Ohm and normally it is not coupled with the VL10 4-20 mA

analog input. It is designated only for device configuration, and it does not support Burst Mode.

The HART Configuration Tool (or Handheld device) is connected to the Maintenance Port at TR1 and TR2

pins. In the default configuration, they are isolated from the boards ground, so their polarity does not

matter.

The HART Modem interface resides on connector J1 on the VL10. The VL10 comes pre-populated with a

Nivis HART Modem interface board connected at J1.

The VN220 radio communicates with the HART Modem using the UART2 interface (CTS line is not used),

and the GPIO lines described in this section. The VL10 was designed for a maximum compatibility with

the HART Modem daughter board, which contains a HART certifiable modem IC, part number

DS8500-JND+.

In order to save power, the HART Modem circuit is turned on by the VN220 only when a carrier signal is

first detected by an auxiliary low-power carrier detector circuit also located on the Modem daughter

board. The HART Modem is turned back off only after the masters request (STX) packet is received and

the slave response (ACK) packet is transmitted.

The GPIO handshaking and data transfer between the VN220 and the HART modem daughter board

connector on the VL10 is shown in Figure 2.


16/46



Figure 2. Modem Interface GPIO for VL10

The Auxiliary Carrier Detect line is an external interrupt input to the VN220. This signal becomes HIGH

when the auxiliary low-power carrier detector located on the HART Modem daughter board detects a

carrier on the line. This circuit is always powered, even when the HART Modem is switched off, and it is

only used to wake-up the VN220 from the sleep mode and/or to request the modems power control to

be switched on by the VN220.

Modem On is an output from the VN220 that turns on the power supply for the HART modem chip.

A LOW on this line will turn on the modem, and a HIGH will turn off the modem. The modem will be

turned on, to stay on reception mode, when the Auxiliary Carrier Detect line first indicates that there is a

carrier on the line.

The Modem OCD line is an input to the VN220 and is connected to the CD digital output of the HART

modem IC. This signal is used by the software to monitor the carrier presence during the reception of a

packet. Logic HIGH indicates a valid carrier detection.

The Data Out / UART2 RX line is the digital data output of the HART modems demodulator and an input

to the VN220s UART2 RX line.

The Data In / UART2 TX line is the digital data input to the HART modems modulator and an outputfrom the VN220s UART2 TX line.

The RTS line is a digital input to the modem from the VN220. When set high, the modem is put into the

demodulator mode. A logic-low puts the modem into modulator mode.

HART MODEM CONNECTORVN220

9Auxiliary Carrier Detect

30

Modem OCD35 11

15Data OutUART2 RX

3

Data In17

UART2 TX4

UART2 RTS RTS211

MODEM ON2318


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3.2 VL10 4-20 mA Input Connectivity

The VL10 acts as a WirelessHART sensor (transmitter) field device. The analog 4-20 mA input on VL10 is

identified with its Primary Variable, which can be transmitted wirelessly, but it does not support the

standard HART current loop output (the VL10 accepts analog data from a non-HART 4-20 mA transmitterdevice through its analog input, however it does not have an analog output configuration to transmit

the measured data value by analog signaling).

On the VL10, the HART Maintenance Port (FSK interface) is separate from the 4-20 mA analog input.

The field device can access the maintenance port on the VL10 on ports TR1 and TR2. Normally they are

isolated from the boards ground, so their polarity does not matter.

To connect the 4-20 mA loop to the VL10 analog input, connect the positive side to TB1, and the

negative side to TB2. Also populate J11, and depopulate J5 and J6. Refer to Figures 3, 4, and to the HART

Loop board schematic in Appendix A for more information.

Note: To introduce minimal error rate in the loop current measurement, ensure that the ground from the

power source is isolated from the VL10 ground. Using a power source with non-isolated ground cancause a significant measuring error at the differential amplifier input.

As an option, the Maintenance Port can be physically connected to the 4-20mA input circuit via

populating jumpers J5, J6 and depopulating J11. Be aware that this will introduce a 500 Ohm resistor in

series with the current loop. Figure 3 shows this connectivity on the VL10 boards side, and Figure 4

shows the circuitry involved on the Modem Daughter Board side.


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Figure 3. HART Modem Connectivity on VL10

Figure 4. HART Modem Connectivity on Modem Daughter Card

J6

90120-0122

1 2

R710

MODEM_OUT-

R610

MODEM_OUT+

J11

90120-0122

1

2

Current Sense Resistors

TB1

1727010

1 1

2 2

To A-D Converter

TB2

1727010

1 1

2 2

TR1

1249

1

1

TR2

1249

1

1

J5

90120-0122

1 2

JP2

TMM-102-01-T-S

T2

TY-307P

1

63

4

MODEM_OUT-

C24

2.2uF

R23

10

R24

499

MODEM_OUT+

From Op Amp U7of modem daughter board

To VL10

To VL10


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3.3 Additional VN220 Interfaces on the VL10

For more information on the interfaces described in this section, refer to the VL10 schematic in

Appendix A.

UART1

The VN220s UART1 lines are connected to J3 on the VL10. This connector is used for firmware loading.

WARNING: Avoid connecting J3 Pin3 to GND or to another power source (e.g. 5V).

I2C

The VN220s I2Cinterface communicates with the A/D converter on the VL10 board. The A/D converter

is used to read the current value from the 4-20mA input. Between the measurements it can be shut

down via the i2C interface to conserve power.

Figure 5. A-D Converter Interface on VL10

3V 3V

3V

C71uF

I2C _SCL sheet2

TP14

I2C _SDA sheet2

TP15

U3ADS7823E

SCL 7

SDA 6

GND 4

A1

5

VDD 8

A0

3

VREF1

AIN2

NOTE: A/D IS SHUTDOWN VIA I2C BUS COMMAND

R42K

R52K

From 2.5 voltage reference

Current monitor input


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Display Status Switch

The VN220 reads in pushbutton switch SW3 at KBI_6, pin 20. SW3 is the Display Status button. Holding

this pin low for 1 second enables the status LED for the next 10 seconds.

Figure 6. Display Status Pushbutton on VL10

Power Fail Monitor

The VN220 reads in an active low power fail monitor input at KBI_5, pin 21. Also, the RESETn line asserts

(low) whenever VCC drops below the selected reset threshold voltage, which is 2.7V.

Figure 7. Power Fail Monitoring on VL10

C18

0.1uF

R20100K

(Pin 20 of VN220)to KBI_6

SW3

EVQ-PAC07K

1

2

3V

TP11

U4

MAX6749KAT

RESET_IN1

GND4

SRT3

SWT2

VCC 8

RESETn 7

WDI 6

WDS 5

R8590K

R13499K

3V

C15

1500pF

3V

To Pin 21 of VN220

C80.1uF

KBI_5 sheet2

R104.7K


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RED Status LED

The VN220 controls a red status LED at VN220 pin 34. The functionality of this LED is described in the

following table:

Table 1. VL10 Status LED

JOIN status LED (red) State Behavior

Device in discovery mode LED blinking with a low refresh

rate. At power-up until the

network is detected.

Device joining the network LED blinking rapidly.

Advertisement has been received

and join request will be or has

been sent. Device in the process

of joining.Joined LED on continuously. The device

has joined the network

(Operational).

Figure 8. Status LED on VL10

D1 LS M67K-H2L1-1-0-2-R18-ZRED

GPIO4

sheet2

TP1

From pin 22 of VN220

R18750


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Current Monitoring Control

The VN220 can turn on/off the 2.5 Voltage reference and the analog input amplifier on the VL10 by

asserting / de-asserting pin 33. De-asserting this line will turn off the boards ability to measure the

4-20mA current loop. This switched voltage is used for power saving on the VL10.

Figure 9. Power Saving Circuit on VL10

FLASH Erase

The VN220 provides a way to erase the VN220 micro controllers internal FLASH via pins 36 and 37

(ADC_VREFH and ADC_VREFL respectively). Set ADC2-VREFH to Low and ADC2-VREFL to High and powerthe VN220 for a few seconds to erase the flash. After erasing the flash, set the ADC2-VREFH to High and

ADC2-VREFL to Low.

WARNING: This operation will erase the Nivis Bootloader and all manufacturing and non-volatile data!

The VN220 will no longer be operational, until a software re-manufacturing procedure is performed.

C210.1uF

5V

5V_SW

R241M

D

S

G

Q2SI1300BDL

1

3

2

S

D

G

Q3SI1305DL

1

2

3

GPIO5sheet2

From Pin 33 of VN220

R25100K


23/46



JTAG

The VL10 board provides a standard 20 pin JTAG interface to update the processor code residing on the

VN220. The connector designator is J2 and connects JTAG lines going to pins 42 46 of the VN220.

See the table below for the JTAG pin-out.Table 2. VL10 JTAG Pin-out

JTAG Function VN220 Pin Number J2 Pin Number

RESET 41 15

RTCK 42 11

TDO 43 13

TDI 44 5

TCK 45 9

TMS 46 7

RESET Switch

The VL10 supports a reset switch at SW1. This switch is used to reset the VN220 stack modem.


24/46



4. VS220 Application

The VS220 sensor node fulfills the Wireless HART field device logical role in the WirelessHART network.

The Nivis VS220 offers a complete integration platform for users who intend to WirelessHART enable

their instruments. This is accomplished by exposing various hardware ports of the stack modem throughwhich the user can interface an application processor.

The Nivis VS220 uses the VN220 radio, which contains an MC13224 processor running a Nivis certifiable

Wireless HART stack. It also includes a HART Maintenance Port (FSK interface) on the HART Modem

daughter card.

4.1 VS220 HART Modem Interface

The VS220 board supports the FSK interface (HART Modem) as a Maintenance Port as described by

WirelessHART specification. The Maintenance Port impedance is 500 Ohms and normally it is not

coupled with the VS220 4-20 mA analog input. It is designated only for device configuration, and it does

not support Burst Mode.

The HART Modem interface board resides on connector J6 on the VS220. The VS220 comes

pre-populated with a Nivis HART Modem interface board connected at J6.

The VN220 radio communicates with the HART Modem using the UART1 interface (CTS line is not used),

and the other GPIO lines described below. Actually UART1 is used for multiple applications on the

VS220. Appropriate jumper settings described in this document and shown on the VS220 schematic in

Appendix B of this document, need to be implemented for the UART1 pins to connect to the HART

modem. The VS220 was designed for a maximum compatibility with the HART Modem daughter board,

which contains a HART certified modem IC, part number DS8500-JND+.

In order to save power, the HART Modem circuit is turned on by the VN220 only when a carrier signal is

first detected by an auxiliary low-power carrier detector circuit also located on the Modem daughter

board. The HART Modem will be turned back off only after the masters request (STX) packet wasreceived and the slave response (ACK) packet was transmitted.

The GPIO handshaking and data transfer between the VN220 and the HART modem daughter board

connector on the VS220 is shown in Figure 10.


25/46



The Auxiliary Carrier Detect line is an external interrupt input to the VN220. This signal becomes HIGH

when the auxiliary low-power carrier detector located on the HART Modem board detects the presence

of a carrier on the line. This circuit is always powered, even when the HART Modem is switched off, and

it is only used to wake-up the VN220 from the sleep mode and/or to request the modems power

control to be switched on by the VN220.

Modem On is an output from the VN220 that turns on the power supply for the HART modem chip.

A LOW on this line will turn on the modem, and a HIGH will turn off the modem. The modem will beturned on, to stay on reception mode, when the Auxiliary Carrier Detect line first indicates that there is a

carrier on the line.

The Modem OCD line is an input to the VN220 and is connected to the CD digital output of the HART

modem chip. This signal is the one used by the software to monitoring the carrier presence during the

reception of a packet. A logic HIGH indicates a valid carrier detection.

The Data Out / UART1 RX line is the digital data output of the HART modems demodulator and an input

to the VN220s UART1 RX line.

The Data In / UART1 TX line is the digital data input to the HART modems modulator and an output

from the VN220s UART1 TX line.

The RTS line is a digital input to the modem from the VN220. When set high, the HART modem is put

into the demodulator mode. A logic-low puts the HART modem into modulator mode.

VN220 HART MODEM CONNECTOR

26 9

Modem OCD1132

15Data OutUART1 RX

7

17UART1 TX Data In

8

RTS215

UART1 RTS

11MODEM ON

23

Auxiliary Carrier Detect

Figure 10. Modem Interface GPIO for VS220


26/46



4.2 VS220 4-20 mA Input Connectivity

The VS220 acts as a WirelessHART sensor (transmitter) field device. The analog 4-20 mA input on the

VS220 is identified with its Primary Variable, which can be transmitted wirelessly, but it does not

support the standard HART current loop output (the VS220 accepts analog data from a non-HART 4-20mA transmitter device through its analog input, however it does not have an analog output

configuration to transmit the measured data value by analog signaling).

On the VS220 board, the HART Maintenance Port (FSK interface) is separate from the 4-20 mA analog

input. The field device can access the maintenance port on TR1 and TR2, and normally they are isolated

from the boards ground, so their polarity does not matter.

To connect the 4-20 mA loop to the VS220 analog input, connect the positive side to TB1, and the

negative side to TB2. Also populate J22, and depopulate J7 and J8. Refer to Figure 11 and to the HART

Development Board Schematic in Appendix B for more information.

As an option, the Maintenance Port can be physically connected to the 4-20mA input circuit via

populating jumpers J7, J8 and depopulating J22. Be aware that this will introduce a 500 Ohm resistor inseries with the current loop. Figure 11 shows the connectivity on the VS220 board, and Figure 4 shows

the circuitry on the Modem Daughter Board side.


27/46



Figure 11. HART Modem Connectivity on VS220

J7

90120-0122

12

J8

90120-0122

12

J22

90120-0122

1

2

Current sense resistors

MODEM_OUT+

R1310

MODEM_OUT-

R1210

TB1

1727010

1 1

2 2

TB2

1727010

1 1

2 2

TR1

1249

1

1

TR2

1249

1

1


28/46



4.3 VS220 Input Power Options

The VS220 has the ability to have input power applied to the board via three methods described in this

section.

WARNING: FAILURE TO COMPLY WITH THE STEPS IN SECTION 4.3 FOR EACH POWER METHOD MAYRESULT IN THE BOARD BEING DAMAGED. SPECIAL CARE MUST BE TAKEN TO COMPLY WITH EACH STEP

BELOW BEFORE APPLYING APPROPRIATE POWER TO THE BOARD.

1. External input power via TB3 connection. The external power supplys input range is 7 to 16

volts DC. For external input power, the following steps need to be performed or verified before

applying power:

1. SW4 needs to be at switch position 1.

2. R14 needs to be de-populated (default board configuration)

3. R15 and R16 needs to be populated (default configuration).

2. Battery power via the battery holder BT1. For maximum battery life, battery power is supplied

by four 3.6V cell Lithium AA batteries. As an alternative, four 1.5V Alkaline AA batteries can be

used for approximately 3 to 8 days of battery life. For battery power, the following steps need to

be performed or verified before applying power:

a. SW4 needs to be at switch position 2.

b. R14 needs to be de-populated (default board configuration).

c. R15 and R16 needs to be populated (default configuration).

3. USB 5V power. For external USB 5V power, the following steps need to be performed or verified

before applying power:

a. SW4 needs to be at switch position 3.

b. R14 (zero Ohm resistor) needs to be populated.

c. R15 and R16 need to be de-populated.

d. A USB cable needs to be connected at J11.

Note: It is not necessary to apply board power via USB in order to update the

firmware via USB. If USB communication is necessary, the VS220 can still

communicate over the USB cable while in input power option 1 or 2 (battery or

external supply). Option 3 is not recommended by Nivis and must only be used if the

board requires 5V power from the USB cable and cannot be powered via the external

supply or battery option.


29/46



Figure 12. Power Input Switch on VS220

4.4 UART1 Alternate Connectivity

The following instructions describe how UART1 should be configured for its three possibleconfigurations (VN220 UART1 to/from USB converter, VN220 UART1 to/from HART modem, and VN220

UART1 to/from external connector). For more information, refer to sheet 3 of the HART Development

Board Schematic in Appendix B.

VN220 UART1 to/from HART modem:

The configuration below should be used when the VN220 communicates with the HART modem. This is

the default configuration for the VS220 board used as a WirelessHART device, since it must have a HART

(FSK) Maintenance Port available.

1. Make sure jumpers J10 and J21 are disconnected.

2. Connect jumpers J12, and J16-20.

3. KBI2, pin 28 of the VN220 must be held LOW. This is automatically done by the WirelessHARTfirmware after the boot process is finished.

4. Apply the power or press the RESET button on the VS220 board.

VN220 UART1 to/from USB:

The configuration below should be used only when the user wishes to communicate to the VN220 via

USB. The typical application is when perform a firmware upgrade, using the dedicated Nivis PC serial

loader program and a USB cable.

1. Make sure jumpers J16-J20 are disconnected.

2. Connect jumpers J10, J12, and J21.

3. KBI2, pin 28 of the VN220 must be held HIGH. This is automatically done by the WirelessHARTfirmware during the boot process, when the communication with the dedicated Nivis PC serial

loader program is established.


SW4

1

4 2

3

Position 3 = USB PowerPosition 2 = Battery Power

Silkscreen: Position 1 = External Power

VIN

POW ER _I N V_BATT VDD _5V_U SB

Power Input Switch


30/46



VN220 UART1 to J14 connector:

The configuration below can be used to load firmware via UART1, as an alternative to the USB interface.

1. Disconnect all jumpers (J10, J12, J16-21) and connect a UART cable to J14. TTL RS232 level

shifters must be employed when connecting to the PCs RS232 port.


4.5 Additional Interfaces on the VS220

For more information on the interfaces described in this section, refer to the VS220 schematic in

Appendix B.

UART2

The VS220 provides a standard UART interface at the VN220s UART2 port for communication using the

Nivis standard API. The connector for UART2 is J2. See below for the UART2 connector pin-out.

Figure 13. UART2 Interface on VS220

SPI

The VS220 provides a standard SPI interface at the VN220s SPI port for communication using the Nivis

standard API. The connector for SPI is J2. See below for the SPI connector pin-out.

Figure 14. SPI Interface on VS220

TP48 TP49

RDY_RADIO

J2

5103309-1

1 23 4

657 89 10

UART2_TXUART2_CTSUART2_RTS

WKU_RADIOUART2_RX

RDY_RADIOWKU_RADIO

SPI_MOSI

TP42TP41

J3

5103309-1

1 23 4

657 89 10

SPI_MISO

TP43

SPI_SS

TP44

SPI_CLK


31/46



Temperature/Humidity Sensor Interface

The VS220 supports a 2 wire (two GPIOs) interface from the VN220 to an on-board

temperature/humidity sensor, which is located at U13. See below for a description of the interface.

Table 3. Temperature/Humidity Sensor Connections

Temperature Sensor Pin Name Function VN220 GPIO Pin

1 GND Ground --

2 DATA Serial Data, bidirectional 35

3 SCK Serial Clock, controlled by VN220 6

4 VDD Source Voltage **

** VDD is turned on/off by VN220 pin 33.

Figure 15. Temperature / Humidity Interface on VS220

TEMP_HUM_2

R910K


Pin 35 of VN220

Pin 6 of VN220

+3.0V

Q2BSS138LT1G

1

3

2

Q1BSS84LT1G 1

3 2

C3

0.1uF

U13

SHT15

44

33

22

11

5 5

6 6

7 7

8 8

R6470K

R8470K

TP13

TP14

TEMP_HUM_1

R710K


32/46



I2C

The VN220s I2C interface communicates with the A/D converter on the VS220 board. The A/D converter

is used to read the current value from the 4-20mA input. Between the measurements it can be shut

down via the i2C interface to conserve power.

Figure 16. A-D Converter Interface on VS220

Display Status Switch

The VN220 reads in pushbutton switch SW3 at KBI_6, pin 20. SW3 is the Display Status button. Holding

this pin low for 1 second enables the STATUS LED for the next 10 seconds.

Figure 17. Display Status Pushbutton on VS220

2.5V REF

+3.0V+3.0V

C91uF

+3.0V

I2C_SDA sheet1

I2C_SCL sheet1

R344.7K

R334.7K

U5

ADS7823E

SCL 7

SDA 6

GND 4

A1

5

VDD 8

A0

3

VREF1

AIN2

NOTE: A/D IS SHUTDOWN VIA I2C BUS COMMAND

From current sense amplifier

R5100K

C2

0.1uF

SW3

EVQ-PAC07K

1

2

+3.0V

To KBI6 (pin 20 of VN220)

TP12


33/46



Power Fail Monitor

The VN220 reads in an active low power fail monitor input at KBI_5, pin 21. Also the RESETn line asserts

(low) whenever VCC drops below the selected reset threshold voltage, which is 2.7V.

Figure 18. Power Fail Monitoring on VS220

Red Status LED

The VN220 controls a red status LED, D1, at VN220 pin 18. The functionality of this LED is described in

the following table:

Table 4. Status LED on VS220

JOIN status LED (red) State Behavior

Device in discovery mode LED blinking with a low refresh

rate. At power-up until the

network is detected.

Device joining the network LED blinking rapidly. Advertisement

has been received and join requestwill be or has been sent. Device in

the process of joining.

Joined LED on continuously. The device

has joined the network

(Operational).

U9

MAX6749KAT

RESET_IN1

GND4

SRT3

SWT2

VCC 8

RESETn 7

WDI 6

WDS 5

R23590K

R28499K

+3.0V +3.0V

C24

1500pF

C200.1uF

KBY _5 sheet1

R254.7K

To pin 21 of VN220


34/46



Figure 19. Status LED on VS220

Green LED

The VN220 controls a green LED, D3, at VN220 pin 34. The functionality of this LED is described in the

following table:

Table 5. Green LED on VS220

COMM LED (green) State Behavior

Communicating with the APP processor LED on continuously. Device

is communicating with the

APP processor in a stable

manner.

Establishing communication LED blinking rapidly. VS220

has detected

communication attempts on

the communication port but

is not yet consistently

communicating with the

external APP processor.

R2750

TP7

D1

LS M67K-H2L1-1-0-2-R18-Z

RED



35/46



Figure 20. Green LED on VS220

Current Monitoring Control

The VN220 can turn on/off the 2.5 voltage reference and the analog input amplifier on the VS220 by

asserting / de-asserting pin 12. De-asserting this line will turn off the boards ability to measure the

4-20mA current loop. This switched voltage is used for power saving on the VS220.

Figure 21. Power Saving Circuit on VS220

R3750

TP9

D3

LG M67K-G1J2-24-0-2-R18-Z

GREEN


C270.1uF

+5.0V

5V_SW

R321M

S

D

G

Q4SI1305DL

1

2

3

D

S

G

Q3SI1300BDL

1

3

2

R35100K

5V_SW_CTRLsheet1



36/46



Boot Switch

The VN220 supports dual boot for Wireless HART and ISA100 stacks based on the input at pin 27 of the

VN220. If switch SW5 is placed at position 1, the VN220 will see a logic HIGH, and the ISA100 stack will

be loaded. If switch SW5 is at position 2, the VN220 will see a logic LOW, and the Wireless HART stackwill be loaded. Switch position 3 is currently not being used.

FLASH Erase

The VN220 provides a way to erase the VN220s micro controllerFLASH via pins 36 and 37 (ADC_VREFH

and ADC_VREFL respectively). Set ADC2-VREFH to Low and ADC2-VREFL to High and power the VN220

for a few seconds to erase the flash. After erasing the flash, set the ADC2-VREFH to High and

ADC2-VREFL to Low.

WARNING: This operation will erase the Nivis Bootloader and all manufacturing and non-volatile data!

The VN220 will no longer be operational, until a software re-manufacturing procedure is performed.

JTAG

The VS220 board provides a standard 20 pin JTAG interface to update the processor code residing on the

VN220. The connector designator is J1 and connects JTAG lines going to pins 42 46 of the VN220.

See the table below for the JTAG pin-out.

Table 6. VS220 JTAG Pin-out

JTAG Function VN220 Pin Number J2 Pin Number

RESET 41 15

RTCK 42 11

TDO 43 13

TDI 44 5

TCK 45 9

TMS 46 7

RESET Switch

The VS220 supports a reset switch at SW1. This switch is used to reset the VN220 stack modem.


37/46



5. VN220 Power Supply Considerations

5.1 Maximum Ratings

Table 7. VN220 Maximum Ratings

Parameter Min Typ Max Units Comment

Supply Voltage -0.3 3.0 3.3 V

Voltage on any digital I/O -0.3 Vcc Vcc + 0.2 V

5.2 Normal Operating Conditions

Table 8. Electrical Characteristics

Parameter Min Typ Max Units Comments

Supply voltage 2.7 3.3 V

Voltage on analog pins 0 Vcc V

Voltage supply noise 200 mVpp 50Hz15MHz

Peak current 60 mA TX mode, maximum output

power

Storage and operating

temperature

-40 +85 C

Operating relative humidity 10 90 %RH Non condensing

Transmit current 60 mA

Receive current 21 27 mA

Hibernate current 15 A

For additional information please consult the VersaNode 220 datasheet (document entitled

93-00017-01_Nivis_VersaNode_220_Datasheet)


38/46



6. VN220 Layout Information and Mechanical Drawings

Figure 22. Recommended layout footprint. Primary dimensions are in inches.

Dimensions in [mm] are in millimeters.


39/46



Figure 23. Outline dimension drawing. Primary dimensions are in inches.



40/46



Figure 24. Detailed outline dimension drawing. Primary dimensions are in inches.



41/46


42/46



Figure 26. VL10 HART Loop Board Reference Schematic, Sheet 2

C18

0.1uF

TP4

3V

R20

100K

UART

1_TX

J7

90120-0122

1

2

TP5

J9

90120-0126

123456

TMR0

KBI2

KBI1

TMR1

TP6

I2C_SDA

sheet1

DEBUGCONNECTOR

TP7

I2C_SCL

sheet1

ADC2_VREFL

SW2

CHS-02TA

FLASHEraseSW

TP9

ADC2_VREFH

TP10

UART1_CTS

MODEM_ON

sheet1

JTAG_RTCK

TMR0

TP16

GPIO4

sheet1

GPIO5

sheet1

TP24

3V

MODEM_UART2_RTS

sheet1

TP17

ModeSelectJumper

JTAGInterface

MODEM_OCD

sheet1

KBI_5

sheet1

Size

Scale

DWGNO

Rev

Sheet

OF

APPROVALS

DATE

CONFIDENTIAL

PROPRIETARYINFORMATIONNOTTOBE

DISCLOSEDORCOPIEDINANYFORM

WITHOUTWRITTENPERMISSIONFROM

NIVISLLC,AtlantaGA

DRAWNBY

DESIGNEDBY

ENGINEER

QUALITY

OPERATIONS

Fax:(678)0202-6820

WIRELESSHARTLOOPBOARDSCHEMATIC

NIVISLLCAtlanta,GA

Sunday,July25,2010

2

2

C

Atlanta,Georgia30339

Phone:(678)202-6800

3

41-00011-01

MODEM_DOUT_UART2_RX

sheet1

TP18

J3

22-28-4060

1

1

2

2

3

3

4

4

5

5

6

6

RESET_B

3V

MODEM_DIN_UART2_TX

sheet1

U8

NCP301LSN27T1G

INPUT 2

NC 4

NC 5

RESET

1

GND3

SW1

EVQ-PAC07K

12

TP8

SW3

EVQ-PAC07K

12 3

V

TP11

TP2

3V

VN220RadioModule

TP19

RESET

3V

TP25

C17

0.1uF

TMR1

ResetPushbutton

KBI_6

UART

1_RTST

P26

3V

TP27

TDO

TP28

KBI1

J4

9

0120-0122

1

2

UART1_RX

UART1_TX

KBI2

TP20

J8

90120-0122

1

2

KBI3

UART

1_CTS

UART1_RTS

TP29

TMS

GND

DEBUG

J2

SBH11-PBPC-D10-ST-BK

246810

12

14

16

18

20

1357911

13

15

17

19

R19

100K

J10

90120-0122

1

2GND

DEBUG

TCK

NOTE:

Place

J10

and

J8

on

opposi

te

sides

of

the

board.

U11

MC1322xRM

UART2-RTS

1

UART2-CTS

2

UART2-RXD

3

UART2-TXD

4

UART1-RTS

5

UART1-CTS

6

UART1-RXD

7

UART1-TXD

8

I2C-SDA

9

I2C-SCL

10

TMR1

11

TMR0

12

SPI-SCK

13

SPI-MOSI

14

SPI-MISO

15

SPI-SS

16

GND

17

KBI0

18

RTC-FOUT

19

KBI6

20

KBI5

21

GND

22

GND

23

GND

24

GND

25

RTC-INT-B

26

KBI1

27

KBI2

28

KBI3

29

KBI4

30

GND

31

ADC3

32

ADC2

33

ADC1

34

ADC0

35

ADC2-VREFH

36

ADC2-VREFL

37

GND

38

VCC

39

GND

40

RESET

41

JTAG-RTCK

42

JTAG-TDO

43

JTAG-TDI

44

JTAG-TCK

45

JTAG-TMS

46

GND

47

GND

48

GND

49

RF

50

GND

51

KBI3

MODEM_KBI_CD

sheet1

R21

100K

TDI

UART

1_RX

UART

TP3


43/46



8. Appendix B. VS220 HART Development Board Reference Schematic

Figure 27. VS220 HART Development Board Reference Schematic Sheet 1

VN220

RadioModule

UART1_TX

sheet3

UART1_RTS

sheet3

I2C_SCL

sheet2

UART1_RX

sheet3

TEMP_HUM_1

I2C_SDA

sheet2

KBY_0

OCD

-

to

HART

Modem

Connector

TEMP_HUM_2

to

ADC

TP37

RD

Y_RADIO

o

HART

Modem

Con

nector

R9

10K

TP47

to

ADC

U2

NCP301LSN27T1G

INPUT 2

NC

4 NC 5

RESET

1

GND3

TP38

TP48

ADC2_VREFH

ADC2_VREFL

TP39

TP49

RD

Y_RADIO

TP50

USB_CTRL

sheet3

to

temp/humidity

sensor

circuit

SW2

CHS-02TA

+3.0V

R2

750

TP40

SPI_CLK

SPI_SS

SPI_MISO

SPI_MOSI

+3.0V

Tempe

rature/HumiditySensor

Q2

BSS138LT1G

1

32

Q1

BSS84LT1G

1

3

2

WKU_RADIO

SPI_MOSI

TP6

to

USB

level

translator

TP42

R5

100K

TP7

C1

0.1uF

R

3

750

C2

0.1uF

KBY_1

sheet3

MODEM_OCD

sheet2

C3

0.1uF

TP8

R1

100K

SW3

EVQ-PAC07K

12

+3.0V

TP9

TP10

U13

SHT15

4

4

3

3

2

2

1

1

5

5

6

6

7

7

8

8

from

boot

switch

TP41

HART_MODEM_ON

sheet2

R6

470K

+3.0V

R8

470K

SW1

EVQ-PAC07K

12

+3.0V

UART2_RTS

D1

LSM67K-H2L1-1-0-2-R18-Z

D3

LGM67K-G1J2-24-0-2-R18-Z

RED

GREEN

TP29

UART2_CTS

TP51

TEMP_HUM_2

TP11

TP12

TP13

J2

5103309-1

1

2

3

46

57

8

9

10

UART2_TX

UART2_CTS

UART2_RTS

WKU_RADIO

UART2_RX

TP30

UART2_RX

RDY_RADIO

sheet3

TP14

to

temp/humidity

sensor

TP31

UART2_TX

J3

5103309-1

1

2

3

46

57

8

9

10

SPI_MISO

ADC1

KBY_6

TP43

SPI_SS

TP32

+3.0V

TCK

TDO

TDI

5V_SW_CTRL

sheet2

TMS

RTCK

RESET

TEMP_HUM_CTRL

TP33

J1

SBH11-PBPC-D10-ST-BK

246810

12

14

16

18

20

1357911

13

15

17

19

+3.0V

MODEM_CD_WKUP

sheet2

Size

Scale

DWG

NO

Rev

Sheet

OF

APPROVALS

DATE

CONFIDEN

TIAL

PROPRIETARYINFORMATION

NOTTOBE

DISCLOSEDORCOPIEDINAN

YFORM


NIVISLLC,AtlantaGA

DRAWNBY

DESIGNEDBY

ENGINEER

QUALITY

OPERATIONS

Phone:(678)202.6800Fax:(678)202.6820

HARTDEVELOPMENTBOARD

NIVISLLCAtlanta,GA

1

3

C

100075CirclePkwy.

Atlanta,GA30339

4

41-00015-01

to

HART

Modem

Connector

TP44

SPI_CLK

U12

MC1322xRM

UART2-RTS

1

UART2-CTS

2

UART2-RXD

3

UART2-TXD

4

UART1-RTS

5

UART1-CTS

6

UART1-RXD

7

UART1-TXD

8

I2C-SDA

9

I2C-SCL

10

TMR1

11

TMR0

12

SPI-SCK

13

SPI-MOSI

14

SPI-MIS

O

15

SPI-SS

16

GND

17

KBI0

18

RTC-FO

UT

19

KBI6

20

KBI5

21

GND

22

GND

23

GND

24

GND

25

RTC-INT-B

26

KBI1

27

KBI2

28

KBI3

29

KBI4

30

GND

31

ADC3

32

ADC2

33

ADC1

34

ADC0

35

ADC2-VREFH

36

ADC2-VREFL

37

GND

38

VCC

39

GND

40

RESET

41

JTAG-RTCK

42

JTAG-TDO

43

JTAG-TDI

44

JTAG-TCK

45

JTAG-TMS

46

GND

47

GND

48

GND

49

RF

50

GND

51

TP34

KBY_5

sheet3

TP35

TP45

TEMP_HUM_1

TP46

R7

10K

TP36

J23

90120-0122

1

2

J24

90120-0122

1

2

GNDDEBUG

WKU_RADIO

sheet3

NOTE:

Place

J24

and

J25

on

opposite

sides

of

the

board.

GN

DDEBUG


44/46



Figure 28. VS220 HART Development Board Reference Schematic Sheet 2

C28

0.1uF

NOTE:

LABEL

"LOOP

CUR

RENT

+"

ON

SILKSCREEN

NOTE:

LABEL

"MAX

CURREN

TON

LOOP

=

200

mA"

NOTE:

LABEL

"LOOP

CURRENT

-"

ON

SILKSCREEN

NOTE:

LABEL

"MAX

CURRENT

ON

LOOP

=

200

mA"

D5

SMS3922-079LF

ANODE CATHODE

+3.0V

J7

90120-0122

1

2

J8

90120-0122

1

2

C27

0.1uF

+5.0V

5V_SW

R32

1M

SD

G

Q4

SI1305DL

1

23

DS

G

Q3

SI1300BDL

1

32

R35

100K

5V_SW_CTRL

sheet1

C29

0.1uF

HART_TX

sheet3

HART_RX

sheet3

J22

90120-0122

12

MODEM_OCD

sheet1

R30

24.9

5V_SW

C25

1uF

U14

AD8210YRZ

-IN

1

GND

2

VREF_2

3

NC

4

OUT

5

V+

6

VREF_1

7

+IN

8

C26

0.1uF

MODEM_CD_WKUP

sheet1

TP52

MODEM_OUT+

TP53C60.0

1uF

R13

10

+3.0V

MODEM_OUT-

R12

10

+3.0V

C4

0.1uF

NOTE:

LABEL

"MODEM

OUT

+"

ON

SILKSCREEN

NOTE:

LABEL

"MODEM

OUT

-"

ON

SILKSCREEN

+3.0V

C9

1uF

I2C_SCL

sheet1

C5

0.1uF

I2C_SDA

sheet1

R33

4.7K

J6

LSS-120-01-L-DV-A-TR-S

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

40

40

38

38

36

36

34

34

32

32

30

30

28

28

26

26

24

24

22

22

20

20

18

18

16

16

14

14

12

12

10

10

8

8

6

6

4

4

2

2

+5.0V

HART

ModemBoardConnector

R34

4.7K

U5

ADS7823E

SCL

7

SDA

6

GND

4

A1 5

VDD

8

A0 3

VREF

1

AIN

2

NOTE:

A/D

IS

SHUTDOWN

VIA

I

2C

BUS

COMMAND

NOTE:

THIS

CONNECTOR

USED

IN

SOCKET

CONFIGURATION

TB1

1727010

1

1

2

2

TB2

1727010

1

1

2

2

5V_SW

HART_RTS

sheet3

U3

ADR121AUJZ

NC1

1

GND

2

VIN

3

VOUT

4

NC2

5

NC3

6

TR1

1249

11

TR2

1249

11

2.5V

HART_MODEM_ON

sheet1

R37

100

Size

Scale

DWGNO

Rev

Sheet

OF

APPROVALS

DATE

CONFIDENTIAL




NIVISLLC,AtlantaGA

DRAWNBY

DESIGNED

BY

ENGINEER

QUALITY

OPERATIO

NS

Phone:(678

)202.6800Fax:(678)202.6820

HARTDEVEL

OPMENTBOARD

NIV

ISLLCAtlanta,GA

2

3

C

100075CirclePkwy.

Atlanta,GA30339

4

4

1-00015-01


45/46


46/46

9. Appendix C. Nivis HART Modem Daughter Board Reference Schematic

D2

1N4148W-7-F

1

2

JP1

TMM-102-01-T-S

C1

0.1uF

J1

LSS-120-01-L-DV-A-TR-P

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

40

40

38

38

36

36

34

34

32

32

30

30

28

28

26

26

24

24

22

22

20

20

18

18

16

16

14

14

12

12

10

10

8

8

6

6

4

4

2

2

41-00008-01

R17

20K

KBI_CD

C7

1000pF

C15

0.1uF

R5

976K

3V

C21

2.2uF

R1

56K

SD

G

Q1

SI1305DL

1

23

R15

1M

C14

0.1uF

U3M

AX4037EUT

-

4

REF

5

GND

2

VCC

6

OUT

1

+

3

R7

1K

C3

0.1uF

R3

10K

VIN

3V

C13

1uF

C20

0.1uF

CarrierDetectCircuit

U1A

MAX9912EKA

-

2

+

3

GND

4

OUT

1

C18

820pF

U5

MCP1702T3002E/CB

Vin

3

Vout

2

GND

1

U2A

MAX99

12EKA

-

2

+

3

GND

4

OUT

1

T1

TY-307P

1

6

3

4

3V

U4

LPV7215MG

+

3

-

4

GND

2

VCC

5

OUT

1

U2B

MAX9912EKA

-

6

+

5

VCC

8

OUT

7

R20

100K

C12

1uF

R8

1M,DNPR

9

200K

U7

LT1784CS6

-

4

+

3

SHDN

5

GND

2

V+

6

OUT

1

R16

200K

C22

2.2uF

HARTM_ON_GPIO1

R2

100K

R21

10

CENTER

PAD

U6

DS8500-JND+

XTAL1

7

XTAL2

8

XCEN

10

OCD

5

D_OUT

19

RTS

6

D_IN

20

RSTn 4

DVDD1 1

DVDD2 2

DGND1 3

DGND2 9

DGND3 16

DGND4 17

DGND5 18

AGND 15

AVDD 11

REF

13

FSK_IN

14

FSK_OUT

12

21CPAD

Y1

ECS-36-18-18-TR

1 2

OCD

C16

0.1uF

R22

499

C5

1000pF

C8

0.01uF

DOUT

R19

100K

R14

0ohm

R18

200K

R10

2.26M

C9

0.01uF

C6

1000pF

RTS

R12

0ohm,DNP

C17

3300pF

DIN

R11

1K

R13

0ohm

MODEM_OUT+

C23

10pF

Size

Scale

DWGNO

Rev

Sheet

OF

APPROVALS

DATE

CONFIDENTIAL




NIVISLLC,AtlantaGA

DRAWNBY

DESIGNEDBY

ENGINEER

QUALITY

OPERATIONS

Fax:(678)0202-6820

WirelessHARTModemBoardSchematic

N

IVISLLCAtlanta,GA

Tuesday,June29,2010

1

C

Atlanta,Georgia3033

Phone:(678)202-680

2

3V

C2

470pF

MODEM_OUT-

J2

TMM-103-01-G-D

135

246

3V

3V

U1B

MAX9912EKA

-

6

+

5

VCC

8

OUT

7

3/24/10

SandraSenn

C10

0.1uF

C11

0.1uF

C19

0.1uF

R6

143K

NOTE

:

THI

S

CONNE

CT

OR

USED

IN

PL

UG

CONFI

GURATI

ON

R4

100K

D1

1N4148W-7-F

12

C4

0.1uF

TX/RXInterfaceCircuit

Documents

Centero VN220 HW Integration Application Note