CDA4253FPGASystemDesign

HaoZhengDeptofCompSci&Eng

UofSouthFlorida

Introduc;on

•  Tradi<onalapproachestocomputa<on:HW&SW•  HW(ASICs–Applica<onSpecificICs)

– Fixedonapar<cularapplica<on– Efficient:performance,siliconarea,power– Highercost/perapplica<on

•  SW(microprocessors)– Programmability:usedinmanyapplica<ons– Lessefficient:performance,siliconarea,power– Lowercost/perapplica<on

Introduc;on

•  FieldProgrammableGateArrays(FPGAs)– Spa;alcompu;ng:similartoHW– Reprogrammable:similartoSW– FasterthanSWandmoreflexiblethanHW– Morecost-effec<veforlowvolumeapplica<ons– HardertoprogramthanSW– LessefficientthanHW:performance,siliconarea,power

•  ButASICHWisgoingaway–designcosttoohigh– FPGAdesignispromising!

CourseDescrip;ons•  OverviewofFPGAarchitectures

– Basicbuildingblocks– Fieldprogrammability

•  DigitaldesignwithVHDL– LearntowriteVHDLforsynthesisandsimula<on– Analyzeandunderstandexis<ngexamples– Modifyorusetheexis<ngexamplesfornewdesigns

•  BasicconceptsofFPGAdesignflow•  BasicIdeasofhigh-levelsynthesis

–  MappingfromalgorithmstoVHDL.•  Otherrelevanttopics:par<alreconfigura<on

CourseOutcomes•  VHDL for design/simulation/synthesis - One of the most basic and sought-after skills

•  Understanding of high-level synthesis

•  Knowledge of state-of-the-art FPGA Design tools used in the industry

•  Knowledge & experiences of a modern FPGA platform.

•  A design portfolio that can be added to your resume.

CourseDescrip;ons

•  Norequiredtextbook.But,youneedaccesstoagoodVHDLreferencebook.

•  Wewillusethefollowingbookextensively.– FPGAPrototypingbyVHDLExamplesbyChu.– VHDLcodeinthebookisavailableathere.

•  Addi<onalreadingmaterialswillbedistributed.•  Requiredbackground:CDA3201/3201L•  Acendanceisrequired.

Part I Basic Digital Circuits -  combinational -  sequential -  state machines and ASM charts

Part II I/O Modules -  video -  serial communication -  keyboard -  mouse

Part III PicoBlaze Microcontroller -  block diagram -  instruction set -  I/O interface -  interrupts

TextbookOverview

availableonlinefromUSFlibrary

CourseDescrip;ons:Evalua;on

•  6-8assignments:60%– Eachassignmentincludesdesignproblems.–  Allassignmentsareindividualunlessspecifiedotherwise.

•  Onefinalproject:40%•  Finalgrade:

•  BeHonest!– Collaborate,butdonotcopyeachother’swork.– Anyonefoundchea<ng(allpar<es)willgetFF.

CDA 4253 Fall 2015 Zheng

Evaluation

Assignments/Exam Grades Date

Lab assignments 50% n/aMidterm 20% Oct. 1st, 2015

Final Project 30% Dec. 4th, 2015

Note: The date for the midterm exam is tentative.

Final grading scale:

< 60% 60%� 69.99% 70%� 79.99% 80%� 89.99% � 90%F D C B A

• The instructor reserves the right to give +/- letter grades for the final grades.

• The above grading scale may be subject to minor change depending on the overall classperformance statistics.

• No incomplete (I) grades will be given.

Assignments

• All assignments are individual, and the final submission must be your own work.

• Late submissions will NOT be accepted unless approvals for extensions are obtainedfrom the instructor beforehand.

• Requests for re-grading must be submitted via email or in writing within one weekafter a graded assignment is returned.

• Additional specific requirements may be imposed for individual assignments. Readcarefully each assignment description when it is distributed.

Midterm Exam The midterm will be 75 minutes during a normal class meeting time. Itwill cover all topics discussed prior to the exam date.

• During the exam, all electronics must be turned o↵. Not chatting or discussion.

• Requests for re-grading must be submitted via email or in writing within one weeksince the graded exam is returned. Asking for a re-grading after the final grade isassigned because you need an additional 0.5 points to get a B or C should be avoided.

• A written request for re-scheduling the midterm exam must be approved by the in-structor beforehand. No make-up exam will be granted unless a true emergencyis involved with either a doctor note or a police report as proof. Your car broken downon your way to school or “I thought the exam would be tomorrow”, or similar excusesare not deemed as true emergencies.

2

OfficeHour

•  Instructor– Time:10-11am,MWF,orbyappointment.– Office: ENB312

•  TA:HernanPalombo– Time:1-4pmThurssday– Office:ENB327

CourseCommunica;on

•  Canvas:– Announcements– Downloadassignmentdescrip<ons– Submityoursolu<ons– Checkyourgrades– Discussionswhereyoucancollaborate

•  www.cse.usf.edu/~zheng/teaching/cda4253– Slides– Othercourserelateddocuments

CourseTopics

•  FPGAarchitectures– Commercial(Xilinx/Altera)

•  DigitalDesignwithVHDL– Modeling/synthesis/simula<on

•  BasicconceptsofFPGACADalgorithms•  Basicideaofhigh-levelsynthesis•  Basicideaofdynamicpar<alreconfigura<onanditsapplica<ons

•  Casestudies

Basys3FPGABoardBasys3™ FPGA Board Reference Manual

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14 13

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5

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8

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11 912

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10

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16

Figure 1. Basys3 FPGA board with callouts.

Table 1. Basys3 Callouts and component descriptions.

A growing collection of board support IP, reference designs, and add-on boards are available on the Digilent website. See the Basys3 page at www.digilentinc.com for more information.

1 Power Supplies

The Basys3 board can receive power from the Digilent USB-JTAG port (J4) or from a 5V external power supply. Jumper JP3 (near the power switch) determines which source is used.

All Basys3 power supplies can be turned on and off by a single logic-level power switch (SW16). A power-good LED (LD20), driven by the “power good” output of the LTC3633 supply, indicates that the supplies are turned on and operating normally. An overview of the Basys3 power circuit is shown in Fig. 2.

Callout Component Description Callout Component Description

1 Power good LED 9 FPGA configuration reset button

2 Pmod connector(s) 10 Programming mode jumper

3 Analog signal Pmod connector (XADC) 11 USB host connector

4 Four digit 7-segment display 12 VGA connector

5 Slide switches (16) 13 Shared UART/ JTAG USB port

6 LEDs (16) 14 External power connector

7 Pushbuttons (5) 15 Power Switch

8 FPGA programming done LED 16 Power Select Jumper

Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Page 2 of 19

Basys3FPGABoard–ConnecttoPower

Basys3FPGABoard-Modes

Tes<ngProgramming/Debugging

•  Morerelatedinforma<oncanbefoundat– Digilent’swebsite– Basys3wikipage

•  ReadtheBasys3ReferenceManual(Digilent’swebsite)-  Trytogetasmuchaspossible.

•  Finishthepower-ontestatthelinkbelowASAP.– Exchangeforanewboardifthetestfails.

Basys3FPGABoard

hcps://reference.digilen<nc.com/learn/programmable-logic/tutorials/basys-3-abacus/start

VivadoDesignSuite

•  AnenvironmentwhereyoucreateVHDLdescrip<onsofdesigns.

•  Offerstoolsfor– simula<on,synthesis,FPGAconfigura<on

•  Theversionforthiscourse:VivadoHLx2016.1Webpack(free)

– Allyourworkwillbeevaluatedwiththistool