CBM DAQ and Event Selection

CBM DAQ and Event CBM DAQ and Event SelectionSelection

Walter F.J. Müller, GSI, Darmstadtfor the CBM Collaboration

International Workshop onTransition Radiation Detectors – Present and

FutureCheile Gradistei, Romania, September 24-28,

2005

25 September 2005 TRD Workshop, Cheile Gradistei, September 24-28, 2005 2

OutlineOutline

CBM (very briefly) observables setup

FEE/DAQ/Event Selection requirements challenges strategies


CBM at FAIR ... evolvingCBM at FAIR ... evolvingSIS 100 Tm

SIS 300 Tm

U: 35 AGeV

p: 90 GeV

Compressed Baryonic Matter

Experiment


CBM Physics Topics and CBM Physics Topics and ObservablesObservables In-medium modifications of hadrons

onset of chiral symmetry restoration at high ρB

measure: , , e+e- (μ+ μ-) open charm: D0, D±

Strangeness in matter enhanced strangeness production measure: K, , , ,

Indications for deconfinement at high ρB

anomalous charmonium suppression ? measure: D0, D±

J/ e+e- (μ+ μ-) Critical point

event-by-event fluctuations

measure: π, K

Good e/π separation

Low cross sections→ High interaction rates→ Selective Triggers

Hadron identification

Vertex detector


CBM SetupCBM Setup

Radiation hard Silicon pixel/strip detectors in a magnetic dipole field

Electron detectors: RICH & TRD & ECAL: pion suppression up to 105

Hadron identification: RPC, RICH

Measurement of photons, π0, η, and muons: ECAL


Add ZCAL to determine centrality

Consider HPD for early lepton tagging (optional)

Consider μID detector (optional)

Consider various Silicon tracker implementations

CBM Setup... evolvingCBM Setup... evolving

ZCALHBD μID


CBM Trigger RequirementsCBM Trigger Requirements In-medium modifications of hadrons

onset of chiral symmetry restoration at high ρB

measure: , , e+e-

open charm (D0, D±) Strangeness in matter

enhanced strangeness production measure: K, , , ,

Indications for deconfinement at high ρB

anomalous charmonium suppression ? measure: D0, D± -

J/ e+e Critical point

event-by-event fluctuations

measure: π, K

offline

assume archive rate:few GB/sec20 kevents/sec

offline

offline

trigger

trigger

trigger trigger on high pt e+ - e- pair

trigger ondisplaced vertex

drives FEE/DAQarchitecture


Open Charm DetectionOpen Charm Detection Example: D0 K-+ (3.9%; c = 124.4 m) reconstruct tracks find primary vertex find displaced tracks find secondary vertex

target

first two planesof vertex detector

few 100 μm

5 cm

standard procedure.... for CBM, this is in 1st level 'trigger'

like for LHcB or BTeV (rip)


CBM DAQ Requirements ProfileCBM DAQ Requirements Profile

D and J/Ψ signal drives the rate capability requirements D signal drives FEE and DAQ/Trigger requirements

Problem similar to B detection, like in LHCb or BTeV (rip)

Adopted approach:

displaced vertex 'trigger' in first level, like in BTeV (rip)

Additional Problem:

DC beam → interactions at random times

→ time stamps with ns precision needed

→ explicit event association needed Current design for FEE and DAQ/Trigger:

Self-triggered FEE Data-push architecture


Conventional FEE-DAQ-Trigger Conventional FEE-DAQ-Trigger LayoutLayout Detector

Cave

Shack

FEE

Buffer

L2 Trigger L1 Trigger

DAQ

L1 A

ccep

t

L0 Trigger

fbunch

Archive

Trigger

Primitives

Especially

instrumented

detectors

Dedicated

connections

Specialized

trigger

hardware

Limited

capacity

Limited

L1 trigger

latency

Modest

bandwidth

Standard

hardware


Limits of Conventional Limits of Conventional ArchitectureArchitecture

Decision time for first level trigger limited.

typ. max. latency 4 μs for LHC

Only especially instrumenteddetectors can contribute to

first level trigger

Large variety of veryspecific trigger hardware

Not suitable for complexglobal triggers like secondary

vertex search

Limits future triggerdevelopment

High development cost


L1 Trigger

Special

hardware

High

bandwidth

The way out .. use Data Push The way out .. use Data Push ArchitectureArchitectureDetector

Cave

Shack

FEE

Buffer

L2 Trigger L1 Trigger

DAQ

L1 A

ccep

t

L0 Trigger

fbunch

Archive

Trigger

Primitives

Especially

instrumented

detectors

Dedicated

connections

Specialized

trigger

hardware

Limited

capacity

Limited

L1 trigger

latency

Modest

bandwidth

Standard

hardware

fclock

L2 Trigger

Timedistribution


L1 Trigger

Special

hardware

High

bandwidth

The way out ... use Data Push The way out ... use Data Push ArchitectureArchitectureDetector

Cave

Shack

FEE

DAQ

Archive

fclock

L2 Trigger


L1 Select

Special

hardware

High

bandwidth

The way out ... use Data Push The way out ... use Data Push ArchitectureArchitecture Detector

Cave

Shack

FEE

DAQ

Archive

fclock

L2 Select

Self-triggered front-end

Autonomous hit detection

No dedicated trigger connectivity

All detectors can contribute to L1

Large buffer depth available

System is throughput-limited

and not latency-limitedModular design:

Few multi-purpose rather

many special-purpose

modulesUse term: Event Selection


Front-End for Data Push Front-End for Data Push ArchitectureArchitecture Each channel detects autonomously all hits

An absolute time stamp, precise to a fraction of the sampling period, is associated with each hit

All hits are shipped to the next layer (usually concentrators)

Association of hits with events done later using time correlation

Typical Parameters: with few 1% occupancy and 107 interaction rate:

some 100 kHz channel hit rate few MByte/sec per channel whole CBM detector: 1 Tbyte/sec

→ power efficient

front-end

→ low jitterclock/time distribution

→ high bandwidth


Typical Front-End Electronics Typical Front-End Electronics Chain Chain

PreAmpPreAmp ShaperShaper ADCADC Hit

Finder

Hit

Finderdigital

Filter

digital

FilterBackend

& Driver

Backend

& Driver

Si Strip Pad GEM's PMT APD's

Shaping

time:

5-200 ns

Sample rate:

10-100 MHz

Dyn. range:

8...>12 bit

1/t Tail

cancellation

Baseline

restorer

Hit

parameter

estimators:

Amplitude

TimeFIFO-Buffering

Line protocol

All in one mixed-signal chip


Towards a Multi-Purpose FEE Towards a Multi-Purpose FEE ChainChain

PreAmpPreAmp ADCADC Hit

Finder

Hit

Finderdigital

Filter

digital

FilterShaperShaper

Several selectable

input stages;

→ pos/neg signals

→ capacitance match

switched capacitor filter

→ programmable

shaping time

programmable

sampling rate

programmable

hit finder and

estimator


Towards an Over All Towards an Over All ArchitectureArchitecture

DigitalPipeline

Ain

EventBuffers

send

DAC

AnalogFilter

sampleDigitalFilters

WE RE

westop

N Pre-AmplifierBlocks

TIMER

CLOCK

different combinations• sampling rate• resoluion• power

DATA-out

ANALOGFIFO

to/from next neighbor hit detection

ADC

start

Hit TDC

Hit Detector• Leading Edge• peak• …

1..N

FastReadout

.

.

.

to/from next neighbor hit detection

ProgrammableFinite StateMachine

leveraging TRAP knowledgeand expertise


A CBM A CBM M-M-MPW RunMPW Run CBM organized a Multi-Multi Project Wafer run in UMC 0.18 μm CMOS

6 different parts combined on a 5 x 5 mm2 wafer submitted June to Europractice (IMEC) dies (already cut) just delivered, now come the moments of truth

Atkin

Fischer

Brüning

Deppe

Muthers

Tontisirin

Content addressable

memory

12bit 50MSPS ADC

Test structuresPreAmp for

Si Strip

DLL based TDC

Clock-Data recovery

Coordination:Marcus Dorn @ KIP


FEE SummaryFEE Summary Concrete R&D on FEE ASIC buildings

blocks MPWs done in 2005 covering essential

blocks analyze results, plan now next steps

Other ongoing developments: Fast PreAmp-Shapers by H.K. Soltveit

in 0.35 μm AMS CMOS as spin-off of DETNI in 0.13 μm IBM CMOS

next generation TAC by H. Flemming

FOPI and HADES work on RPC electronic both learn to build mid-sized systems self-triggered multi-hit TDC based on

CERN HPTDC as HADES spin-off planned


CBM DAQ and Online Event CBM DAQ and Online Event SelectionSelection

More than 50% of total data volume relevant for first level event selection

Aim for simplicity

Simple two layer approach:1. event building2. event processing

neededfor D needed

for J/μ usefullfor J/μ

STS, TRD, and ECAL data usedin first level event selection


Logical Data FlowLogical Data Flow

Concentrators:multiplex channelsto high-speed links

Time distribution

Buffers

Build Network

Processing resources forfirst level event selectionstructured in small farms

Connection to'high level'

selection processing


Bandwidth RequirementsBandwidth Requirements

Data flow:

~ 1 TB/sec

1st level selection:

10~14 operation/sec

Data flow:

few 10 GB/sec

archive target: 1 GB/sec

Moore helps

Gilder helps


CBM DAQ / L1 Event Selection CBM DAQ / L1 Event Selection Requirements Profile RevisitedRequirements Profile Revisited

So far assumed: D and J/Ψ measured simultaneously @ 107 int/sec requirements driven by D (displaced vertex @ L1)

Current scenarios: open charm runs with ~106 int/sec look into D0, D±, Ds, and Λc

look into J/Ψ → e+e-

look into J/Ψ → μ+μ-

look into p-A and p-p

less computational B/W

open charm L1 select

lower σ → 107 int/sec

all new game, still open

even lower σ → 108+ int/sec

Λc has cτ = 60μm only


CBM DAQ / L1 Event Selection CBM DAQ / L1 Event Selection Requirements Profile RevisitedRequirements Profile Revisited

System Observable Interaction Rate

Au+Au open charm 106

C+C open charm 107

p+p,p+A open charm few 107

Au+Au J/Ψ 107

C+C J/Ψ 108

p+p,p+A J/Ψ few 108

p+A Y few 108

MAPS/DEPFET pile-up again

primary vertex determination ?

events no longer well separated in time....


Feasibility & Options: BNetFeasibility & Options: BNet

Data flow in Event Builder

~ 1 TB/sec


Example: InfiniBand SwitchesExample: InfiniBand Switches

TODAY: Voltaire ISR 9288 InfiniBand switch 288 4x ports; non-blocking cost today ~120 kEUR (or ~400 EUR/port) 288 GByte/sec switching bandwidth

likely in a few years: 288 4x port QDR likely same or lower cost 1152 GByte/sec switching speeds adequate for CBM...

Conclusion: BNet switch is not a major issue There will be a COTS solution


Feasibility & Options: PNetFeasibility & Options: PNet

Initial proposal:Network of FPGA and

CPU resources


Slide from CHEP'04 Dave McQueeney

IBM CTO US Federal

Shown in CBM Collaboration Meeting October 2004


The Cell Processor one 'normal' PowerPC CPU (PPE) 8 Synergistic Processing Element

(SPE) each with 256 kB memory; 128 x 128 bit

register 4 SP floating point units (SIMD)

designed for best GFlop/W runs at ~ 3 GHz → 200 GFlop peak Software support state:

Linux integration planned for 2.6.13 SPE interface via spufs gcc/gdb support for C/C++ SIMD instructions via instrinsics...

221 mm2 die sizein 90 nm

Developed bySony, Toshiba and IBMMarket: VIDEOGAMESBudget: 500 M$


The Cell Processor cont.The Cell Processor cont. Processors like the Cell offer

massive single precision floating point capabilities large memory bandwidth very good power efficiency (GFlop / W)

This is a very promising platform for L1 tracking great for algorithms with a lot of arithmetic probably much easier to handle than FPGAs

Next steps analyze CA/KF tracker algorithm determine the SIMD potential re-implement it for speed

Note: might even improve time on a normal PC when SSE is used.... and of course, get a Cell system ...

Note: 1000 Cell processors have 200 SP TFlop peak ....

Even Intel has realizednow that this is thetheessential figure of

merit


CBM FEE/DAQ DemonstratorCBM FEE/DAQ Demonstrator Mission: Provide a platform to

demonstrate essential architecture elements of the CBM FEE-DAQ concept FEE: self-triggered, data push, conditional RoI based readout CNet: combined data, time, control, and RoI traffic TNet: low jitter clock and synchronization over serial links BNet: high bandwidth, RDMA based architecture E/DCS: integrated approach for DCS/ECS

provide test bed for all future FEE/DAQ prototyping in hardware firmware controlware software

perform beam tests with detector prototypes form basis for medium-scale applications in intermediate-term

experiments

Be operational by end 2006 avoid cathedrals, go for the bazaar, try and learn build a first generation (G1) demonstrator quickly


Mini Setup: Ethernet basedMini Setup: Ethernet based

DCB

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FEE

FEE

DCB-TC

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FEE

FEE

DCB

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FEE

FEE

FEE

FEE

GE Switch

Next to minimal test bench setupfew DCB

clock/trigger from DCB-TCmodest data date via GE

PC

GE

PC

GE


The EndThe End

Thanks for Thanks for your attentionyour attention

We acknowledge the support of the European Community-Research Infrastructure Activity under the

FP6 "Structuring the European Research Area" programme (HadronPhysics, contract number RII3-CT-

2004-506078).

Documents

CBM DAQ and Event Selection