CASIS: a Very High Dynamic Range Front-End Electronics ...bonvicin/CASIS2/Bonvicini_IEEE_NSS_2007.pdf · 10/31/2007 Valter Bonvicini - IEEE NSS 2007 1 CASIS: a Very High Dynamic Range

10/31/2007 Valter Bonvicini - IEEE NSS 2007 1

CASIS: a Very High Dynamic Range Front-End Electronics with Integrated Cyclic ADC for

Calorimetry Applications

V. Bonvicini, G. Orzan, G. Zampa, N. Zampa(INFN - Trieste)

Presented by V. Bonvicini

1. The CASIS chip: motivations, objectives and design;2. First (preliminary) experimental results;

3. Outlook.

IEEE NSS 2007 - October 27 - November 3, 2007 - Honolulu (Hawaii)

CASIS: a Very High Dynamic Range Front-End Electronics with Integrated Cyclic ADC for

Calorimetry Applications

V. Bonvicini, G. Orzan, G. Zampa, N. Zampa(INFN - Trieste)

Presented by V. Bonvicini

1. The CASIS chip: motivations, objectives and design;2. First (preliminary) experimental results;

3. Outlook.

IEEE NSS 2007 - October 27 - November 3, 2007 - Honolulu (Hawaii)


The CASIS project

CASIS (Silicon Calorimetry for Space) :INFN R&D project aimed at improving the present performance of Si – W calorimeters (both detectors and front-end electronics) in view of future astroparticle physics experiments, where very high energy (up to 1015 eV) particles are to be studied.

Design approach:

• Front-end section: a double gain (double range) CSA with automatic gain control followed by a Correlated Double Sampling (CDS) filter.

• ADC: Cyclic ADC with 12 bits of resolution, clock up to a few MHz.• Technology: 0.35 um C35B4 CMOS from AMS (4M/2P, 3.3V supply).

Development of integrated front-end electronics with very largedynamic range for silicon detectors in calorimeter applications

Phase1- 2006 (CASIS1.0): front-end circuit with• Range of 50 pC (~ 104 MIP for 380 µm thick Si detectors);• ENC < 6000 e- rms @ Cdet = 300 pF;• Power consumption < 3 mW/channel.Perform a feasibility test of integration of one ADC/channel

Phase2- 2007 (CASIS1.1): improved prototype, including all lessonslearned from CASIS1.0 (especially concerning the ADC)Phase3- 2008 (CASIS1.2): “Final” 16-channel complete circuit with 1 ADC/channel.


The front-end part (CSA + CDS) in CASIS1.0 fulfilled all design specs (dynamic range,noise, linearity and power consumption), therefore:

From CASIS1.0 to CASIS1.1

Only minor improvements and modifications were implemented in CASIS1.1 (mainly inthe CSA feedback and feedback control networks).

The ADC part in CASIS1.0 have shown some (expected) problems, mainly due tothe effect of random device mismatch on the Diff. Op. Amps:

- Percentage of working channels ~ 50%;- Anomalous power consumption in the non-working channels (~ 10 times)

Therefore:

We revised the design of the Diff. Op. Amps of the ADC, implementing 9 ADC channelsdesigned around 2 alternative solutions.


CASIS1.1: CSA and Correlated Double Sampling block scheme


CASIS1.1: Cyclic ADC block scheme

+

-

ADCON

CYCLE

0.5 pF

0.5 pF

0.25 pF

CYCLE

CLK3N

ADCON

0.25 pF

CYCLE ADCON

Vcm

Vcm

Vcm

CLK3N

CLK2N

SAMPLE

Vinput

CLK4

Vom

CLK2N

CLK4Vop

+

-

CLK2

CLK2

0.5 pF

0.5 pF

CLK1 ADCON

CLK1 ADCON

CLK2

CLK2

0.5 pF

0.5 pF

CLK3

SUBPOS

SUBNEG

Vref+

Vref-

CLK3

SUBNEG

SUBPOS

Vref+

Vref-

Vcm

Vcm

+

-

Vip

Vim

Vcm

CLK3

CLK3

Q

Q

CLR

CLK2

CLK2

30 fF

30 fF

CLK3

QSUBPOS

SUBNEG

SUBPOSCLK3

Q

CLK3

QSUBNEG

CLK3

Q


Input diff. amp. BiasInput diff. amp.

Output buffer CMFB amplifier

Diff. Op. Amp. Solution 1 (baseline)


Diff. Op. Amp. Solution 2 (back-up)


Micrograph of a die (chip CASIS1.1)

3.1 mm

3.1 mm

CDS ch. 1

Buffer ch. 1

CSA ch. 1CSA bias

3 “Type O”ADC

ADC control

3 “Type N”ADC

3 “Type F”ADC

The CASIS chip was designed during 2006/2007 and produced within an Europractice MPW run started in April 2007.


Linearity_LowGain

y = 0.1456x + 921.55

0

500

1000

1500

2000

2500

3000

0 2000 4000 6000 8000 10000 12000

Input charge, MIP

Out

put v

olta

ge, m

V

Linearity_HighGain

y = 2.9393x + 933.19

0

500

1000

1500

2000

2500

3000

0 100 200 300 400 500 600

Input charge, MIP

Out

put v

olta

ge, m

V

Non-linearity_HighGain

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0 100 200 300 400 500 600

Input charge, MIP

%Er

ror

Non-linearity_LowGain

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0 10 20 30 40 50 60

Input charge, fC

%Er

ror

Dynamic ranges : 560 MIP for high gain, and 11000 MIP for low gain (or ~ 52 pC)Maximum deviation from linear fit : < 0.3% for high gain, and 0.6% for low gain

Power consumption: 2.8 mW/channel

CASIS1.1: Front-end results


• ENC@0 pF = 2280 e- rms (~12.9 SNR for 1 MIP)



CASIS1.1: Front-end results

Measured noisey = 7.5588x + 2278.7

0

1000

2000

3000

4000

5000

6000

0 50 100 150 200 250 300 350

Cd, pF

ENC,

e- r

ms

ENCLinear (ENC)


CASIS1.1: ADC resultsLinearity (FE + int. ADCs) Chip 1

0255075

100125150175200

0 5 10 15 20 25 30

Input charge [MIP]

Sign

al -

ped.

[AD

C c

h.] Ch2-ADC1

Ch2-ADC2Ch2-ADC3Ch2-ADC4Ch2-ADC5Ch2-ADC6Ch2-ADC7Ch2-ADC8Ch2-ADC9

Preliminary! Linearity (FE + int. ADCs), Chip1

0500

1000150020002500300035004000

0 1000 2000 3000 4000 5000 6000 7000

Input charge, MIP

ADC

chan

nels

ADC2ADC3ADC4ADC5ADC6ADC7ADC8ADC9ADC1

Chip1_ADCtest

60708090

100110120130140150160

798 800 802 804 806 808

Input voltage, mV

ADC

chan

nels

ADCOndADCO1ADCO2ADCF1ADCF2ADCFndADCN1ADCN2ADCNnd

• All ADC channels work! (19 chips“fast tested”, i.e. 171 ADC channels);

• First, preliminary indications areconsistent with 12-bit resolution;

• Complete and detailed measurementsare under way to exactly determinethe ADC performance.


Summary and Outlook

• The 2nd prototype of a VLSI front-end chip (CASIS1.1) intended for the read-out of silicon calorimeters has been designed, produced and tested in the framework of the INFN R&D experiment CASIS2.

• The chip features 2 channels including a double-range CSA (with gains 2.94 mV/MIP and 146 µV/MIP) with real-time control feedback network, a CDS filter and an output buffer, and 9 channels with fully differential cyclic ADCs (2 different designs for the Diff. Op. Amps).

• The front-end part (CSA + CDS) fulfils all design specs. In particular, a dynamic range of 52.2 pC (in Low-Gain mode), an ENC = 2280 e- + 7.6 e-/pF, a very good linearity and a power consumption of 2.8 mW/ch have been achieved.

• Tests on the ADC part are under way, from the results available at this time we can conclude that:

a) 100% of the channels convert correctly (171 ADC channels fast-tested at 250 kHz and 1 MHz) and display the expected power consumption we solved the random device mismatch problems;

b) Preliminary indications show that the ADC resolution is close to the design one, but we need to complete the measurements to fully determine all ADC performance (missing codes, linearity…).

• On the basis of the results on this prototype, we are confident to be able to design the “final” chip version (CASIS1.2) with 16 complete channels in 2008.

This work has been completely supported by the Istituto Nazionale di Fisica Nucleare (INFN)


Back-up slides


Power consumption [mW]

Phase margin [deg]

Cou

nts

Cou

nts

DC gain [dB]

Unity-gain frequency [MHz]

Cou

nts

Cou

nts

Monte Carlo simulation of the modified Diff. Op. Amp. (500 runs)

The corrections made on the input differential amplifier solve the mismatch problem


400 MIP

300 MIP

200 MIP

100 MIP

From the bottom: 7000 MIP8000 MIP9000 MIP

10000 MIP

CASIS: results of the front-end section

Oscilloscope pictures of the output of the CDS. Input charge injected by a pulse generator through an external capacitor.


Documents

CASIS: a Very High Dynamic Range Front-End Electronics ...bonvicin/CASIS2/Bonvicini_IEEE_NSS_2007.pdf · 10/31/2007 Valter Bonvicini - IEEE NSS 2007 1 CASIS: a Very High Dynamic Range