Cascaded Two-Level Inverter-Based Multilevel

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IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 29, NO. 3, JUNE 2014 993

Cascaded Two-Level Inverter-Based Multilevel

STATCOM for High-Power ApplicationsN. N. V. Surendra Babu, Member, IEEE, and B. G. Fernandes, Member, IEEE

AbstractIn this paper, a simple static var compensating

scheme using a cascaded two-level inverter-based multilevel in-verter is proposed. The topology consists of two standard two-levelinverters connected in cascade through open-end windings of athree-phase transformer. The dc-link voltages of the inverters areregulated at different levels to obtain four-level operation. The

simulation study is carried out in MATLAB/SIMULINK to pre-

dict the performance of the proposed scheme under balanced andunbalanced supply-voltage conditions. A laboratory prototype isdeveloped to validate the simulation results. The control schemeis implemented using the TMS320F28335 digital signal processor.

Further, stability behavior of the topology is investigated. Thedynamic model is developed and transfer functions are derived.

The system behavior is analyzed for various operating conditions.

Index TermsDC-link voltage balance, multilevel inverter,

power quality (PQ), static compensator (STATCOM).

I. INTRODUCTION

T HE application of flexible ac transmission systems(FACTS) controllers, such as static compensator(STATCOM) and static synchronous series compensator

(SSSC), is increasing in power systems. This is due to their

ability to stabilize the transmission systems and to improve

power quality (PQ) in distribution systems. STATCOM is pop-ularly accepted as a reliable reactive power controller replacing

conventional var compensators, such as the thyristor-switched

capacitor (TSC) and thyristor-controlled reactor (TCR). This

device provides reactive power compensation, active power

oscillation damping, flicker attenuation, voltage regulation, etc.

[1].

Generally, in high-power applications, var compensation is

achieved using multilevel inverters [2]. These inverters consist

of a large number of dc sources which are usually realized by

capacitors. Hence, the converters draw a small amount of active

power to maintain dc voltage of capacitors and to compensate

the losses in the converter. However, due to mismatch in con-duction and switching losses of the switching devices, the ca-

pacitors voltages are unbalanced. Balancing these voltages is a

major research challenge in multilevel inverters. Various con-

trol schemes using different topologies are reported in [3][7].

Among the three conventional multilevel inverter topologies,

Manuscriptreceived February 07,2012; revisedJune 27, 2012, June19, 2013,and October 02, 2013; accepted February 04, 2014. Date of publication March

04, 2014; dateof current versionMay 20, 2014. Paper no. TPWRD-00127-2012.The authors are with the Electrical Engineering Department, Indian Institute

of Technology Bombay, Mumbai, Maharashtra 400076, India (e-mail: suren-

[email protected]; [email protected]).

Digital Object Identifier 10.1109/TPWRD.2014.2305692

cascade H-bridge is the most popular for static var compensa-

tion [5], [6]. However, the aforementioned topology requires a

large number of dc capacitors. The control of individual dc-link

voltage of the capacitors is difficult.

Static var compensation by cascading conventional multi-

level/two level inverters is an attractive solution for high-power

applications. The topology consists of standard multilevel/two-

level inverters connected in cascade through open-end wind-

ings of a three-phase transformer. Such topologies are popular

in high-power drives [8]. One of the advantages of this topology

is that by maintaining asymmetric voltages at the dc links of the

inverters, the number of levels in the output voltage waveformcan be increased. This improves PQ [8]. Therefore, overall con-

trol is simple compared to conventional multilevel inverters.

Various var compensation schemes based on this topology are

reported in [10][12]. In [10], a three-level inverter and two-

level inverter are connected on either side of the transformer

low-voltage winding. The dc-link voltages are maintained by

separate converters. In [11], three-level operation is obtained by

using standard two-level inverters. The dc-link voltage balance

between the inverters is affected by the reactive power supplied

to the grid.

In this paper, a static var compensation scheme is proposed

for a cascaded two-level inverter-based multilevel inverter. Thetopology uses standard two-level inverters to achieve multilevel

operation. The dc-link voltages of the inverters are regulated at

asymmetrical levels to obtain four-level operation. To verify the

efficacy of theproposed control strategy, the simulation study is

carried out for balanced and unbalanced supply-voltage condi-

tions. A laboratory prototype is also developed to validate the

simulation results.

From the detailed simulation and experimentation by the au-

thors, it isfound that the dc-link voltages of two inverters col-

lapse for certain operating conditions when there is a sudden

change inreference current. In order to investigate the behavior

of the converter, the complete dynamic model of the system isdeveloped from the equivalent circuit. The model is linearized

and transfer functions are derived. Using the transfer functions,

systembehavior is analyzed for different operating conditions.

This paper is organized as follows: The proposed control

schemeis presented in Section II. Stability analysis of the con-

verter is discussed in Section III. Simulation and experimental

results are presented in Sections IV and V, respectively.

II. CASCADED TWO-LEVEL INVERTER-BASED

MULTILEVELSTATCOM

Fig. 1 shows the power system model considered in this paper

[13]. Fig. 2 shows the circuit topology of the cascaded two-level

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994 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 29, NO. 3, JUNE 2014

inverter-based multilevel STATCOM using standard two-level

inverters. The inverters are connected on the low-voltage (LV)

side of the transformer and the high-voltage (HV) side is con-

nected to thegrid. The dc-linkvoltages of the inverters are main-

tained constant and modulation indices are controlled to achieve

the required objective. The proposed control scheme is derived

from the ac side of the equivalent circuit which is shown in

Fig. 3. In the figure, and are the source voltages re-

ferred to LV side of the transformer, and are the re-

sistances which represent the losses in the transformer and two

inverters, and are leakage inductances of transformer

windings, and and are the output volt-

ages of inverters 1 and 2, respectively. are the leakage

resistances of dc-link capacitors and , respectively. As-

suming and applying

KVL on the ac side, the dynamic model can be derived using

[14] as

(1)

Equation (1) represents the mathematical model of the cas-

caded two-level inverter-based multilevel STATCOM in the

stationary reference frame. This model is transformed to the

synchronously rotating reference frame [14]. The - axes

reference voltage components of the converter and are

controlled as

(2)

(3)

where is the -axis voltage component of the ac source and

are - axes current components of the cascaded inverter,

respectively. The synchronously rotating frame is aligned with

source voltage vector so that the -component of the source

voltage is made zero. The control parameters and are

controlled as follows:

(4)

(5)

The -axis reference current is obtained as

(6)

where and are the reference and actual

dc-link voltages of inverters 1 and 2, respectively. The -axis

reference current is obtained either from an outer voltage

regulation loop when the converter is used in transmission-line

voltage support [5] or from the load in case of load compensa-

tion [16].

Fig. 1. Power system and the STATCOM model.

Fig. 2. Cascaded two-level inverter-based multilevel STATCOM.

Fig. 3. Equivalent circuit of the cascaded two-level inverter-based multilevel

STATCOM.

A. Control Strategy

The control block diagram is shown in Fig. 4. The unitsignals and are generated from the phase-locked

loop (PLL) using three-phase supply voltages [14].

The converter currents are transformed to the syn-

chronous rotating reference frame using the unit signals. The

switching frequency ripple in the converter current components

is eliminated using a low-pass filter (LPF). From

and loops, the controller generates axes reference volt-

ages, and for the cascaded inverter. With these reference

voltages, the inverter supplies the desired reactive current

and draws required active current to regulate total

dc-link voltage . However, this will not ensure that

individual dc-link voltages are controlled at their respective

reference values. Hence, additional control is required to regu-

late individual dc-link voltages of the inverters.


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SURENDRA BABU AND FERNANDES: CASCADED TWO-LEVEL INVERTER-BASED MULTILEVEL STATCOM 995

Fig. 4. Control block diagram.

B. DC-Link Balance Controller

The resulting voltage of the cascaded converter can be given

as , where and .

The active power transfer between the source and inverter de-

pends on and is usually small in the inverters supplying var to

the grid [1]. Hence, can be assumed to be proportional to .

Therefore, the -axis reference voltage component of inverter-2

is derived to control the dc-link voltage of inverter-2 as

(7)

The -axis reference voltage component of inverter-1 is ob-

tained as

(8)

The dc-link voltage of inverter-2 is controlled at 0.366

times the dc-link voltage of inverter-1 [9]. It results in

four-level operation in the output voltage and improves the har-

monic spectrum. Expressing dc-link voltages of inverter-1 and

inverter-2 in terms of total dc-link voltage, as

(9)

(10)

Since the dc-link voltages of the two inverters are regulated, the

reference -axis voltage component is divided in between the

two inverters in proportion to their respective dc-link voltage as

(11)

(12)

For a given power, if

increases and

decreases. Therefore, power transfer to inverter-2 increases,

while it decreases for inverter-1. The power transfer to

inverter-2 is directly controlled, while for inverter-1, it is

controlled indirectly. Therefore, during disturbances, the

dc-link voltage of inverter-2 is restored to its reference quickly

compared to that of inverter-1. Using and , the reference

voltages are generated in stationary reference frame for

inverter-1 and using and for inverter-2. The reference

voltages generated for inverter-2 are in phase opposition to

that of inverter-1. From the reference voltages, gate signals are

generated using the sinusoidal pulse-width modulation (PWM)

technique [15]. Since the two inverters reference voltages

are in phase opposition, the predominant harmonic appears at

double the switching frequency.

C. Unbalanced Conditions

Network voltages are unbalanced due to asymmetric faults or

unbalanced loads [16]. As a result, negative-sequence voltage

appears in the supply voltage. This causes a double supply fre-

quency component in the dc-link voltage of the inverter. This

double frequency component injects the third harmonic com-ponent in the ac side [17]. Moreover, due to negative-sequence

voltage, large negative-sequence current flows through the in-

verter which may cause the STATCOM to trip [16]. Therefore,

during unbalance, the inverter voltages are controlled in such

a way that either negative-sequence current flowing into the in-

verter is eliminated or reduces the unbalance in the grid voltage.

In the latter case, STATCOM needs to supply large currents

since the interfacing impedance is small. This may lead to trip-

ping of the converter.

The negative-sequence reference voltage components of the

inverter and are controlled similar to positive-sequence

components in the negative synchronous rotating frame as [18]

(13)

(14)

where are - axes negative-sequence voltage compo-

nents of the supply and are - axes negative-sequence

current components of the inverter, respectively. The control pa-

rameters and are controlled as follows:

(15)

(16)

The reference values for negative-sequence current components

and are set at zero to block negative-sequence current

from flowing through the inverter.

III. STABILITYANALYSIS

Considering the dc side of the two inverters in Fig. 3, the

complete dynamics of the system are derived in the Appendix.

The transfer function is as follows:

(17)


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and the transfer function is

(18)

where and are given in the

Appendix.

From the transfer functions (26) and (27), it can be observed

that the denominator is a function of resistances ,

reactances , and modulation indices

and . Although the denominator includes an op-

erating condition term , the product

is always positive. Hence, the poles of transfer function always

lie on the left half of the -plane. However, numerators of the

transfer functions are functions of the operating conditions

of and . The positions of zeros primarily de-

pend on and . The sign of these variables changes

according to the mode of operation. Therefore, zeros of the

transfer functions shift to the right half of the -plane for certain

operating conditions. This system is said to be nonminimum

phase and there is a limit onachievable dynamic response[19].

The system may exhibit oscillatory instability when there is a

step change in reference for high controller gains. Therefore,

the controller gains should be designed suitably to avoid the

instability. This behavior is similar to that of the two-level

inverter-based STATCOM [20], [21].

The transfer function for 1.02 p.u.,

(capacitive mode) is given in (19), shown at the bottom of the

page. From (19), it can be observed that all poles as well as all

zeros lie on the left half of the -plane for this operating condi-

tion. Fig. 5 shows the frequency response of the transfer func-tion for the same operating condition. From

the figure, it can be observed that the system has sufficient gain

and phase margins for this operating condition. Fig. 6 shows an

enlarged root locus of the transfer function

when STATCOM is in inductive mode of operation. The reac-

tive component is set at 0.75 p.u. and proportional gain

is varied from 0 to 10. It can be seen that all poles lie on the

left half of the -plane for this case as well. However, one zero

shift to the right half and three zeros lie on the left half of the

-plane. Moreover, it can be seen that closed-loop poles of the

system shift to the right half of the -plane for high controller

gains.

IV. SIMULATION RESULTS

The system configuration shown in Fig. 1 is considered for

simulation. The simulation study is carried out using MATLAB/

SIMULINK. The system parameters are given in Table I.

Fig. 5. Frequency response at 1.02 p.u.,

80 p.u., 60 p.u.

Fig. 6. Root locus of the transfer function at 0.75p.u., 80 p.u., 60 p.u.

TABLE ISIMULATIONSYSTEM PARAMETERS

A. Reactive Power Control

In this case, reactive power is directly injected into the gridby setting the reference reactive current component at a par-

ticular value. Initially, is set at 0.5 p.u. At 2.0 s, is

changed to 0.5 p.u. Fig. 7(a) shows the source voltage and

converter current of the phase. Fig. 7(b) shows the dc-link

voltages of two inverters. From the figure, it can be seen that the

dc-link voltages of the inverters are regulated at their respective

(19)


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Fig. 7. Reactive power control. (a) Source voltage and inverter current.

(b) DC-link voltages of two inverters.

reference values when the STATCOM mode is changed from ca-

pacitive to inductive. Moreover, the dc-link voltage of inverter

2 attains its reference value faster compared to that of inverter

1 as discussed in Section II.

B. Load Compensation

In this case, the STATCOM compensates the reactive power

of the load. Initially, STATCOM is supplying a current of 0.5

p.u. At 2.0 s, the load current is increased so that STATCOM

supplies its rated current of 1 p.u. Fig. 8(a) shows source voltage

and converter current, while Fig. 8(b) shows the dc-link voltages

of two inverters. The dc-link voltages are maintained at their

respective reference values when the operating conditions are

changed.

C. Operation During the Fault Condition

In this case, a single-phase-to-ground fault is created at

1.2 s,on the phase ofthe HVside ofthe 33/11-kVtransformer.

The faultis cleared after 200 ms. Fig. 9(a) shows voltages across

the LV side of the 33/11-kV transformer. Fig. 9(b) and (c) shows

the - axes components of negative-sequence current of the

converter. These currents are regulated at zero during the fault

condition.

V. EXPERIMENTALRESULTS

A scaled down laboratory prototype is developed for the val-

idation of the proposed var compensation scheme. The exper-

imental setup consists of two insulated-gate bipolar transistor

(IGBT)-based two-level inverters connected in cascade on the

LV side of the 6-kVA, 200/400-V, three-phase transformer. The

Fig. 8. Load compensation. (a) Source voltage and inverter current.

(b) DC-link voltages of two inverters.

HV side of the transformer is connected to supply lines. The

transformer has resistance and leakage reactance of 5.1% and

3.6%, respectively. The control strategy is implemented using

TMS320F28335. The switching frequency is set at 1.2 kHz. The

dc-link voltages of inverters 1 and 2 are regulated at 88 V and

32 V, respectively. The source voltage is kept at 70 V(rms). The

reactive power is directly injected into the source by keeping

the reference current at a particular value.

A. Operation Under Balanced Voltage Conditions

a) Capacitive Mode of Operation: Initially, STATCOM is

set ina capacitive modeof operationby keeping at 7 A.The

waveforms for this operating condition are shown in Fig. 10.

Fig. 10(a) shows the source voltage and STATCOM current,

while Fig. 10(b) shows dc-link voltages of the two inverters.

Fig. 10(c) shows the harmonic spectrum of the STATCOM cur-

rent. From the harmonic spectrum, it can be seen that the pre-

dominant harmonic appears at double the switching frequency.

b) Inductive Mode of Operation: In this case, the dynamic

performance of the controller is verified by changing from 7

A to 7 A. Fig. 11(a) shows the variation of dc-link voltages of

two inverters. These voltages are maintained at their respective

reference values and the experimental result resembles the sim-

ulation result presented in the previous section. Fig. 11(b) shows

the response of STATCOM current during this disturbance.

B. Operation Under Unbalanced Voltage Conditions

a) Without Negative-Sequence Controller: In this case,

output of the STATCOM has only the positive-sequence volt-

ages. Unbalance in the supply voltages is created by connecting


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Fig. 9. Operation during fault. (a) Grid voltages on the LV side of the trans-

former. (b) -axis negative-sequence current component . (c) -axis nega-

tive-sequence current component .

an inductor in the phase. The reference current is set at

A. Fig. 12(a) shows the source voltages and converter currents.

From the figure, it can be seen that the converter currents are un-

balanced. Fig. 12(b) shows the dc-link voltages of the inverters.The waveforms pulsate at twice the supply frequency.

b) With Negative-Sequence Controller: In this case, the

negative-sequence controller represented by (13) and (14) is

enabled along with the positive-sequence controller. The ref-

erences for inverter negative-sequence current components

and are set at zero. Therefore, the inverter supplies balanced

currents as shown in Fig. 13(a). Fig. 13(b) shows the dc-link

voltages of two inverters. The oscillations in the dc-link voltages

of two inverters are reduced compared to those in Fig. 12(b).

VI. CONCLUSION

DC-link voltage balance is one of the major issues in cas-

caded inverter-based STATCOMs. In this paper, a simple var

Fig. 10. Experimental result: Capacitive mode of operation. (a) Source voltage(50 V/div) and STATCOM current (5 A/div). (b) DC-link voltages of inverter-1

and inverter-2 (20 V/div). Time scale: 5 ms/div. (c) Harmonic spectrum ofcurrent.

compensating scheme is proposed for a cascaded two-level in-

verter-based multilevel inverter. The scheme ensures regulationof dc-link voltages of inverters at asymmetrical levels and reac-

tive power compensation. The performance of the scheme is val-

idated by simulation and experimentations under balanced and

unbalanced voltage conditions. Further, the cause for instability

when there is a change in reference current is investigated. The

dynamic model is developed and transfer functions are derived.

System behavior is analyzed for various operating conditions.

From the analysis, it is inferred that the system is a nonmin-

imum phase type, that is, poles of the transfer function always

lie on the left half of the -plane. However, zeros shift to the

right half of the -plane for certain operating conditions. For

such a system, oscillatory instability for high controller gains

exists.


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Fig. 11. Experimental result: Mode change from capacitive to inductive.

(a) DC-link voltages of inverter-1 and inverter-2 (20 V/div). Time scale:100 ms/div. (b) Source voltage (100 V/div) and STATCOM current (5 A/div)

in steady state. Time scale: 100 ms/div.

APPENDIX

From Fig. 3, the ac-side dynamics are derived as

(20)

where

(21)

where are modulation indices, are phase angles

between inverters voltage and source voltage, and is the

supply frequency in radians per second. Substituting (21) in

(20), expressed in per unit

(22)

(23)

Fig. 12. Operation under unbalanced voltage conditions and without the neg-

ative-sequence controller: (a) Source voltages (20 V/div) and inverter currents(5 A/div). (b) DC-link voltages of inverter-1 and inverter-2 (20 V/div). Time

scale: 5 ms/div.

Fig. 13. Operation with a negative-sequence controller in capacitive mode of

operation. (a) Source voltages (20 V/div) and inverter currents(5 A/div). (b) DClink voltages of inverter-1 and inverter-2 (20 V/div). Time scale: 5 ms/div.


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Equating power on both sides of the inverter, the dc-side dy-

namics of two inverters in per unit, are derived as

(24)

(25)

In the equations, (22)(25), , and rep-

resent the per-unit quantities of , and

, respectively. The dynamic equations (22)(25) are

linearized, and transfer functions are derived. The transfer func-

tion is as follows:

(26)

where

The transfer function is

(27)

where and represent steady-state

values.

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N. N. V. Surendra Babu (S10M14) received theB.E. degree in electrical and electronics engineering

from Andhra University, Visakhapatnam India, in

1998, the M.Tech. degree in power and energysystems from Mangalore University, Mangalore,

Karnataka, in 2000, and the Ph.D. degree in powerelectronics from the Indian Institute of Technology

Bombay, Mumbai, India in 2013.His technical interests include power electronics,

machines, and power-electronicinterfaces for renew-

able energy sources.

B. G. Fernandes (M13) received the B.Tech.degree in electrical engineering from Mysore Uni-

versity, Mangalore, Karnataka, India, in 1984, the

M.Tech. degree in power electronics and machinedrives from the Indian Instiute of Technology (IIT)

Kharagpur in 1989, and the Ph.D. degree in powerelectronics and machine drives from the Indian

Institute of Technology Bombay, Mumbai, in 1993.He then joined IIT Kanpur as an Assistant Pro-

fessor. In 1997, he joined IIT Bombay where he iscurrently a Professor in the Department of Electrical

Engineering. His current research interests are high-performance ac drives, mo-

tors for electric vehicles, and power-electronic interfaces for nonconventionalenergy sources.

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Cascaded Two-Level Inverter-Based Multilevel