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Caprivi Link HVDC Interconnector: Comparison between energized system testing and real-time simulator testing
T G MAGG, PB Power, South Africa M MANCHEN, NamPower, Namibia
E KRIGE, NamPower, Namibia E KANDJII, NamPower, Namibia
R PÅLSSON, ABB, Sweden J WASBORG, ABB, Sweden
SUMMARY The Caprivi Link HVDC Scheme in Namibia, connects the ac networks of Namibia and Zambia with 950km of overhead line operating at -350kV dc. The 300MW monopole phase of the scheme was set into commercial operation in October 2010. The scheme has been planned for a future bipole extension to 600MW. The scheme utilises Voltage Sourced Converters (VSC) and is the first scheme to use VSC technology with overhead lines. The scheme connects two presently very weak ac networks where the fault levels are in the order of the rated power of the converters. This presented unique challenges in the studies and design phase of the scheme. As a final verification of the system studies and control and protection system performance, factory system testing and energized system testing were performed. The factory system test was performed with the complete control and protection software and hardware together with a real-time simulator with reduced ac network models which included machine dynamics. An extensive energized system testing program was performed during commissioning. Some important tests from the factory and field are presented, compared and discussed. The results of the energized system testing were in line with the factory system testing. KEYWORDS VSC HVDC – Control functions – Real time digital simulator – Reduced network models – Factory System Testing – Energized System Testing – Staged faults – Passive ac network
21, rue d’Artois, F-75008 PARIS Paper B4 107 2012 CIGRE 2012 http : //www.cigre.org
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1. OVERVIEW The Caprivi Link HVDC Interconnector is a 300 MW HVDC power transmission between the Zambezi 330 kV substation near Katima Mulilo in the Caprivi Strip of Namibia and the Gerus 400 kV substation near Otjiwarongo in the centre of Namibia with 950km of overhead line operating at -350kV dc. The scheme utilises Voltage Sourced Converters (VSC) and is the first scheme to use VSC technology with overhead lines. The link has been designed to allow for a future bipole extension to 600 MW in conjunction with ac network strengthening which is planned to connect Zambezi 330kV substation to Botswana and Zimbabwe. Commercial operation of the Caprivi Link Interconnector started in October 2010. Figure 1 shows the geographical location of the scheme in the southern African region with the major generating stations and transmission interconnections.
Figure 1: Geographical Location of the Caprivi Link Interconnector The CIGRE paper “Caprivi Link HVDC Interconnectior – The first VSC transmission with overhead lines” [1] provides an overview of the scheme and its features.
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2. MAIN CONTROL FUNCTIONS The main control functions of the Caprivi Link HVDC Interconnector are described below. Power control The active power can be selected from 0 to 300 MW import (power flow from Zambezi to Gerus), and up to 350 MW overload capability at low ambient temperatures, or from 0 to 280 MW export (power flow from Gerus to Zambezi), without power interruption when changing power direction. One converter station controls the active power constant and the other station controls the dc voltage constant during power transmission. AC voltage control AC voltage control is available in conjunction with active power transfer and provides voltage stability to the connected ac networks by generating reactive power to the ac grid or absorbing reactive power from the ac grid. The converters can also be operated without overhead line connection, SVC operation. During significant disturbances of the ac voltage, such as ac line faults, a more powerful transient ac voltage control is used for fast recovery. Passive or islanded network operation Passive or islanded ac network conditions are detected by frequency deviation criteria and the converter station connected to the passive/islanded network will be transferred from power control/dc voltage control to passive/islanded network operation with frequency control. The other converter station will control the dc voltage and needs to be connected to a normal, healthy ac network. DC line fault clearing After detection of a dc line fault, such as a lightning stroke, the converter valves are blocked immediately, the incoming ac circuit breakers are opened to interrupt the fault current through the diodes in the converter valves, most of the ac filters are disconnected to reduce the increase of the ac voltage and the dc pole breakers are opened to eliminate residual dc currents and to de-ionize the dc line. Then, the ac circuit breakers and ac filter breakers are re-closed, the converter valves de-blocked and SVC operation is resumed within 500 ms after fault detection. Finally the dc pole breakers are re-closed and active power transmission is resumed. 3. DYNAMIC PERFORMANCE STUDIES Dynamic performance studies (DPS) where performed using PSCAD. The main purpose of these studies was to determine the converter control system parameters and to verify dynamic performance requirements such as recovery following ac and dc line faults and transition to islanded ac networks. The networks close to the converter stations were modelled in detail while the rest of the network was reduced using the software E-TRAN. Different ac network configurations were studied; the initial extremely weak ac network as well as future stronger ac networks. 4. FACTORY AND ENERGIZED SYSTEM TESTING The factory system testing (FST) was performed as the final verification of the complete control and protection system software and hardware before shipment of the control cubicles to site. Since complex control features were to be implemented in extremely weak ac grids, exposed to instability problems, it was decided to perform a profound factory system testing. All simulation models have a degree of simplification. There is always a risk that the real ac networks will not behave exactly as simulated. For this reason, the FST was followed with an extensive energized system testing (EST) program during commissioning where several of the DPS and FST cases were repeated, such as such as staged ac and dc faults to earth and transition to passive/islanded ac networks.
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The EST, including trial operation, was performed during the period from the middle of May to the end of September 2010 as a final verification of the performance of the HVDC link before start of commercial operation. In the FST as detailed models of the ac grids as practically possible were implemented. The models included representative dynamics of machines. However, due to limitations of the simulation hardware, the ac grids had to be reduced. On the Zambezi side, the radial ac grid up to the Victoria Falls and Kafue Gorge power stations in Zambia were included, as well as the future ac line to the Hwange power station in Zimbabwe, while the rest of the grid was replaced with infinite sources. On the Gerus side, the meshed Namibian ac grid was reduced to a radial ac grid up to the Ruacana and Van Eck power stations, while the South African grid was replaced with an infinite source. The reduced ac grids represented the same impedance/frequency response up to the first pole and the same fault levels as used for the DPS. The validation of the reduced ac grids was done by verifying the load flows and short circuit levels with the complete network of the PSCAD model. Impedance plots of the reduced ac networks were matched for the first peak with the impedance plots of the complete networks of the PSCAD model, which was considered sufficient for the factory system testing purpose. The ac grids and the HVDC link were modelled in the RSCAD programming tool and used together with a real time digital simulator (RTDS) as solver. The results of the FST were in line with the DPS. 5. COMPARISON OF TEST RESULTS A sample of tests of interest performed both at the factory and in the field is presented below and is compared and discussed at the end of this clause:
• Step change responses (Figure 1 through 6) • Staged dc line fault (Figure 7 and 8) • Staged ac line fault (Figure 9 and 10) • Transition to passive ac network (Figure 11 and 12)
The most important quantities of the figures are explained in the legend below: Analog signals: Upcc AC voltage at point of common coupling Ipcc AC current at point of common coupling Ud, Udc DC voltage Idc DC current Ppcc Active Power at point of common coupling Qprimside Reactive power at primary side of converter transformer Omega Frequency*2� Digital signals (filled bar means activated): P-ctrl Active power control mode Uac-ctrl AC voltage control mode Transient mode Transient ac voltage control mode 3PWM Powerful switching pattern at transients Island det Passive/islanded ac network detected Island op Passive/islanded network operation control mode Indices: f Noise filtering of plotted value ref Reference value
4
Active power step response
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20.06
0.07
0.08
0.09
0.1
Pp
cc f
[pu
]
File: TFR CL_S1PCP1A1 1 20120109 10;47;15_052000.CFG
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2300
310
320
330
340
350
360
upc
c rm
s f [
kV]
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20.95
1
1.05
upc
c [p
u]
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2Time [s]
3PWM
P-ctrl
Uac-ctrl
Figure 1. Step of active power reference in FST
5
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.80.06
0.07
0.08
0.09
0.1
Pp
cc f
[pu
]File: TFR CL_S1PCP1A1 1 20100531 12;10;50_450000.CFG
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8300
310
320
330
340
350
360
upc
c rm
s f [
kV]
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.80.9
0.92
0.94
0.96
0.98
1
udc
[pu
]
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8Time [s]
3PWM
P-ctrl
Uac-ctrl
Figure 2. Step of active power reference in EST
6
DC voltage step respons
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20.9
0.92
0.94
0.96
0.98
udc
re
f [pu
] u
dc [
pu]
File: TFR CL_S2PCP1A1 1 20120109 13;18;41_647000.CFG
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2360
370
380
390
400
410
420
upc
c rm
s f [
kV]
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20
0.01
0.02
0.03
0.04
0.05
Pp
cc f
[pu
]
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2Time [s]
3PWM
P-ctrl
Uac-ctrl
Figure 3. Step of dc voltage reference in FST
7
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.40.9
0.92
0.94
0.96
0.98
udc
re
f [pu
] u
dc [
pu]
File: TFR CL_S2PCP1A1 1 20100531 12;54;36_292000.CFG
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4360
370
380
390
400
410
420
upc
c rm
s f [
kV]
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.40
0.01
0.02
0.03
0.04
0.05
Pp
cc f
[pu
]
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4Time [s]
3PWM
P-ctrl
Uac-ctrl
Figure 4. Step of dc voltage reference in EST
8
AC voltage step response
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0.9
0.91
0.92
0.93
0.94
0.95
0.96
0.97
upc
c re
f [p
u] u
pcc
f [p
u]
File: TFR CL_S2PCP1A1 1 20120109 11;37;37_494000.CFG
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2360
370
380
390
400
410
420
upc
c rm
s f [
kV]
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
Qpr
imsi
de [p
u]
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2Time [s]
3PWM
P-ctrl
Uac-ctrl
Figure 5. Step of ac voltage reference in FST
9
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60.94
0.96
0.98
1
1.02
upc
c re
f [p
u] u
pcc
f [p
u]
File: TFR CL_S2PCP1A1 1 20100527 16;48;54_664000.CFG
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6360
370
380
390
400
410
420
upc
c rm
s f [
kV]
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60.1
0.15
0.2
0.25
Qpr
imsi
de [p
u]
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6Time [s]
3PWM
P-ctrl
Uac-ctrl
Figure 6. Step of ac voltage reference in EST
10
Staged dc line fault
0 0.5 1 1.5 2 2.5 3 3.5 4-500
0
500
upcc
[kV
]
File: S1WMNN100M35DB_S1PCP1A1 1 20091124 20;26;10_792000.CFG
0 0.5 1 1.5 2 2.5 3 3.5 4
-1000
0
1000
ipcc
[A]
0 0.5 1 1.5 2 2.5 3 3.5 4-0.4
-0.2
0
0.2
0.4
Pp
cc [p
u] Q
prim
side
[pu]
0 0.5 1 1.5 2 2.5 3 3.5 4
0
0.5
1
udc
[pu
]
0 0.5 1 1.5 2 2.5 3 3.5 40
1000
2000
3000
idc
[A]
0 0.5 1 1.5 2 2.5 3 3.5 4Time [s]
BLOCKED W2W3Q1_CLOSED_IND W2W1Q1_CLOSED_IND W2W2Q1_CLOSED_IND
HP60_CLOSED_IND DCB_Q1_CLOSED_IND DCB_Q2_CLOSED_IND DCB_Q3_CLOSED_IND DCB_Q4_CLOSED_IND
Figure 7. DC line fault in FST
11
0 0.5 1 1.5 2 2.5 3 3.5 4-500
0
500
upcc
[kV
]
File: TFR CL_S1PCP1A1 1 20100607 17;22;16_623000.CFG
0 0.5 1 1.5 2 2.5 3 3.5 4
-1000
0
1000
ipcc
[A]
0 0.5 1 1.5 2 2.5 3 3.5 4-0.4
-0.2
0
0.2
0.4
Pp
cc [p
u] Q
prim
side
[pu]
0 0.5 1 1.5 2 2.5 3 3.5 4
0
0.5
1
udc
[pu
]
0 0.5 1 1.5 2 2.5 3 3.5 40
1000
2000
3000
idc
[A]
0 0.5 1 1.5 2 2.5 3 3.5 4Time [s]
BLOCKED W2W3Q1_CLOSED_IND W2W1Q1_CLOSED_IND W2W2Q1_CLOSED_IND
HP60_CLOSED_IND DCB_Q1_CLOSED_IND DCB_Q2_CLOSED_IND DCB_Q3_CLOSED_IND DCB_Q4_CLOSED_IND
Figure 8. DC line fault in EST
12
Staged ac line fault
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2-500
0
500
u
pcc
[kV
]
File: TFR CL_S1PCP1A1 1 20120109 14;52;49_795000.CFG
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-1000
0
1000
ipcc
[A]
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-0.5
0
0.5
Pp
cc [p
u]
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-0.4
-0.2
0
0.2
0.4
Qpr
imsi
de [p
u]
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0.6
0.8
1
udc
[pu
]
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2Time [s]
3PWM
Transient mode
Island det.
Island op.
Figure 9. AC line fault in FST
13
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8-500
0
500
upcc
[kV
]File: TFR CL_S1PCP1A1 1 20100607 23;24;09_092000.CFG
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
-1000
0
1000
ipcc
[A]
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
-0.6
-0.4
-0.2
0
0.2
0.4
Pp
cc [p
u]
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
-0.4
-0.2
0
0.2
0.4
Qpr
imsi
de [p
u]
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
0.6
0.8
1
udc
[pu
]
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8Time [s]
3PWM
Transient mode
Island det.
Island op.
Figure 10. AC line fault in EST
14
Transition to passive ac network
1 2 3 4 5 6 7-500
0
500
upcc
[kV
]
File: 4_S1WMNN100ZB_S1PCP1A1 1 20091203 11;27;09_340000.CFG
1 2 3 4 5 6 7
-1000
0
1000
ipcc
[A]
1 2 3 4 5 6 7
-0.6
-0.4
-0.2
0
0.2
0.4
Pp
cc [p
u]
1 2 3 4 5 6 7
-0.4
-0.2
0
0.2
0.4
Qpr
imid
e [p
u]
1 2 3 4 5 6 7100
200
300
400
500
Om
ega
[rad
]
1 2 3 4 5 6 7Time [s]
P-ctrl
Island det.
Island op.
Figure 11. Transition to passive ac network in FST
15
0 1 2 3 4 5 6 7 8-500
0
500
upcc
[kV
]File: TFR CL_S1PCP1A1 1 20100606 11;00;02_925000.CFG
0 1 2 3 4 5 6 7 8
-1000
0
1000
ipcc
[A]
0 1 2 3 4 5 6 7 8
-0.6
-0.4
-0.2
0
0.2
0.4
Pp
cc [p
u]
0 1 2 3 4 5 6 7 8
-0.4
-0.2
0
0.2
0.4
Qpr
imsi
de [p
u]
0 1 2 3 4 5 6 7 8100
200
300
400
500
Om
ega
[rad
]
0 1 2 3 4 5 6 7 8Time [s]
P-ctrl
Island det.
Island op.
Figure 12. Transition to passive network in EST
16
Comparison of step change response tests Step change response testing is a basic method to verify system stability. An active power step was applied at Zambezi and ac and dc voltage steps were applied at Gerus. These tests demonstrated similar and well damped behaviour in both FST and EST. However, the response of the ac grid was slightly different in EST compared to FST since there was a minor decay of the real ac voltage after the initial voltage rise. The result of this decay of ac voltage was that the ac voltage controller needed a bit longer time to null the error between the new ac voltage reference and the measured ac voltage. Comparison of staged dc line faults The dc line fault was performed at higher power level in FST than in EST, which caused a higher increase of the ac voltage due to load rejection. Otherwise the responses of the ac and dc system were similar. The digital bars show the blocking of the converter valve and the position of the ac circuit breaker and dc pole breakers at one of the converter stations. As seen, the blocking and de-blocking of the converter valve, and open and re-close sequence of the circuit breakers look about the same as in the simulator. Comparison of staged ac line faults The staged single phase ac line fault on the incoming ac line from Zambia at Zambezi in EST resulted in a transition to passive ac network due to incorrect operation of the ac line protection. The dc system recovered as expected and changed to passive/islanded network operation. The oscillation of dc voltage was very similar in both FST and EST. The behaviour of the active and reactive power flow from the converter station was similar initially, before the islanding occurred. Comparison of transitions to passive network Transition to supply of the passive network at Zambezi was done in EST by manually disconnecting the incoming ac line from Zambia during import of power to Namibia. In FST this was done by applying a single phase ac line fault followed by unsuccessful operation of the auto-reclosure scheme. In both FST and EST the transition to passive/islanded network operation at Zambezi was successful. However, this transition took longer time in FST resulting in a larger frequency deviation than in EST. The reason was that the condition for detection of passive or islanded ac network includes a condition that the ac voltage should be normal, in order not to transfer to passive/islanded network operation at ac line faults. 6. CONCLUSION The experience of the Caprivi Link HVDC Interconnector project is that a real-time digital simulator with reduced network models is a powerful tool to verify dynamic performance at factory system testing and reduce the time for commissioning. The reduced network models used in the factory system testing have been proved to represent the real ac grids with sufficient accuracy. Some minor problems in the coordination between the control system and HVDC/ac network protections were picked up during the energised system testing. These were not picked up in the factory system testing due to the limitations of full modelling of some of the components and full representation of protections in the ac networks. This highlights the importance of performing energised system testing, including staged ac and dc faults, in addition to factory system testing of the control and protection equipment. In general the energized system testing performed during commissioning of the Caprivi Link HVDC Interconnector was in line with the factory system testing and no major changes of the converter control was necessary. BIBLIOGRAPHY [1] CIGRE SCB4 Colloquium, Brisbane, Australia, 2011: Caprivi Link HVDC Interconnector –
The first VSC transmission with overhead lines
