Capacitive Touch Controller CMT126

CMT126 Capacitive Touch Controller for Large-sized Screen Revision 0.3 – Apr. 2020

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Product Datasheet CMT126DS

www.cubermotive.com

Copyright © 2020, Cubermotive

1. Features

Max 126 channels for capacitive touch panel (Tx 46 channels & Rx 80 channels)

Mutual capacitance and self-capacitance sensing

Max 150Hz report rate

Tx output drive voltage: 24V

High resolution ADC & 12-bit resolution touch position reporting

Ultra-low noise AFE and digital filter

ARM Cortex-M3 32-bit MCU

128KB SRAM

128KB EEPROM with ECC(16KB)

Input voltage level detection

Input voltage power on reset

Communication interface: I2C, UART, SPI and USB2.0

Internal clock generators & PLL

Wide supply voltage range: 3.0 – 5.5V

2. Applications

All around middle to large-sized industrial touch screen modules

Self-service KIOSK & POS terminal touch screen modules

Home appliances & IoT devices

Outdoor display solutions

Touch modules used in a high environmental electronic noise

3. Description

The CMT126 is a capacitive touch sensor controller optimized for large interactive displays such

as KIOSK, digital signage, smart appliances, smart boards, and so on. It offers the most efficient

way to develop and optimize a mutual capacitive multi-touch screen ranging from mid to large

screen applications. It detects the electric signal changes of the touch screen when it was touched

with a finger or stylus or glove, and calculates their coordinates precisely.

The CMT126 integrates total 126 channels of receivers and high voltage output signal drivers, low

noise amplifiers, high order LPFs(low pass filters), high resolution ADCs, digital signal processing

unit(DSP), internal clock generators, LDOs, high voltage charge pump and 32-bit high

performance ARM Cortex-M3 MCU.

Low noise AFE(Analog Front-End) amplifiers detect the analog signal changes of the touch panel.

High order LPFs(low pass filters) remove interferences and high frequency noises. High resolution

ADCs(Analog-to-Digital Converters) convert the analog signals to the digital signals. The values of

the digital signals vary depending on the presence or absence of touches, and increased number

of transmitter and receiver channels on the same panel size also increases accuracy of calculation

of touch locations.

ARM Cortex-M3 MCU governs custom firmware including SRAM data memory, EEPROM memory,


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internal oscillators and internal regulators, and performs signal processing of digital outputs from

ADCs, and finally calculates coordinates of the touch locations. UART, USB, I2C and GPIO are for

communication with the external HOST. Embedded flexible power management algorithm provides

various power supply options and optimizes power consumption at operating mode. Using this

feature, users can generate more flexible, customized touch screen configuration.

One of the most important features of the capacitive touch screen controller technology is to

suppress many different types of noises generated by external sources such as fluorescent lamps,

LCD display, electro-magnetic radiation. Cubermotive’s proprietary technologies, such as ultra-low

noise AFE and smart filtering, suppress external noises efficiently and prevent system from

malfunctioning.

The CMT126 is offered in a 192-ball BGA package, and supports up to 126 Tx/Rx channels. When

designing a capacitive touch screen, please refer to the Design Guide to optimize your design and

maximize touch panel performance.

Table of Contents

1. Features…………………..…………………….1

2. Applications……………………….…………….1

3. Description………………………………………1

4. Revision History…………………………...……2

5. Pin Configurations and Functions………...…..2

5.1 Pin Configuration……………………….….2

5.2 Pin Functions……………………………….3

6. Electrical Characteristics………………………8

6.1 Absolute Maximum Ratings……………....8

6.2 ESD Ratings………………………………..9

6.3 Recommended Operating Conditions…...9

6.4 DC Specifications………………………....9

6.5 USB DC Specifications……………………9

6.6 Crystal Characteristics……………….…10

7. Block Diagram………………………..……….10

8. Application……………………………………11

8.1 5V Power Supply & USB Connection…11

8.2 3.3V Power Supply & I2C or SPI

Connection………………………..………12

8.3 Multichip Connection…………………….13

9. Orderable Information………………….…….13

10. Package Information…………………….……14

4. Revision History

Date Revision Notes

April 2020 A Preliminary

June 2020 0.3 Release version


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5. Pin Configuration and Functions

5.1. Pin Configuration

The package is a 9mm x 9mm 192-ball CVBGA with 0.5mm ball pitch in a 17 x 17 grid.

192-ball CVBGA Package

RX43 RX44 RX46 RX48 RX52 RX56 RX60 RX64 RX68 RX72 RX76 VSS NC NC NC NC NC

RX42 RX45 RX47 RX49 RX53 RX57 RX61 RX65 RX69 RX73 RX77 VSS NCVDD

CPVDD5

VDD

30NC

RX40 RX41 NC NC

RX38 RX39 RX50 RX54 RX58 RX62 RX66 RX70 RX74 RX78 VSS TX3 TX2 TX1 TX0

RX36 RX37 RX51 RX55 RX59 RX63 RX67 RX71 RX75 RX79 VSS TX7 TX6 TX5 TX4

RX32 RX33 RX34 RX35 TX11 TX10 TX9 TX8





RX13 RX14 RX15 VSS TX31 TX30 TX29 TX28

RX10 RX11 RX12 VSS TX35 TX34 TX33 TX32

RX7 RX8 RX9 VSS DP TST MS0SPM_

CSN1

SPM_

MISO1

SPI_

CLK

JTAG

_MXGPIO3

GPIO7

_RXDTX37 TX36

RX4 RX5 RX6 VSS DN RSTB MS1SPM_

CSN0

SPM_

MISO0

SPI_

CSN

HOST

_

SEL

GPIO2GPIO6

_TXDTX39 TX38

RX2 RX3 TX41 TX40

RX1VDD

3AVBUS

VDD

CKNC NC NC KICK MRST

SPM_

CLK

SPM_

MOSI0

SPI_

MOSIGPIO1 GPIO5 VSS TX43 TX42

RX0 VDDAVDD

18

VDD

3DVDDD XOUT XIN DONE DRV

SPM_

CSN2

SPM_

MISO2

SPI_

MISOGPIO0 GPIO4

VDD

IOTX45 TX44

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

TOP VIEW

Figure 1. Pin Configuration

5.2. Pin Functions

Table 1. Pin Functions

NAME BALL No I/O TYPE DESCRIPTION

RSTB P7 I External reset; active high

VSS A12 I GND Ground, star connection in PKG

VSS B12 I GND Ground, star connection in PKG


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VSS D12 I GND Ground, star connection in PKG

VSS E12 I GND Ground, star connection in PKG

VSS L5 I GND Ground, star connection in PKG

VSS M5 I GND Ground, star connection in PKG

VSS N5 I GND Ground, star connection in PKG

VSS P5 I GND Ground, star connection in PKG

VSS T15 I GND Ground, star connection in PKG

VDD3D U4 I Power Input power supply (3.0 ~ 5.5V); connect a bypass capacitor 2.2-μF to VSS

VDD3A T2 I Power Input power supply (3.0 ~ 5.5V); connect a bypass capacitor 2.2-μF to VSS

VDDIO U15 I Power Input power supply (3.0 ~ 5.5V) for interfaces; connect a bypass capacitor 2.2-μF to VSS

VDD18 U3 O Power 1.8V output power supply of internal LDO; connect a bypass capacitor 2.2-μF to VSS

VBUS T3 I Power Input USB power supply (4.5 ~ 5.5V) for interfaces; connect a bypass capacitor 2.2-μF to VSS

VDDCP B14 I Power Input power supply (3.0 ~ 5.5V); connect a bypass capacitor 2.2-μF to VSS

VDDCK T4 O Power Output power supply of internal LDO; connect a bypass capacitor 2.2-μF to VSS

VDDD U5 O Power Output power supply of internal LDO; connect a bypass capacitor 2.2-μF to VSS

VDDA U2 O Power Output power supply of internal LDO; connect a bypass capacitor 2.2-μF to VSS

VDD5 B15 O Power Output power supply of charge pump; connect a bypass capacitor 2.2-μF to VSS

NC O N/C No connection

VDD30 B16 O Power Output power supply of charge pump; connect a bypass capacitor 2.2-μF to VSS

NC A13-A17 O N/C No connection (A13, A14, A15, A16, A17, B13, B17,C16, C17)

XIN U7 I CLK XTAL input clock signal

XOUT U6 O CLK XTAL output clock signal

DP N6 I/O - Input differential data signal of USB

DN P6 I/O - Input differential data signal of USB

TST N7 I Test-mode selection; connect to VSS

SPI_CLK N11 I SPI clock and I2C SCL

SPI_CSN P11 I/O SPI CSN and GPIO[0]

SPI_MISO U12 I/O SPI data output and I2C SDA

SPI_MOSI T12 I/O SPI data input and GPIO[1]

HOST_SEL P12 I SPI / I2C selection

JTAG_MX N12 I JTAG Mux; connect to VSS.

GPIO0 U13 I/O GPIO[2], PWM[0] and UART_RX

GPIO1 T13 I/O GPIO[3], PWM[1] and UART_TX

GPIO2 P13 I/O GPIO[4] and PWM[2]

GPIO3 N13 I/O GPIO[5] and PWM[3]

GPIO4 U14 I External reset; connect to VDDIO

GPIO5 T14 I External clock input for test mode; connect to VSS

GPIO6_TXD P14 I/O GPIO[6] and TXD


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GPIO7_RXD N14 I/O GPIO[7] and RXD

MS0 N8 I Master / Slave selection; #0 for multi-chip

MS1 P8 I Master / Slave selection; #1 for multi-chip

KICK T8 I/O GPIO[8] & Start pulse hand-shaking interface for multichip

DONE U8 I/O GPIO[9] & Done pulse hand-shaking interface for multichip

DRV U9 I/O GPIO[10] & Driving information for multichip

MRST T9 I/O GPIO[11] & ADC RESET information for multichip

SPM_CSN0 P9 O SPM chip selection for multichip

SPM_CSN1 N9 I/O GPIO[12] & SPM chip selection for multichip

SPM_CSN2 U10 I/O GPIO[13] & Done pulse hand-shaking interface for multichip

SPM_MISO0 P10 I/O SPM0 data input for multichip and I2CM SDA

SPM_MISO1 N10 I/O GPIO[14] & SPM1 data input for multichip

SPM_MISO2 U11 I ECC bypass mode selection

SPM_MOSI0 T11 O SPM0 data output

SPM_CLK T10 I/O SPM clock for multichip and I2CM SCL

NC T5 N/C No connection



RX0 U1 I I/O Channel RX0

RX1 T1 I I/O Channel RX1

RX2 R1 I I/O Channel RX2

RX3 R2 I I/O Channel RX3

RX4 P1 I I/O Channel RX4



RX7 N1 I I/O Channel RX7



RX10 M1 I I/O Channel RX10



RX13 L1 I I/O Channel RX13



RX16 K1 I I/O Channel RX16




RX20 J1 I I/O Channel RX20




RX24 H1 I I/O Channel RX24



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RX28 G1 I I/O Channel RX28




RX32 F1 I I/O Channel RX32




RX36 E1 I I/O Channel RX36


RX38 D1 I I/O Channel RX38


RX40 C1 I I/O Channel RX40

RX41 C2 I I/O Channel RX41

RX42 B1 I I/O Channel RX42

RX43 A1 I I/O Channel RX43





























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TX0 D17 I/O HV I/O channel TX0




TX4 E17 I/O HV I/O channel TX4




TX8 F17 I/O HV I/O channel TX8




TX12 G17 I/O HV I/O channel TX12




TX16 H17 I/O HV I/O channel TX16




TX20 J17 I/O HV I/O channel TX20




TX24 K17 I/O HV I/O channel TX24




TX28 L17 I/O HV I/O channel TX28




TX32 M17 I/O HV I/O channel TX32





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TX36 N17 I/O HV I/O channel TX36

TX37 N16 I/O HV I/O channel TX37

TX38 P17 I/O HV I/O channel TX38

TX39 P16 I/O HV I/O channel TX39

TX40 R17 I/O HV I/O channel TX40

TX41 R16 I/O HV I/O channel TX41

TX42 T17 I/O HV I/O channel TX42

TX43 T16 I/O HV I/O channel TX43

TX44 U17 I/O HV I/O channel TX44

TX45 U16 I/O HV I/O channel TX45

NC A13~A17 - N/C No connection

NC B13, B17 - N/C No connection

NC C16, C17 - N/C No connection

Pin Functionality Definitions

I: Input

O: Output

I/O: Input/Output

GND: Ground

HV: High Voltage output

N/C: No Connection

6. Electrical Characteristics

6.1. Absolute Maximum Ratings

PARAMETER SYMBOL MIN MAX UNIT

USB Power supply voltage VBUS -0.5 6 V

VDD3D to GND VDD3D -0.5 6 V

VDD3A to GND VDD3A -0.5 6 V

VDDIO to GND VDDIO -0.5 6 V

VDDCP to GND VDDCP -0.5 6 V

VDD to GND VDD30 -0.5 35 V

Input Voltage Vi -0.5 6 V

Output Voltage Vo -0.5 6 V

Operating Junction Temperature Tj -40 125 ℃

Storage Temperature Tstg -40 150 ℃

6.2. ESD Ratings

VALUE UNIT

V(ESD) Electrostatic Discharge HBM (Human Body Model) 2000 V

MM (Machine Model) 200 V


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6.3. Recommended Operating Conditions

PARAMETER SYMBOL MIN NOM MAX UNIT

VBUS to GND VBUS 4.5 5.0 5.5 V

VDD3D to GND VDD3D 3.0 3.3 5.5 V

VDD3A to GND VDD3A 3.0 3.3 5.5 V

VDDIO to GND VDDIO 1.65 3.3 5.5 V

VDDCP to GND VDDCP 3.0 3.3 5.5 V

Operating Ambient Temperature Range TA -40 25 85 ℃

6.4. DC Specifications


USB input power supply voltage VBUS 4.5 5 5.5 V

Digital input power supply voltage VDD3D 3.0 3.3 5.5 V

Analog input power supply voltage VDD3A 3.0 3.3 5.5 V

Charge pump input power supply voltage VDDCP 3.0 3.3 5.5 V

Interface input power supply voltage VDDIO 1.65 3.3 5.5 V

Digital 1.5V LDO output voltage VDDD 1.35 1.5 1.65 V

Analog 1.5V LDO output voltage VDDA 1.35 1.5 1.65 V

Clock 1.5V LDO output voltage VDDCK 1.35 1.5 1.65 V

1.8V LDO output voltage VDD18 1.62 1.8 1.98 V

6.5. USB DC Specifications

PARAMETER SYMBOL MIN MAX UNIT

Hi-Z State Data Line Leakage Current ILO -10 10 uA

Standby Current IDDS 20 uA

Operating Supply Current IOP 8 mA

Input Voltage Difference VDI 0.2 V

Differential Common-Mode Voltage Range VCM 0.8 2.5 V

Low-level Single-ended Input Voltage VSEL 0.8 V

High-level Single-ended Input Voltage VSEH 2.0 V

Low-level Static Output Voltage VSOL 0.3 V

High-level Static Output Voltage VSOH 2.8 V

Low-level Output-Voltage VOL 0.3 V

High-level Output-Voltage VOH 2.8 V


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6.6. Crystal Characteristics


Input Clock Frequency XIN NOM–1% 12 NOM+1% MHz

7. Block Diagram

AH

B B

US

matrix

ARMCortex-M3

EEPROM

SRAM

DMA

USB

AP

B

SUB I2C

GPIO

TIMER

PWM

WDT

Peripherals

Analog

System

Interface

General

Memory

Registers

Touch Core

Controller

DSP

I2C / SPI

POWER

POR

MUX

Analog

Front-End

Analog

Signal

Processing

ADC

Analog Core

OSC & PLL

SCAN

MBIST

ClockControl

PMU

Touch Panel CMT126

Figure 2. Functional Block Diagram


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8. Application

8.1. 5V Power Supply & USB Connection

VBUS

2.2 μF

VDD3D

2.2 μF

2.2 μF

3.3 V

LDO

5 V

1.0 μF

10 kΩ

4.7 kΩ

VDDIO

4.7 kΩ

12 MHz

I2C to HOST

USB to HOST

2.2 μF

VDDIO

10 pF

10 pF

VBUS VDD18

VDD30

VDD3D

VDD3A

VDDCP

RSTB

2.2 μF

VDDCK2.2 μF

VDDD2.2 μF

VDDA2.2 μF

TST

SPI_CLK (SCL)

SPI_MISO (SDA)

HOST_SEL

DP

DN

GPIO<0:7>

XIN

XOUT

VSS

MS<0:1>

KICK

DONE

DRV

MRST

SPM_CSN<0:2>

Fo

r mu

lti-ch

ip

so

lutio

ns

X<0:45>

Y<0:79>

CMT126

VDD5

2.2 μF(50 V)

VDDIO

SPM_MISO<0:1>

SPM_MOSI0

JTAG_MX

SPI_MOSI

SPI_CSN

SPM_MISO2 VDDIO

SPM_CLK

1 MΩ

24V

Figure 3. Application Schematic for USB


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8.2. 3.3V Power Supply & I2C or SPI Connection

VBUS

2.2 μF

VDD3D

2.2 μF

2.2 μF

3.3 V

LDO

5 V

1.0 μF

10 kΩ

4.7 kΩ

VDDIO

4.7 kΩ

I2C to HOST

2.2 μF

VDDIO

VBUS VDD18

VDD30

VDD3D

VDD3A

VDDCP

RSTB

2.2 μF

VDDCK2.2 μF

VDDD2.2 μF

VDDA2.2 μF

TST

SPI_CLK (SCL)

SPI_MISO (SDA)

HOST_SEL

DP

DN

GPIO<0:7>

XIN

XOUT

VSS

MS<0:1>

KICK

DONE

DRV

MRST

SPM_CSN<0:2>

Fo

r mu

lti-ch

ip

so

lutio

ns

X<0:45>

Y<0:79>

CMT126

VDD5

2.2 μF(50 V)

VDDIO

SPM_MISO<0:1>

SPM_MOSI0

JTAG_MX

SPI_MOSI

SPI_CSN

SPM_MISO2 VDDIO

SPM_CLK

24V

Figure 4. Application Schematic for I2C


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8.3. Multichip Connection

TEST

SPI_CLK (SCL)

SPI_MISO (SDA)

4.7 kΩ

HOST_SEL

VDDIO

4.7 kΩ

DP

DN

I2C or SPI to HOST

USB to HOST

MS<1>

KICK

DONE

DRV

MRST

SPM_MOSI0

X<0:45> Y<0:79>

CMT126Master (MS<1:0> = '00')

SPM_MISO<0>

SPM_CLK

MS<0>

SPI_CSN

SPI_MOSI

Master Sensing Area Slave Sensing Area

MS<0>

MS<1>

Y<0:79> X<0:45>

CMT126Slave (MS<1:0> = '01')

DONE

SPM_CSN<0> SPI_CSN

SPI_CLK (SCL)

SPI_MISO

SPI_MOSI4.7 kΩ

VDDIO

KICK

DRV

MRST

VDDIO

Figure 5. Application Schematic for Multichip Connection

9. Orderable Information

Orderable Device

Status Package

Type Balls Grid Size

Package Size

Ball Finish Eco Plan

CMT126 Sampling CVBGA 192 17 x 17 9 x 9 x 1 mm NiAu RoHS


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10. Package Information

Figure 6. Amkor Technology 192-b CVBGA Package Outline

IMPORTANT NOTICE AND DISCLAIMER No Implied Licenses Nothing contained herein shall be construed as conferring by implication, estoppel, or otherwise any license or right under any patent, trademark, copyright, or proprietary rights of Cubermotive or of any third party. No Warranties Cubermotive has made reasonable efforts to ensure the accuracy of the information contained in this Web site. However, it is presented AS IS and Cubermotive makes no warranties, conditions, or representations of any kind, either express or implied, with respect to the content, the products listed herein, or the completeness or accuracy of this document. In No Event Shall Cubermotive be liable to any person for any special, incidental, indirect or consequential damages, arising out of or in connection with the use or performance of the information presented herein. Updates and Changes Cubermotive reserves the right to change the content of this Web site or modify the design or characteristics of any product/service described herein at any time without prior notice.

Documents

Capacitive Touch Controller CMT126